Field effect transistor and method for manufacturing the same

Abstract

The present invention provides a field effect transistor and a manufacturing method thereof. In the manufacturing method of the field effect transistor, the input-output device region on both sides of the first gate structure is first etched to form a first source-drain groove, and then the core device region on both sides of the second gate structure is etched to form a second source-drain groove, thereby the critical dimensions of the first source-drain groove and the second source-drain groove can be controlled respectively, that is, the contour of the first source-drain groove and the contour of the second source-drain groove can be controlled, so that the critical dimension of the first source-drain groove is larger than the critical dimension of the second source-drain groove, the maximum electric field can be kept away from the channel of the input-output device region, thereby reducing the electric field strength near the channel, thereby improving the reliability of the formed device. In addition, the requirements of different operating voltages of the core device region and the input-output device region can be met, thereby facilitating the improvement of the overall performance and reliability of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a field effect transistor and a manufacturing method thereof. Background Art

[0002] At present, in the manufacturing process of field effect transistors, source and drain grooves are etched in the core device area and input and output device area of ​​the substrate as source and drain areas, and a germanium silicon epitaxial layer is formed in the source and drain grooves. The substrate along the channel direction is compressed by the germanium silicon epitaxial layer to generate compressive stress, thereby improving the hole mobility in the channel and further improving the performance of the device. However, since the materials of the germanium silicon epitaxial layer and the substrate are different, it is easier to cause dislocation defects. In addition, since the critical dimensions of the source and drain grooves will affect the profile of the germanium silicon epitaxial layer, it will affect the performance of the source and drain areas in the core device area and the input and output device area, and further affect the reliability of the device. Summary of the invention

[0003] The object of the present invention is to provide a field effect transistor and a method for manufacturing the same, so as to improve the reliability of the device.

[0004] To achieve the above-mentioned object, the present invention provides a method for manufacturing a field effect transistor, comprising: providing a substrate, the substrate comprising an input-output device region and a core device region, a first gate structure being formed on the input-output device region, and a second gate structure being formed on the core device region; etching the input-output device region on both sides of the first gate structure to form a first source-drain trench; etching the core device region on both sides of the second gate structure to form a second source-drain trench, wherein the critical dimension of the first source-drain trench is greater than the critical dimension of the second source-drain trench; sequentially forming a first epitaxial layer, a second epitaxial layer and a silicon cap layer, the first epitaxial layer covering the inner surface of the first source-drain trench and the second source-drain trench, the second epitaxial layer covering the first epitaxial layer and filling the first source-drain trench and the second source-drain trench, and the silicon cap layer covering the second epitaxial layer, wherein the first epitaxial layer, the second epitaxial layer and the silicon cap layer in the first source-drain trench constitute a first source-drain region, and the first epitaxial layer, the second epitaxial layer and the silicon cap layer in the second source-drain trench constitute a second source-drain region.

[0005] Optionally, the material of the first epitaxial layer and the material of the second epitaxial layer are both germanium silicon, and the germanium content in the second epitaxial layer is greater than the germanium content in the first epitaxial layer.

[0006] Optionally, the germanium content in the first epitaxial layer gradually increases from the bottom surface to the top surface of the first epitaxial layer, and the germanium content in the first epitaxial layer is 1%-5%.

[0007] Optionally, the germanium content in the second epitaxial layer gradually increases from the bottom surface to the top surface of the second epitaxial layer, and the germanium content in the second epitaxial layer is 20%-40%.

[0008] Optionally, the first epitaxial layer, the second epitaxial layer and the silicon cap layer are all doped with boron ions, the concentration of boron ions in the silicon cap layer is greater than the concentration of boron ions in the second epitaxial layer, and the concentration of boron ions in the second epitaxial layer is greater than the concentration of boron ions in the first epitaxial layer.

[0009] Optionally, the shape of the second source-drain trench and the shape of the first source-drain trench are both Σ-shaped, the sidewalls of the first source-drain trench and the sidewalls of the second source-drain trench both have pointed tips, the tip of the first source-drain trench faces the first gate structure, and the tip of the second source-drain trench faces the second gate structure.

[0010] Optionally, the critical dimensions of the first source-drain groove include the tip depth of the first source-drain groove, the tip proximity of the first source-drain groove, and the width of the first source-drain groove opening; the critical dimensions of the second source-drain groove include the tip depth of the second source-drain groove, the tip proximity of the second source-drain groove, and the width of the second source-drain groove opening.

[0011] Optionally, the method for forming the first source-drain groove includes: forming a first patterned photoresist layer on the substrate, the first patterned photoresist layer exposing the input-output device area on both sides of the first gate structure; using the first patterned photoresist layer as a mask to perform lightly doped drain ion implantation on the input-output device area on both sides of the first gate structure; using the first patterned photoresist layer as a mask, etching the exposed input-output device area by a dry etching process to form a first opening, the first opening being U-shaped; using the first patterned photoresist layer as a mask, etching the input-output device area at the bottom of the first opening by a wet etching process to form the first source-drain groove; and removing the first patterned photoresist layer.

[0012] Optionally, the method for forming the second source-drain groove includes: forming a second patterned photoresist layer on the substrate, the second patterned photoresist layer filling the first source-drain groove and exposing the core device area on both sides of the second gate structure; etching the exposed core device area using a dry etching process to form a second opening, the second opening is U-shaped, wherein the width of the first opening is greater than the width of the second opening, and the depth of the first opening is greater than the depth of the second opening; etching the core device area at the bottom of the second opening using a wet etching process to form the second source-drain groove; and removing the second patterned photoresist layer.

[0013] Based on the same inventive concept, the present invention also provides a field effect transistor, comprising: a substrate, the substrate comprising an input-output device region and a core device region, a first gate structure is formed on the input-output device region, a second gate structure is formed on the core device region, first source-drain trenches are formed in the input-output device regions on both sides of the first gate structure, second source-drain trenches are formed in the core device regions on both sides of the second gate structure, and a critical dimension of the first source-drain trench is greater than a critical dimension of the second source-drain trench; a first epitaxial layer, the first epitaxial layer covers the inner surface of the first source-drain trench and the second source-drain trench; a second epitaxial layer, the second epitaxial layer covers the first epitaxial layer and fills the first source-drain trench and the second source-drain trench; a silicon cap layer, the silicon cap layer covers the second epitaxial layer; wherein the first epitaxial layer, the second epitaxial layer and the silicon cap layer in the first source-drain trench constitute a first source-drain region, and the first epitaxial layer, the second epitaxial layer and the silicon cap layer in the second source-drain trench constitute a second source-drain region.

[0014] In the manufacturing method of the field effect transistor provided by the present invention, the input-output device region on both sides of the first gate structure is first etched to form a first source-drain groove, and then the core device region on both sides of the second gate structure is etched to form a second source-drain groove, thereby the critical dimensions of the first source-drain groove and the second source-drain groove can be controlled respectively, that is, the contour of the first source-drain groove and the contour of the second source-drain groove can be controlled, so that the critical dimension of the first source-drain groove is larger than the critical dimension of the second source-drain groove, and the maximum electric field can be kept away from the channel of the input-output device region, thereby reducing the electric field intensity near the channel, thereby improving the reliability of the formed device. In addition, since the critical dimension of the first source-drain groove of the input-output device region is larger than the critical dimension of the second source-drain groove of the core device region, the critical dimension of the first source-drain region of the subsequently formed input-output device region can be larger than the critical dimension of the second source-drain region of the core device region, thereby meeting the requirements of different operating voltages of the core device region and the input-output device region (the operating voltage of the input-output device region is larger than the operating voltage of the core device region), thereby facilitating the improvement of the overall performance and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic flow chart of a method for manufacturing a field effect transistor according to an embodiment of the present invention.

[0016] Figure 2 It is a schematic structural diagram after the first opening is formed in the method for manufacturing the field effect transistor according to an embodiment of the present invention.

[0017] Figure 3 It is a schematic diagram of the structure after the first source-drain trench is formed in the method for manufacturing the field effect transistor according to an embodiment of the present invention.

[0018] Figure 4 It is a schematic structural diagram after the first patterned photoresist layer is removed in the method for manufacturing a field effect transistor according to an embodiment of the present invention.

[0019] Figure 5 It is a schematic structural diagram after the second opening is formed in the method for manufacturing the field effect transistor according to the embodiment of the present invention.

[0020] Figure 6 It is a schematic diagram of the structure after the second source-drain trench is formed in the method for manufacturing the field effect transistor according to an embodiment of the present invention.

[0021] Figure 7 It is a schematic diagram of the structure after a silicon cap layer is formed in the method for manufacturing a field effect transistor according to an embodiment of the present invention.

[0022] Among them, the figure numbers are explained as follows: 100-substrate; 100a-input and output device area; 100b-core device area; 110-first gate structure; 111-first gate; 112-first silicon oxide sidewall; 113-first silicon nitride sidewall; 120-second gate structure; 121-second gate; 122-second silicon oxide sidewall; 123-second silicon nitride sidewall; 130-first patterned photoresist layer; 140-first opening; 141-first source and drain grooves; 150-second patterned photoresist layer; 160-second opening; 161-second source and drain grooves; 170-first epitaxial layer; 180-second epitaxial layer; 190-silicon cap layer. DETAILED DESCRIPTION

[0023] The field effect transistor and the manufacturing method thereof proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0024] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a field effect transistor according to an embodiment of the present invention. Figure 1 As shown, the manufacturing method of the field effect transistor provided in this embodiment includes: step S1: providing a substrate, the substrate including an input-output device region and a core device region, a first gate structure is formed on the input-output device region, and a second gate structure is formed on the core device region; step S2: etching the input-output device region on both sides of the first gate structure to form a first source-drain groove; step S3: etching the core device region on both sides of the second gate structure to form a second source-drain groove, wherein the critical dimension of the first source-drain groove is greater than the critical dimension of the second source-drain groove. Critical dimensions; Step S4: forming a first epitaxial layer, a second epitaxial layer and a silicon cap layer in sequence, wherein the first epitaxial layer covers the inner surfaces of the first source-drain groove and the second source-drain groove, the second epitaxial layer covers the first epitaxial layer and fills the first source-drain groove and the second source-drain groove, and the silicon cap layer covers the second epitaxial layer, wherein the first epitaxial layer, the second epitaxial layer and the silicon cap layer in the first source-drain groove constitute a first source-drain region, and the first epitaxial layer, the second epitaxial layer and the silicon cap layer in the second source-drain groove constitute a second source-drain region.

[0025] The following will be combined with the attached Figure 2~Figure 7 The method for manufacturing the field effect transistor provided in this embodiment is described in more detail.

[0026] Figure 2FIG. 1 is a schematic diagram of a structure after a first opening is formed in a method for manufacturing a field effect transistor according to an embodiment of the present invention. Figure 2 As shown, step S1 is performed to provide a substrate 100, wherein the substrate 100 includes an input-output device region 100a and a core device region 100b, wherein a first gate structure 110 is formed on the input-output device region 100a, and a second gate structure 120 is formed on the core device region 100b. At least two first gate structures 110 may be formed on the input-output device region 100a, and at least two second gate structures 120 may be formed on the core device region 100b, and the spacing between adjacent first gate structures 110 is greater than the spacing between adjacent second gate structures 120.

[0027] In this embodiment, the substrate 100 is used to provide an operating platform for subsequent processes, and the substrate 100 may be a silicon substrate. The core device area 100b is used to form core devices, and the input / output device area 100a is used to form input / output devices. A shallow trench isolation structure (not shown) is formed between the core device area 100b and the input / output device area 100a.

[0028] like Figure 2 As shown, the first gate structure 110 includes a first gate 111, a first silicon oxide sidewall 112 and a first silicon nitride sidewall 113. The first gate 111 is formed on the input-output device region 100a. The channel of the input-output device region 100a is located in the region below the first gate 111. A gate dielectric layer (not shown) is also formed between the first gate 111 and the input-output device region 100a. The material of the first gate 111 may include polysilicon or metal.

[0029] The first silicon oxide spacer 112 covers the sidewall and top surface of the first gate 111 , and the first silicon nitride spacer 113 covers the first silicon oxide spacer 112 .

[0030] In this embodiment, the second gate structure 120 includes a second gate 121, a second silicon oxide sidewall 122, and a second silicon nitride sidewall 123. The second gate 121 is formed on the core device area 100b, and the channel of the core device area 100b is located below the second gate 121. A gate dielectric layer (not shown) is also formed between the second gate 121 and the core device area 100b. The material of the second gate 121 may include polysilicon or metal.

[0031] The second silicon oxide spacer 122 is formed on the sidewall and top surface of the second gate 121 , and the second silicon nitride spacer 123 covers the second silicon oxide spacer 122 .

[0032] like Figure 3 As shown, step S2 is performed to etch the input-output device region 100 a on both sides of the first gate structure 110 to form a first source-drain trench 141 .

[0033] Specifically, the method for forming the first source-drain trench 141 includes: first, Figure 2 As shown, a first patterned photoresist layer 130 is formed on the substrate 100, and the first patterned photoresist layer 130 exposes the input-output device area 100a on both sides of the first gate structure 110. The first patterned photoresist layer 130 can cover the top surface of the first gate structure 110, the top surface of the second gate structure 120 and the core device area 100b; further, the first patterned photoresist layer 130 also covers part of the input-output device area 100a.

[0034] The first patterned photoresist layer 130 is used as a mask to perform lightly doped drain ion implantation on the input-output device region 100a on both sides of the first gate structure 110, so as to suppress the diffusion of doped ions subsequently formed in the first source and drain regions to the channel of the input-output device region 100a at the bottom of the first gate 111, thereby suppressing the short channel effect. When lightly doped drain ion implantation is performed on the input-output device region 100a, the doped ions may be P-type ions, such as boron ions.

[0035] like Figure 2 As shown, the first patterned photoresist layer 130 is used as a mask, and the exposed input-output device area 100a is etched by a dry etching process to form a first opening 140. The shape of the first opening 140 is U-shaped (the bottom angle of the first opening 140 is a right angle or an obtuse angle). The etching gas of the dry etching process includes chlorine, hydrogen bromide, or a mixed gas of chlorine and hydrogen bromide.

[0036] Then, if Figure 3 As shown, the first patterned photoresist layer 130 is used as a mask, and the input-output device region 100a at the bottom of the first opening 140 is etched by a wet etching process to form the first source-drain trench 141. The depth D of the first source-drain trench 141 is 1 It can be 60nm~90nm.

[0037] In this embodiment, the first source-drain trench 141 is Σ-shaped to enhance channel stress. The sidewall of the first source-drain trench 141 has a tip, and the tip of the first source-drain trench 141 faces the first gate structure 110. The etching solution used in the wet etching process may be a tetramethylammonium hydroxide (TMAH) solution.

[0038] It should be noted that the crystal orientation of the substrate 100 of the input-output device region 100a on both sides of the first gate structure 110 is <100> Therefore, during the wet etching process, the substrate 100 <100> The etching rate of the crystal direction is less than <110> The etching rate of the crystal direction is such that the wet etching process has anisotropy on the input-output device area 100a. Therefore, when the input-output device area 100a at the bottom of the first opening 140 is etched by the wet etching process, a first source-drain groove 141 with a pointed end on the sidewall surface is formed, so that the shape of the first source-drain groove 141 is Σ-shaped.

[0039] Preferably, the tip of the first source-drain groove 141 is located below the first gate 111 (or below the channel of the input-output device region 100a). This can more effectively enhance the hole drift rate, which can be beneficial to enhancing the performance of the device.

[0040] In this embodiment, the critical dimension of the first source-drain trench 141 can be controlled by controlling the etching time of the wet etching process. The critical dimension of the first source-drain trench 141 includes the tip depth Y of the first source-drain trench 141. 1 , the tip proximity of the first source-drain trench 141 (proximity) X 1 and the width L of the opening of the first source-drain trench 141 1 The tip depth Y of the first source-drain trench 141 is 1 It refers to the distance from the tip of the first source-drain trench 141 to the surface of the input-output device region 100a. The tip depth Y of the first source-drain trench 141 is 1 The tip proximity of the first source-drain groove 141 refers to the lateral distance from the tip of the first source-drain groove 141 to the channel of the input-output device region 100a (or the lateral distance from the tip of the first source-drain groove 141 to the sidewall of the first gate 111). 1 The width of the first source / drain trench 141 at the opening is used to define the lateral dimension (S / D lateral dimension) of the first source / drain region to be formed subsequently.

[0041] Afterwards, if Figure 4 As shown, the first patterned photoresist layer 130 is removed. The first patterned photoresist layer 130 may be removed by a wet cleaning process or a stripping method.

[0042] Figure 6 FIG. 1 is a schematic diagram of a structure after forming a second source-drain trench in a method for manufacturing a field effect transistor according to an embodiment of the present invention. Figure 6 As shown, step S3 is performed to etch the core device area 100b on both sides of the second gate structure 120 to form a second source-drain trench 161, and the critical dimension of the first source-drain trench 141 is larger than the critical dimension of the second source-drain trench 161, or in other words, the critical dimension of the second source-drain trench 161 is smaller than the critical dimension of the first source-drain trench 141.

[0043] Specifically, the method for forming the second source-drain trench 161 includes: first, Figure 5 As shown, a second patterned photoresist layer 150 is formed on the substrate 100, and the second patterned photoresist layer 150 fills the first source-drain groove 141 and exposes the core device area 100b on both sides of the second gate structure 120; further, the second patterned photoresist layer 150 also covers a portion of the core device area 100b close to the input-output device area 100a.

[0044] Then, if Figure 5 As shown, the exposed core device region 100b is etched by dry etching to form a second opening 160. The second opening 160 is U-shaped (the bottom angle of the second opening 160 is a right angle or an obtuse angle). The etching gas of the dry etching process includes chlorine, hydrogen bromide, or a mixed gas of chlorine and hydrogen bromide.

[0045] Then, if Figure 6 As shown, the second patterned photoresist layer 150 is used as a mask and a wet etching process is adopted to etch the core device region 100 b at the bottom of the second opening 160 to form the second source-drain trench 161 .

[0046] In this embodiment, the second source-drain trench 161 is Σ-shaped to enhance channel stress. The sidewall of the second source-drain trench 161 has a tip, and the tip of the second source-drain trench 161 faces the second gate structure 120. The etching solution used in the wet etching process may be a tetramethylammonium hydroxide (TMAH) solution.

[0047] It should be noted that the crystal orientation of the substrate 100 in the core device region 100b on both sides of the second gate structure 120 is <100> Therefore, during the wet etching process, the substrate 100 <100> The etching rate of the crystal direction is less than <110> The etching rate of the crystal direction, therefore, the wet etching process has anisotropy on the core device area 100b. Therefore, when the core device area 100b at the bottom of the second opening 160 is etched by the wet etching process, a second source-drain groove 161 with a pointed sidewall surface is formed, so that the shape of the second source-drain groove 161 is Σ-shaped.

[0048] In this embodiment, the critical dimension of the second source-drain trench 161 can be controlled by controlling the etching time of the wet etching process. The critical dimension of the second source-drain trench 161 includes the tip depth Y of the second source-drain trench 161. 2 , the tip proximity X of the second source-drain trench 161 2 and the width L of the opening of the second source-drain trench 161 2 The tip depth Y of the second source-drain trench 161 is 2 refers to the distance from the tip of the second source-drain trench 161 to the surface of the core device region 100b; the proximity X of the tip of the second source-drain trench 161 2 It refers to the lateral distance from the tip of the second source / drain trench 161 to the channel of the core device area 100 b (or the lateral distance from the tip of the second source / drain trench 161 to the sidewall of the second gate 121 ); the width at the opening of the second source / drain trench 161 is used to define the lateral dimension (S / D lateral dimension) of the second source / drain region to be formed subsequently.

[0049] In this embodiment, the tip depth Y of the second source-drain trench 161 is 2 can be smaller than the tip depth Y of the first source and drain trench 1 , the tip proximity X of the second source-drain trench 161 2 is smaller than the tip proximity X of the first source-drain trench 141 1 , the width L of the second source-drain trench 161 at the opening 2 smaller than the width L of the opening of the first source-drain trench 141 1 In addition, the depth D of the second source-drain trench 161 is 2 It may be smaller than the depth D of the first source / drain trench 141 1 .

[0050] In this embodiment, the critical dimension of the second source-drain groove 161 is different from the critical dimension of the first source-drain groove 141, and the second source-drain groove 161 and the first source-drain groove 141 are formed in different steps. Therefore, the critical dimensions of the first source-drain groove 141 and the second source-drain groove 161 can be controlled respectively, so that the critical dimension of the first source-drain groove 141 is larger than the critical dimension of the second source-drain groove 161, so that the maximum electric field can be kept away from the channel of the input-output device area 100a, thereby reducing the electric field strength near the channel, thereby improving the reliability of the formed device.

[0051] In the present embodiment, since the critical dimension of the first source-drain trench 141 of the input-output device area 100a is greater than the critical dimension of the second source-drain trench 161 of the core device area 100b, the critical dimension of the first source-drain region of the input-output device area 100a formed subsequently can be greater than the critical dimension of the second source-drain region of the core device area, thereby meeting the different operating voltage requirements of the core device area 100b and the input-output device area 100a (the operating voltage of the input-output device area 100a is greater than the operating voltage of the core device area 100b), which is beneficial to improving the overall performance and reliability of the device.

[0052] Specifically, the critical dimension of the first source-drain trench 141 is greater than the critical dimension of the second source-drain trench 161, including: the tip depth Y of the first source-drain trench 141 1 Greater than the tip depth Y of the second source / drain trench 161 2 In this way, the electric field strength of the input-output device area 100a can be dispersed and reduced, thereby improving the withstand voltage and reliability of the device, and is conducive to optimizing the electric field distribution of the input-output device area 100a, reducing the electric field concentration, and thus improving the breakdown voltage (V bd ); In addition, the hot carrier injection effect (HCI) of the input-output device region 100a can be improved. The tip proximity X of the first source-drain trench 141 1 is greater than the tip proximity X of the second source-drain trench 161 2 In this way, the stress of the first epitaxial layer and the second epitaxial layer formed subsequently can be more evenly distributed in the channel region of the input-output device region 100a, and a greater strain effect can be generated in the input-output device region 100a, thereby improving the mobility of holes. The width L of the first source-drain trench 141 at the opening is 1 Greater than the width L of the opening of the second source-drain trench 161 2 , which can make the top surface area of ​​the first source and drain region formed subsequently larger, thereby increasing the contact surface of the first source and drain region, reducing the source-drain resistance, and improving the current driving capability of the device, and is beneficial to improving the electric field distribution of the input-output device area 100a, reducing electric field concentration and leakage current, and improving the voltage resistance and stability of the device, thereby improving the reliability of the device.

[0053] Afterwards, the second patterned photoresist layer 150 is removed. The second patterned photoresist layer 150 may be removed by a wet cleaning process or a stripping method.

[0054] Figure 7 FIG. 1 is a schematic diagram of the structure after a silicon cap layer is formed in the method for manufacturing a field effect transistor according to an embodiment of the present invention. Figure 7 As shown, step S4 is performed to sequentially form a first epitaxial layer 170, a second epitaxial layer 180 and a silicon cap layer 190, wherein the first epitaxial layer 170 covers the inner surfaces of the first source-drain groove 141 and the second source-drain groove 161, the second epitaxial layer 180 covers the first epitaxial layer 170 and fills the first source-drain groove 141 and the second source-drain groove 161, and the silicon cap layer 190 covers the second epitaxial layer 180, wherein the first epitaxial layer 170, the second epitaxial layer 180 and the silicon cap layer 190 in the first source-drain groove 141 constitute a first source-drain region, and the first epitaxial layer 170, the second epitaxial layer 180 and the silicon cap layer 190 in the second source-drain groove 161 constitute a second source-drain region.

[0055] Specifically, the material of the first epitaxial layer 170 and the material of the second epitaxial layer 180 can be germanium silicon. The first epitaxial layer 170 and the second epitaxial layer 180 can generate compressive stress on the channel, which helps to increase the mobility of hole carriers in the channel, thereby improving the performance of the device.

[0056] The germanium content in the first epitaxial layer 170 gradually increases from the bottom surface to the top surface of the first epitaxial layer 170 to relieve the stress caused by lattice mismatch, which is conducive to achieving good lattice matching between the first epitaxial layer 170 and the substrate 100, reducing defects and dislocations, and improving the reliability and stability of the device. Preferably, the germanium content in the first epitaxial layer 170 is 1% to 5%.

[0057] It should be noted that if the germanium content in the first epitaxial layer 170 is too high, it is easy to affect the lattice matching between the first epitaxial layer 170 and the substrate 100 or easily cause dislocation defects; if the germanium content in the first epitaxial layer 170 is too low, it is easy to affect the growth process of the bulk first epitaxial layer 170. Accordingly, the germanium content in the first epitaxial layer 170 is 1% to 5% to reduce or avoid the lattice matching or dislocation defects between the first epitaxial layer 170 and the substrate 100.

[0058] In this embodiment, the germanium content in the first epitaxial layer 170 is lower than the germanium content in the subsequently formed second epitaxial layer 180, thereby enabling the first epitaxial layer 170 to serve as a transition layer between the subsequently formed second epitaxial layer 180 and the substrate 100, and enabling the relatively sharp inner surface contours of the first source-drain groove 141 and the second source-drain groove 161 to become smooth, thereby improving the contact interface quality between the subsequently formed second epitaxial layer 180 and the first epitaxial layer 170.

[0059] After the first epitaxial layer 170 is deposited, the first source-drain trench 141 and the second source-drain trench 161 having the first epitaxial layer 170 both become smooth U-shaped openings, that is, the surface shape of the first epitaxial layer 170 is U-shaped.

[0060] Afterwards, doping ions are implanted into the first epitaxial layer 170. The doping ion implantation can be completed by a one-step or multi-step ion implantation process. The doping ion implantation process can be vertical ion implantation, tilted ion implantation, or a combination of vertical ion implantation and tilted ion implantation. The doping ions in the first epitaxial layer 170 can be boron ions. The concentration of boron ions in the first epitaxial layer 170 is less than the concentration of boron ions doped in the second epitaxial layer 180 formed subsequently. In this way, the rate of change of the electric field in the channel can be slowed down, which is conducive to suppressing the short channel effect.

[0061] Then, if Figure 7 As shown, a second epitaxial layer 180 is formed on the surface of the first epitaxial layer 170 by a selective epitaxial growth process. The material of the second epitaxial layer 180 is the same as that of the first epitaxial layer 170, that is, the material of the second epitaxial layer 180 is also germanium silicon, but the germanium content in the second epitaxial layer 180 is greater than the germanium content in the first epitaxial layer 170, thereby improving the hole carrier mobility in the channel of the core device area 100b and the input-output device area 100a. Further, the second epitaxial layer 180 can serve as a transition between the first epitaxial layer 170 and the silicon cap layer 190 formed subsequently, so that the contact between the first epitaxial layer 170 and the silicon cap layer 190 is more reliable, and can provide greater compressive stress to the channel of the core device area 100b and the channel of the input-output device area 100a, thereby improving the hole carrier mobility in the channel.

[0062] Preferably, the germanium content in the second epitaxial layer 180 gradually increases from the bottom surface to the top surface of the second epitaxial layer 180, and the germanium content in the second epitaxial layer 180 is 20% to 40%. In this way, a buffering effect can be played, and the lattice constant of the second epitaxial layer 180 can be gradually changed, thereby alleviating the stress caused by lattice mismatch and reducing the dislocation density. Due to the gradual change of the lattice constant, the stress in the second epitaxial layer 180 can be dispersed and released, thereby reducing the dislocation caused by stress concentration, and further improving the mobility of hole carriers in the channel.

[0063] Next, doping ions are implanted into the second epitaxial layer 180 to dope boron ions in the second epitaxial layer 180 . The concentration of the boron ions in the second epitaxial layer 180 is greater than the concentration of the boron ions in the first epitaxial layer 170 .

[0064] Afterwards, if Figure 7 As shown, a silicon cap layer 190 is grown on the surface of the second epitaxial layer 180 by a selective epitaxial growth process, and the top surface of the silicon cap layer 190 is higher than the top surface of the substrate 100. The silicon cap layer 190 may be made of silicon to reduce contact resistance.

[0065] Next, the silicon cap layer 190 is doped with ions to dope boron ions in the silicon cap layer 190 . The concentration of the boron ions doped in the silicon cap layer 190 is greater than the concentration of the boron ions in the first epitaxial layer 170 and the concentration in the second epitaxial layer 180 to reduce contact resistance.

[0066] Continue to refer Figure 7As shown, this embodiment further provides a field effect transistor, comprising: a substrate 100, the substrate 100 comprising an input-output device region 100a and a core device region 100b, a first gate structure 110 formed on the input-output device region 100a, first source-drain trenches 141 formed in the input-output device region 100a on both sides of the first gate structure 110, a second gate structure 120 formed on the core device region 100b, second source-drain trenches 161 formed in the core device region 100b on both sides of the second gate structure 120, the critical dimension of the first source-drain trench 141 being greater than the critical dimension of the second source-drain trench 161; a first epitaxial layer 170, The first epitaxial layer 170 covers the inner surfaces of the first source-drain groove 141 and the second source-drain groove 161; the second epitaxial layer 180, the second epitaxial layer 180 covers the first epitaxial layer 170 and fills the first source-drain groove 141 and the second source-drain groove 161; the silicon cap layer 190, the silicon cap layer 190 covers the second epitaxial layer 180; wherein the first epitaxial layer 170, the second epitaxial layer 180 and the silicon cap layer 190 in the first source-drain groove 141 constitute a first source-drain region, and the first epitaxial layer 170, the second epitaxial layer 180 and the silicon cap layer 190 in the second source-drain groove 161 constitute a second source-drain region.

[0067] In addition, the field effect transistor of this embodiment may be a P-type field effect transistor.

[0068] In summary, in the field effect transistor and the manufacturing method thereof provided by the present invention, the input-output device region on both sides of the first gate structure is first etched to form a first source-drain groove, and then the core device region on both sides of the second gate structure is etched to form a second source-drain groove, thereby the critical dimensions of the first source-drain groove and the second source-drain groove can be controlled respectively, that is, the contour of the first source-drain groove and the contour of the second source-drain groove can be controlled, so that the critical dimension of the first source-drain groove is larger than the critical dimension of the second source-drain groove, so that the morphology of the first source-drain region and the second source-drain region formed subsequently can be controlled, and the reliability of the formed device can be improved. In addition, since the critical dimension of the first source-drain groove is larger than the critical dimension of the second source-drain groove, the requirements of different operating voltages of the input-output device region and the core device region can be met (the operating voltage of the input-output device region is larger than the operating voltage of the core device region), which is conducive to improving the overall performance and reliability of the device.

[0069] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the claims. In addition, it should be recognized that although the present invention has been disclosed as above with preferred embodiments, the above embodiments are not used to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a field effect transistor, characterized in that: include: Providing a substrate, the substrate comprising an input-output device region and a core device region, a first gate structure is formed on the input-output device region, and a second gate structure is formed on the core device region; forming a first patterned photoresist layer on the substrate, wherein the first patterned photoresist layer exposes the input-output device regions on both sides of the first gate structure; Using the first patterned photoresist layer as a mask, etching the input-output device regions on both sides of the first gate structure to form first source-drain trenches, and removing the first patterned photoresist layer; forming a second patterned photoresist layer on the substrate, wherein the second patterned photoresist layer fills the first source-drain trench and exposes the core device region on both sides of the second gate structure; Using the second patterned photoresist layer as a mask, etching the core device area on both sides of the second gate structure to form a second source-drain groove, and removing the second patterned photoresist layer, wherein the shape of the second source-drain groove and the shape of the first source-drain groove are both Σ-shaped, the sidewalls of the first source-drain groove and the sidewalls of the second source-drain groove both have tips, the tip of the first source-drain groove faces the first gate structure, the tip of the second source-drain groove faces the second gate structure, and the critical dimension of the first source-drain groove is greater than the critical dimension of the second source-drain groove, the critical dimension of the first source-drain groove is greater than the critical dimension of the second source-drain groove, including that the tip proximity of the first source-drain groove is greater than the tip proximity of the second source-drain groove, the tip proximity of the first source-drain groove is the lateral distance from the tip of the first source-drain groove to the channel of the input-output device area, and the tip proximity of the second source-drain groove is the lateral distance from the tip of the second source-drain groove to the channel of the core device area; A first epitaxial layer, a second epitaxial layer and a silicon cap layer are formed in sequence, wherein the first epitaxial layer covers the inner surfaces of the first source-drain trench and the second source-drain trench, the second epitaxial layer covers the first epitaxial layer and fills the first source-drain trench and the second source-drain trench, and the silicon cap layer covers the second epitaxial layer, wherein the first epitaxial layer, the second epitaxial layer and the silicon cap layer in the first source-drain trench constitute a first source-drain region, and the first epitaxial layer, the second epitaxial layer and the silicon cap layer in the second source-drain trench constitute a second source-drain region.

2. The method for manufacturing a field effect transistor according to claim 1, wherein: The material of the first epitaxial layer and the material of the second epitaxial layer are both germanium silicon, and the germanium content in the second epitaxial layer is greater than the germanium content in the first epitaxial layer.

3. The method for manufacturing a field effect transistor according to claim 2, wherein: The germanium content in the first epitaxial layer gradually increases from the bottom surface to the top surface of the first epitaxial layer, and the germanium content in the first epitaxial layer is 1%-5%.

4. The method for manufacturing a field effect transistor according to claim 2, wherein: The germanium content in the second epitaxial layer gradually increases from the bottom surface to the top surface of the second epitaxial layer, and the germanium content in the second epitaxial layer is 20%-40%.

5. The method for manufacturing a field effect transistor according to claim 1, wherein: The first epitaxial layer, the second epitaxial layer and the silicon cap layer are all doped with boron ions, the concentration of boron ions in the silicon cap layer is greater than the concentration of boron ions in the second epitaxial layer, and the concentration of boron ions in the second epitaxial layer is greater than the concentration of boron ions in the first epitaxial layer.

6. The method for manufacturing a field effect transistor according to claim 1, wherein: The critical dimensions of the first source-drain groove include the tip depth of the first source-drain groove, the tip proximity of the first source-drain groove, and the width of the first source-drain groove opening; the critical dimensions of the second source-drain groove include the tip depth of the second source-drain groove, the tip proximity of the second source-drain groove, and the width of the second source-drain groove opening.

7. The method for manufacturing a field effect transistor according to claim 1, wherein: Using the first patterned photoresist layer as a mask, a dry etching process is used to etch the exposed input / output device region to form a first opening, wherein the first opening is in a U-shape; The first patterned photoresist layer is used as a mask and a wet etching process is adopted to etch the input-output device region at the bottom of the first opening to form the first source-drain trench.

8. The method for manufacturing a field effect transistor according to claim 7, wherein: Using the second patterned photoresist layer as a mask, a dry etching process is used to etch the exposed core device area to form a second opening, wherein the second opening is in a U-shape, wherein the width of the first opening is greater than the width of the second opening, and the depth of the first opening is greater than the depth of the second opening; The second patterned photoresist layer is used as a mask and a wet etching process is adopted to etch the core device region at the bottom of the second opening to form the second source-drain trench.

9. A field effect transistor, characterized in that: include: A substrate, the substrate comprising an input-output device region and a core device region, a first gate structure is formed on the input-output device region, a second gate structure is formed on the core device region, first source-drain grooves are formed in the input-output device region on both sides of the first gate structure, second source-drain grooves are formed in the core device region on both sides of the second gate structure, the second source-drain grooves and the first source-drain grooves are both Σ-shaped, the sidewalls of the first source-drain grooves and the sidewalls of the second source-drain grooves both have sharp tips, and the tip of the first source-drain groove faces the first gate structure, The tip of the second source-drain trench faces the second gate structure, and the critical dimension of the first source-drain trench is greater than the critical dimension of the second source-drain trench, and the critical dimension of the first source-drain trench is greater than the critical dimension of the second source-drain trench, including that the tip proximity of the first source-drain trench is greater than the tip proximity of the second source-drain trench, the tip proximity of the first source-drain trench is the lateral distance from the tip of the first source-drain trench to the channel of the input-output device region, and the tip proximity of the second source-drain trench is the lateral distance from the tip of the second source-drain trench to the channel of the core device region; a first epitaxial layer, wherein the first epitaxial layer covers inner surfaces of the first source-drain trench and the second source-drain trench; A second epitaxial layer, wherein the second epitaxial layer covers the first epitaxial layer and fills the first source-drain trench and the second source-drain trench; a silicon cap layer, wherein the silicon cap layer covers the second epitaxial layer; The first epitaxial layer, the second epitaxial layer and the silicon cap layer in the first source-drain trench constitute a first source-drain region, and the first epitaxial layer, the second epitaxial layer and the silicon cap layer in the second source-drain trench constitute a second source-drain region.

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