Intelligent design system and design method for analog integrated circuits

Abstract

The present invention belongs to the field of automated design of analog integrated circuits. In view of the problem that existing analog integrated circuit design methods based on artificial intelligence algorithms do not fully consider the automated implementation process of the design system and are difficult to meet specific user needs, the present invention provides an intelligent design system and design method for analog integrated circuits. The intelligent design system for analog integrated circuits includes (1) an input interface; (2) a simulator interface unit: including an input interface, a monitoring interface, and a reading interface; (3) a domain knowledge base: including a design preference analysis unit, a topology structure library, a design rule library, and an evaluation rule library; (4) a simulator; (5) an intelligent optimization algorithm unit; and (6) a result evaluation and optimization constraint generation unit. The present invention eliminates manual intervention in the design process, and the application of manual design rules can effectively improve the efficiency and effectiveness of intelligent optimization of analog integrated circuits.

Description

Technical Field

[0001] The present invention belongs to the field of automated design of analog integrated circuits, and in particular relates to an intelligent design system and a design method for analog integrated circuits. Background Art

[0002] The key to front-end design of analog integrated circuits lies in topology selection and circuit parameter design. Analog circuit design parameters have a highly nonlinear relationship with circuit performance parameters, and each performance parameter has complex constraints. This makes parameter adjustment (optimization) of analog integrated circuits complex, iterative, and time-consuming. Adding artificial intelligence methods to assist in the parameter adjustment phase, which takes the longest time, can significantly improve design efficiency and reduce labor costs.

[0003] For example, patent document CN115713057A discloses a method for automatically optimizing analog integrated circuit design parameters based on a deep neural network. This method uses a deep neural network to calculate continuously changing component design parameter values. Adding an optimization target variable as input improves its goal-oriented nature, memorizes circuit optimization experience, and eliminates the need to retrain the algorithm from scratch for new optimization targets. It also establishes a library of circuit optimization models, enabling direct access across different computers within seconds. However, this method relies on a proxy model, requiring training of the proxy model and requiring significant computational resources. Furthermore, the accuracy of the model can affect the final design results.

[0004] Patent document CN114429099A proposes a method based on gm / ID design methodology and ID / W-gm / ID lookup table to reduce the optimization dimension of the algorithm. This method is equivalent to optimizing the circuit in the circuit's feature space, thereby improving the algorithm's optimization effect and accelerating the convergence speed. Patent document CN112417803A discloses a method for automatically optimizing analog integrated circuit design parameters based on an artificial intelligence algorithm. In the netlist parsing module, a simulator interface program is written in a computer programming language to complete the simulation process, and performance evaluation is performed through CPU or GPU parallel computing simulation. The disadvantage is that in each round of iteration, whether the design requirements are met is determined only by whether a single performance indicator meets the requirements. There is no comprehensive evaluation of all design indicators, and the user's design preferences are not taken into account. The resulting design results are often not optimal.

[0005] Patent document CN116738917A uses a Gaussian probability model to model each parameter and continuously generates the next generation of populations through rejection sampling, thus overcoming the disadvantage of genetic algorithms that they are prone to convergence to local optimal solutions, and achieving efficient and accurate circuit parameter optimization. Patent document CN112417803A discloses a method for automatic optimization of analog integrated circuit design parameters based on artificial intelligence algorithms. In the netlist parsing module, a simulator interface program is written in a computer programming language to complete the simulation process, and performance evaluation is performed through CPU or GPU parallel computing simulation. The disadvantages of these two technical solutions are that they only rely on intelligent optimization methods to optimize the parameters of analog integrated circuits, without combining manual design experience, are prone to falling into local optimal solutions, and cannot weigh various factors in multi-objective optimization.

[0006] Patent document CN114841106A discloses an integrated circuit optimization method based on a rule-guided genetic algorithm. This method introduces design rules during the mutation phase. By tracing the paternal and maternal parentage of the current individual, these paternal and maternal parentages undergo a design-rule-guided genetic mutation, generating new paternal and maternal parentages. These new paternal and maternal parentages are then recrossed to produce new individuals, which are added to the next generation population. This method achieves faster convergence and higher optimization efficiency, but has drawbacks: the weights of circuit performance parameters are set by the user, increasing the user's knowledge requirements. Furthermore, the method lacks a standardized representation of manual design rules, reducing the degree of automation in the analog integrated circuit design optimization process.

[0007] The above analysis shows that relying solely on artificial intelligence algorithms for analog integrated circuit design can easily lead to local optimal solutions. Surrogate model-based approaches require training of these surrogate models, consume significant computing resources, and affect the accuracy of these models, ultimately impacting the final design results. Focusing solely on whether the intelligent optimization algorithm satisfies the requirements for a single performance metric while neglecting simulation process monitoring, reading various simulation results (values, waveforms, transistor status, etc.), and evaluating design results based on domain knowledge can fail to achieve optimal overall design results. Furthermore, the inability to standardize manual design rules reduces the overall system's automation level. Furthermore, the approach fails to consider user design preferences, making it difficult to meet specific user needs. Summary of the Invention

[0008] In response to the problem that existing analog integrated circuit design methods based on artificial intelligence algorithms do not fully consider the automated implementation process of the design system and are difficult to meet specific user needs, the present invention provides an intelligent design system and design method for analog integrated circuits. It systematically considers various aspects such as user input analysis, simulator monitoring, simulation result reading and judgment, and the construction and application of domain knowledge bases, eliminating manual intervention in the design process. The application of manual design rules can effectively improve the efficiency and effectiveness of intelligent optimization of analog integrated circuits.

[0009] The present invention is achieved through the following technical solutions:

[0010] In one aspect, the present invention provides an intelligent design system for analog integrated circuits, comprising the following components:

[0011] (1) Input interface: used to receive the user's circuit design information and transmit it to the domain knowledge base, wherein the circuit design information includes at least the designed circuit type, design goals, and design preferences;

[0012] (2) Simulator interface unit: including input interface, monitoring interface and reading interface;

[0013] The input interface is connected to the input interface, the simulator, and the domain knowledge base, respectively, and is used to convert the user's circuit design information and the topology recommended by the domain knowledge base based on the user preference analysis into simulator settings;

[0014] The monitoring interface is connected to the interface of the simulator and is used to monitor the simulator information in real time during the operation of the simulator. If a simulation anomaly is found, the simulation process is terminated.

[0015] The reading interface is connected to the simulator and the design result evaluation unit respectively, and is used to read the simulation results related to the design target and output the read simulation results to the design result evaluation unit;

[0016] (3) Domain knowledge base: including design preference analysis unit, topology structure library, design rule library and evaluation rule library;

[0017] The design preference analysis unit is associated with the input interface, the topology library, and the design rule library, and is used to recommend circuit topologies based on the design preferences selected by the user and extract the evaluation function to be used for this design from the evaluation rule library;

[0018] The topology library is also associated with the input interface and includes several topologies, with at least one topology stored under each circuit, and different topologies are associated with different design preferences;

[0019] The design rule library is associated with the topology library and the optimization constraint generation unit, and is used to store the correlation between various circuit performance indicators and design parameters for each topology. The correlation is divided into three situations: no correlation, positive correlation, and negative correlation. The correlation is used to determine the optimization direction of the design parameter in the next step;

[0020] Evaluation rule base: associated with the design preference analysis unit, used to store evaluation functions for evaluating circuit performance indicators. Different design preferences correspond to different evaluation functions. The larger the function value, the better the design effect. The evaluation function includes Vi Function, FoM function for evaluating the current design and f k Function; the evaluation is divided into two stages, the first stage uses V i Function to evaluate a single performance indicator; the second stage uses FoM function and f k Function evaluation overall design;

[0021] V i =G i (P i -P i,level ), where G i is the positive or negative value of the i-th performance index. The larger the index value, the better the performance index is. It is a positive index. G i =1, the smaller the index value, the better the performance index is, which is a reverse index. i =-1; P i is the true value of the i-th performance indicator obtained by the simulator; P i,level is the qualified value of the i-th performance indicator; V i When ≥0, it means that the i-th performance index meets the requirements; otherwise, it does not meet the requirements;

[0022] Among them, FoM k refers to the FoM function of the k-th topology, P ki and P kj is the index value of performance index i and j of the kth topology structure, T j and T j are the weights of the i-th and j-th performance indicators, respectively. The denominator is the weighted sum of m reverse indicators, the numerator is the weighted sum of n forward indicators, and the sum of m and n is the total number of performance indicators of the k-th topology. FoM k The larger it is, the better the design effect;

[0023] f k =FoM k -FoM k,pred , where FoM k,pred is the standard value of the FoM function of the k-th topological structure, when f k When ≥0, it means the current design meets the requirements, f k The larger the value, the better the design effect; otherwise, it means that the requirements are not met.

[0024] (4) simulator, used to execute the simulation process;

[0025] (5) Intelligent optimization algorithm unit: associated with the optimization constraint generation unit and the simulator unit, used to solve the design parameters according to the optimization constraints and optimization algorithm, and submit them to the simulator;

[0026] (6) Result evaluation and optimization constraint generation unit: including design result evaluation unit and optimization space constraint generation unit;

[0027] The design result evaluation unit is associated with the simulator interface unit and the domain knowledge base unit respectively, and is used to read the simulation results and call the evaluation rules in the domain knowledge base to determine whether the current design meets the requirements. When the evaluation result does not meet the requirements, the evaluation result is provided to the optimization constraint generation unit; when the evaluation result meets the requirements, the design is terminated and the design result is output;

[0028] The optimization space constraint generation unit is associated with the domain knowledge base unit and is used to call the design rule base, generate the optimization direction and step size of the design parameters according to the design deviation between the evaluation results and the design goals, and submit it to the intelligent optimization algorithm unit for the next step of design parameter solution.

[0029] Furthermore, the input interface is a graphical interface.

[0030] Furthermore, the input interface writes the user's circuit design information and topology structure into the simulator script file, thereby converting the circuit design information into simulator settings.

[0031] The general manifestation of simulation abnormality is either terminating the calculation or being unable to stop, that is, the simulation time is too long. Furthermore, the present invention sets a simulation threshold to address the problem of too long simulation time. The simulation threshold is set according to the complexity of the circuit design.

[0032] Furthermore, in the topology library, the correspondence between design preferences and topology structures can be manually adjusted.

[0033] Furthermore, the topological structures in the topological rule base are all set to an initial state, and manual adjustment of the initial state is allowed.

[0034] Furthermore, the design rule base is implemented in the form of a matrix. For a design with M design parameters and N performance indicators, the design rule base is an M×N matrix. Each value in the matrix represents its correlation, 0 represents no correlation, -1 represents negative correlation, and +1 represents positive correlation.

[0035] Furthermore, the method for determining the optimization direction of the design parameters is as follows: when a certain design parameter is correlated with only one performance indicator, and the performance indicator needs to be increased, if the correlation between the design parameter and the performance indicator is positive, the design parameter is increased; if the correlation is negative, the design parameter is decreased; when a certain design parameter has different correlations with more than two performance indicators, and the optimization goals of these performance indicators conflict with the adjustment direction of the design parameter, the design preference needs to be considered, and among the two or more performance indicators, if the performance indicator as the design preference is positively correlated with the design parameter, the design parameter is increased; if the correlation is negative, the design parameter is decreased; other situations are randomly handled by the intelligent optimization algorithm unit.

[0036] Furthermore, the standard value of the FoM function is determined by the following method: for each topology, simulation is performed in an offline state, and a design whose performance indicators meet the requirements is selected, and its FoM value is calculated according to the FoM function. The standard value of the FoM function is calculated according to the following formula:

[0037] Among them, FoM k,pred is the standard value of the FoM function of the kth topology, FoM k,uplevel is the FoM value of the design whose topology meets the constraints, x is the x-th design, and n is the number of designs that meet the constraints.

[0038] Furthermore, a commercial simulator is used, and the optimization algorithm is a heuristic optimization algorithm.

[0039] In another aspect, the present invention provides a method for designing an analog integrated circuit, using the analog integrated circuit design system of the present invention, comprising the following steps:

[0040] (1) System startup;

[0041] (2) The input interface receives the user's circuit design information;

[0042] (3) The design preference analysis unit analyzes the user's design preference and extracts the corresponding topology, design rules, and evaluation rules from the topology library, design rule library, and evaluation rule library respectively;

[0043] (4) The simulator interface unit generates simulator input information based on the topology structure, initial values, and design goals, and starts the simulation process;

[0044] (5) The monitoring interface monitors the simulator information during the simulation process. If any abnormality is found, the process proceeds to step (9);

[0045] (6) After the simulation is completed, the reading interface reads the simulation results related to the design target and outputs the read results to the design result evaluation unit;

[0046] (7) The design result evaluation unit determines whether the current design meets the design requirements based on the simulation results, design goals and evaluation rules; if the design requirements are met, the design is terminated and the design results are output; otherwise, the process goes to step (8);

[0047] (8) The optimization constraint generation unit calls the design rules according to the current design deviation, generates the optimization direction and step size of each design parameter, generates the optimization constraints, and submits them to the intelligent optimization algorithm unit;

[0048] (9) The intelligent optimization algorithm solves the next set of design parameters based on the optimization constraints and the optimization algorithm and submits them to the simulator interface unit;

[0049] (10) The simulator interface unit generates new simulator input information from the design parameters and starts the simulation process;

[0050] (11) Execute steps (5) to (7) until the current design meets the design requirements, end the optimization process, and output the optimization results.

[0051] The present invention has the following beneficial effects:

[0052] (1) Comprehensively build a domain knowledge base and apply it throughout the design optimization process. In particular, the design rule base uses a correlation matrix method to parameterize the manual design rules (the relationship between design parameters and performance indicators), effectively narrowing the search space of the optimization algorithm and improving optimization efficiency and effectiveness.

[0053] (2) With the assistance of the simulator interface and domain knowledge base, the optimization process does not require human participation, which improves design efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 FIG. 1 is a schematic diagram of the structure of an analog integrated circuit design system according to an embodiment.

[0055] Figure 2 The flowchart of the analog integrated circuit design method according to the embodiment is shown. DETAILED DESCRIPTION

[0056] The present invention is further described in detail below with reference to specific embodiments and accompanying drawings.

[0057] Example

[0058] like Figure 1 As shown, the analog integrated circuit design system includes:

[0059] (1) Input interface: This interface receives the user's circuit design information and transmits it to the domain knowledge base. The received circuit design information includes circuit type, design goals (performance parameters), etc. A graphical interface can be used.

[0060] (2) Simulator interface unit: including input interface, monitoring interface and reading interface;

[0061] The input interface is connected to the input interface, the simulator, and the domain knowledge base, respectively, and is used to write the user's circuit design information and the topology recommended by the domain knowledge base based on the user's preference analysis into the simulator script file, and convert the circuit design information into simulator settings;

[0062] The monitoring interface is connected to the simulator interface and is used to monitor simulator information in real time during the simulator operation. If a simulation anomaly is detected, a command is used to terminate the simulation process in a timely manner, thereby improving the operating efficiency of the design system. The simulation threshold is set according to the complexity of the circuit design.

[0063] The reading interface is connected to the simulator and the design result evaluation unit, respectively, and is used to read simulation results related to the design objectives and output the read simulation results to the design result evaluation unit. Depending on the circuit design objectives, different performance indicators require reading simulation result values or waveforms, MOS transistor status, etc. The computer digitizes the graph and then determines its changing trend. Specifically, the slope of the tangent line at each point in the graph is calculated, and the changing trend is determined by the slope value, thereby determining whether the waveform shape meets the requirements.

[0064] (3) Domain knowledge base: including design preference analysis unit, topology structure library, design rule library and evaluation rule library;

[0065] The design preference analysis unit is associated with the input interface, the topology library, and the design rule library, and is used to recommend circuit topologies based on the design preferences selected by the user, such as "power consumption priority" or "gain priority", and to extract the evaluation function to be used in this design from the evaluation rule library;

[0066] The topology library is also associated with the input interface and contains several topologies. At least one topology is stored under each circuit. Different topologies are associated with different design preferences so that selection can be made according to different preferences set by the user. The topology is stored in the simulator. The correspondence between design preferences and topologies is pre-configured, and different topologies correspond to different design preferences. Design preferences also correspond to evaluation functions, and different design preferences correspond to different evaluation functions. For example, the weights in the evaluation function may be different (quality factor or cost function). Engineers can adjust the correspondence. The topology in the topology rule library can select topologies that are commonly used in the industry and have good effects. A reasonable initial state is set for each topology. A reasonable state means that each design parameter has its range and mutual relationship (such as matching), and the initial state should meet these characteristics.

[0067] The design rule library is associated with the optimization constraint generation unit and is used to store the correlation between various circuit performance indicators and design parameters for each circuit topology. The correlation is divided into three situations: no correlation, positive correlation, and negative correlation. The correlation is used to determine the optimization direction of the design parameter in the next step. When a design parameter is correlated with only one performance indicator and the performance indicator needs to be increased, if the correlation between the design parameter and the performance indicator is positive, the design parameter is increased; if the correlation is negative, the design parameter is decreased; when a design parameter has different correlations with more than two performance indicators, and the optimization direction of these performance indicators conflicts with the adjustment direction of the design parameter, the design preference needs to be considered. Among the more than two performance indicators, if the performance indicator that serves as the design preference needs to be increased and is positively correlated with the design parameter, the design parameter is increased; if the correlation is negative, the design parameter is decreased; other situations are randomly handled by the intelligent optimization algorithm unit.

[0068] The design rule base can be implemented in the form of a matrix. For a design with M design parameters and N performance indicators, the design rule base is an M×N matrix. Each value in the matrix represents its correlation, with 0 representing no correlation, -1 representing negative correlation, and +1 representing positive correlation. For example, vector C11 = -1 and C12 = 1 indicates that design parameter 1 is negatively correlated with performance indicator 1 and positively correlated with performance indicator 2. When both performance indicators 1 and 2 need to be increased, if the user's design preference is performance indicator 1, the design parameter should be reduced; if the user's design preference is performance indicator 2, design parameter 1 should be increased.

[0069] Evaluation rule base: Associated with the design preference analysis unit, it is used to store evaluation functions for evaluating circuit performance indicators. Different design preferences correspond to different evaluation functions. The evaluation function includes V i Function, FoM function for evaluating the current design and f k Function; the evaluation is divided into two stages, the first stage uses V i Function to evaluate a single performance indicator; the second stage uses FoM function and f k Function evaluation overall design;

[0070] V i =G i (P i -P i,level ), where G i is the positive or negative value of the i-th performance index. The larger the index value, the better the performance index is. It is a positive index. G i =1, the smaller the index value, the better the performance index is, which is a reverse index. i =-1; P i is the true value of the i-th performance indicator obtained by the simulator; P i,levelis the qualified value of the i-th performance indicator; V i When ≥0, it means that the i-th performance index meets the requirements; otherwise, it does not meet the requirements;

[0071] Taking a two-stage op amp circuit as an example, its performance index constraints are shown in the following table:

[0072] Table 1 Design objectives of the two-stage operational amplifier circuit

[0073]

[0074] Use V i Functions evaluate individual performance indicators: For gain, the evaluation function is V1 = 1 * (gain1 - 50), where gain1 is the actual gain value obtained through the simulator. For power, the evaluation function is V2 = -1 * (power2 - 240), where power2 is the actual power value obtained through the simulator. The evaluation of other performance indicators is similar.

[0075] Among them, FoM k refers to the FoM function of the k-th topology, P ki and P kj is the index value of performance index i and j of the kth topology structure, T j and T j are the weights of the i-th and j-th performance indicators, respectively. The weight of each performance indicator is related to manual experience and design preferences. The performance indicator selected by the user as the design preference has the largest weight. The denominator is the weighted sum of m reverse indicators, the numerator is the weighted sum of n forward indicators, and the sum of m and n is the total number of performance indicators of the k-th topology. FoM k The larger it is, the better the design effect.

[0076] Taking the above two-stage op amp circuit as an example, if the user selects the design preference "area", the FOM function can be designed as follows:

[0077]

[0078] f k =FoM k -FoM k,pred , where FoM k,pred is the standard value of the FoM function of the k-th topological structure, when f k When ≥0, it means the current design meets the requirements, f k The larger the value, the better the design effect; otherwise, it means that the requirements are not met.

[0079] The standard value of the FoM function is determined by the following method: For each topology, multiple simulations (for example, 1000 times) are performed offline. Designs that meet the performance requirements are selected and their FoM values are calculated using the FoM function. The standard value of the FoM function is calculated using the following formula:

[0080] Among them, FoM k,pred is the standard value of the FoM function of the kth topology, FoM k,uplevel is the FoM value of the design whose topology meets the constraints, x is the x-th design, and n is the number of designs that meet the constraints.

[0081] For the above two-stage op amp circuit, if the FoM function value of a design is 15, FoM k，pred The function value is 10, then its comprehensive evaluation function value is: f k =15-10=5, which means the design meets the requirements and the solution can be stopped.

[0082] (4) Simulator, using SPICE;

[0083] (5) Intelligent optimization algorithm unit: associated with the optimization constraint generation unit and the simulator unit, used to solve the design parameters according to the optimization constraints and optimization algorithm, and submit them to the simulator;

[0084] (6) Result evaluation and optimization constraint generation unit: including design result evaluation unit and optimization space constraint generation unit;

[0085] The design result evaluation unit is associated with the simulator interface unit and the domain knowledge base unit respectively, and is used to read the simulation results and call the evaluation rules in the domain knowledge base to determine whether the current design meets the requirements. When the evaluation result does not meet the requirements, the evaluation result is provided to the optimization constraint generation unit; when the evaluation result meets the requirements, the design is terminated and the design result is output;

[0086] The optimization space constraint generation unit is associated with the domain knowledge base unit and is used to call the design rule base, generate the optimization direction and step size of the design parameters according to the design deviation between the evaluation results and the design goals, and submit it to the intelligent optimization algorithm unit for the next step of design parameter solution.

[0087] Design process:

[0088] (1) System startup;

[0089] (2) The input interface receives the user's circuit design information;

[0090] (3) The design preference analysis unit analyzes the user's design preference and extracts the corresponding topology, design rules, and evaluation rules from the topology library, design rule library, and evaluation rule library respectively;

[0091] (4) The simulator interface unit generates simulator input information based on the topology structure, initial values, and design goals, and starts the simulation process;

[0092] (5) The monitoring interface monitors the simulator information during the simulation process. If any abnormality is found, the process proceeds to step (9);

[0093] (6) After the simulation is completed, the reading interface reads the simulation results related to the design target and outputs the read results to the design result evaluation unit;

[0094] (7) The design result evaluation unit determines whether the current design meets the design requirements based on the simulation results, design goals and evaluation rules; if the design requirements are met, the design is terminated and the design results are output; otherwise, the process goes to step (8);

[0095] (8) The optimization constraint generation unit calls the design rules according to the current design deviation, generates the optimization direction and step size of each design parameter, generates the optimization constraints, and submits them to the intelligent optimization algorithm unit;

[0096] (9) The intelligent optimization algorithm solves the next set of design parameters based on the optimization constraints and the optimization algorithm and submits them to the simulator interface unit;

[0097] (10) The simulator interface unit generates new simulator input information from the design parameters and starts the simulation process;

[0098] (11) Execute steps (5) to (7) until the current design meets the design requirements, end the optimization process, and output the optimization results.

[0099] The embodiments described above are merely descriptions of preferred implementations of the present invention and are not intended to limit the scope of the present invention. Without departing from the spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should fall within the scope of protection determined by the claims of the present invention.

Claims

1. An intelligent design system for analog integrated circuits, characterized in that: Includes the following sections: (1) Input interface: used to receive the user's circuit design information and transmit it to the domain knowledge base, wherein the circuit design information includes at least the designed circuit type, design goals, and design preferences; (2) Simulator interface unit: including input interface, monitoring interface and reading interface; The input interface is connected to the input interface, the simulator, and the domain knowledge base, respectively, and is used to convert the user's circuit design information and the topology recommended by the domain knowledge base based on the user preference analysis into simulator settings; The monitoring interface is connected to the simulator and is used to monitor the simulator information in real time during the simulator operation. If a simulation anomaly is found, the simulation process is terminated. The reading interface is connected to the simulator and the design result evaluation unit respectively, and is used to read the simulation results related to the design target and output the read simulation results to the design result evaluation unit; (3) Domain knowledge base: including design preference analysis unit, topology structure library, design rule library and evaluation rule library; The design preference analysis unit is associated with the input interface, the topology library, and the design rule library, and is used to recommend circuit topologies based on the design preferences selected by the user and extract the evaluation function to be used for this design from the evaluation rule library; The topology library is also associated with the input interface and includes several topologies, with at least one topology stored under each circuit, and different topologies are associated with different design preferences; The design rule library is associated with the topology library and the optimization constraint generation unit, and is used to store the correlation between various circuit performance indicators and design parameters for each circuit topology. The correlation is divided into three situations: no correlation, positive correlation, and negative correlation. The correlation is used to determine the optimization direction of the design parameter in the next step; Evaluation rule base: associated with the design preference analysis unit, used to store evaluation functions for evaluating circuit performance indicators. Different design preferences correspond to different evaluation functions. The larger the function value, the better the design effect. The evaluation includes V i Function, FoM function for evaluating the current design and f k Function; the evaluation is divided into two stages, the first stage uses V i Function to evaluate a single performance indicator; the second stage uses FoM function and f k Function evaluation overall design; V i =G i (P i -P i,level ), where G i is the positive or negative value of the i-th performance index. The larger the index value, the better the performance index is. It is a positive index. G i =1, the smaller the index value, the better the performance index is, which is a reverse index. i =-1; P i is the true value of the i-th performance indicator obtained by the simulator; P i,level is the qualified value of the i-th performance indicator; V i When ≥0, it means that the i-th performance index meets the requirements; otherwise, it does not meet the requirements; Among them, FoM k refers to the FoM function of the k-th topology, P ki and P kj is the index value of performance index i and j of the kth topology structure, T j and T j are the weights of the i-th and j-th performance indicators, respectively. The denominator is the weighted sum of m reverse indicators, the numerator is the weighted sum of n forward indicators, and the sum of m and n is the total number of performance indicators of the k-th topology. f k =FoM k -FoM k,pred , where FoM k,pred is the standard value of the FoM function of the k-th topological structure, when f k When ≥0, it means that the current design meets the requirements; otherwise, it means that the requirements are not met; (4) Simulator; (5) Intelligent optimization algorithm unit: associated with the optimization constraint generation unit and the simulator unit, used to solve the design parameters according to the optimization constraints and optimization algorithm, and submit them to the simulator; (6) Result evaluation and optimization constraint generation unit: including design result evaluation unit and optimization space constraint generation unit; The design result evaluation unit is associated with the simulator interface unit and the domain knowledge base unit respectively, and is used to read the simulation results and call the evaluation rules in the domain knowledge base to determine whether the current design meets the requirements. When the evaluation result does not meet the requirements, the evaluation result is provided to the optimization constraint generation unit; when the evaluation result meets the requirements, the design is terminated and the design result is output; The optimization space constraint generation unit is associated with the domain knowledge base unit and is used to call the design rule base, generate the optimization direction and step size of the design parameters according to the design deviation between the evaluation results and the design goals, and submit it to the intelligent optimization algorithm unit for the next step of design parameter solution.

2. The intelligent design system for analog integrated circuits according to claim 1, wherein: The input interface is a graphical interface.

3. The intelligent design system for analog integrated circuits according to claim 1, wherein: The input interface writes the user's circuit design information and topology structure into the simulator script file, thereby converting the circuit design information into simulator settings.

4. The intelligent design system for analog integrated circuits according to claim 1, wherein: The design rule base is implemented in the form of a matrix. For a design with M design parameters and N performance indicators, the design rule base is an M×N matrix. Each value in the matrix represents its correlation, 0 represents no correlation, -1 represents negative correlation, and +1 represents positive correlation.

5. The intelligent design system for analog integrated circuits according to claim 1, wherein: The method for determining the optimization direction of the design parameters is as follows: when a certain design parameter is correlated with only one performance indicator and the performance indicator needs to be increased, if the correlation between the design parameter and the performance indicator is positive, the design parameter is increased; if the correlation is negative, the design parameter is decreased; when a certain design parameter has different correlations with more than two performance indicators, and the optimization direction of these performance indicators conflicts with the adjustment direction of the design parameter, the design preference needs to be considered, and among the more than two performance indicators, the performance indicator that serves as the design preference needs to be increased and is positively correlated with the design parameter, the design parameter is increased; if the correlation is negative, the design parameter is decreased; other situations are handled randomly by the intelligent optimization algorithm unit.

6. The intelligent design system for analog integrated circuits according to claim 1, wherein: The standard value of the FoM function is determined by the following method: for each topology, simulation is performed in an offline state, and the design whose performance index meets the requirements is selected, and its FoM value is calculated according to the FoM function. The standard value of the FoM function is calculated according to the following formula; Among them, FoM k,pred is the standard value of the FoM function of the kth topology, FoM k,uplevel is the FoM value of the design whose topology meets the constraints, x is the x-th design, and n is the number of designs that meet the constraints.

7. The intelligent design system for analog integrated circuits according to claim 1, wherein: A commercial simulator is used.

8. The intelligent design system for analog integrated circuits according to claim 1, wherein: The optimization algorithm is a heuristic optimization algorithm.

9. A method for designing an analog integrated circuit, characterized in that: The intelligent design system for analog integrated circuits according to any one of claims 1 to 8 comprises the following steps: (1) System startup; (2) The input interface receives the user's circuit design information; (3) The design preference analysis unit analyzes the user's design preference and extracts the corresponding topology, design rules, and evaluation rules from the topology library, design rule library, and evaluation rule library respectively; (4) The simulator interface unit generates simulator input information based on the topology structure, initial values, and design goals, and starts the simulation process; (5) The monitoring interface monitors the simulator information during the simulation process. If any abnormality is found, the process proceeds to step (9); (6) After the simulation is completed, the reading interface reads the simulation results related to the design target and outputs the read results to the design result evaluation unit; (7) The design result evaluation unit determines whether the current design meets the design requirements based on the simulation results, design goals and evaluation rules; if the design requirements are met, the design is terminated and the design results are output; otherwise, the process goes to step (8); (8) The optimization constraint generation unit calls the design rules according to the current design deviation, generates the optimization direction and step size of each design parameter, generates the optimization constraints, and submits them to the intelligent optimization algorithm unit; (9) The intelligent optimization algorithm solves the next set of design parameters based on the optimization constraints and the optimization algorithm and submits them to the simulator interface unit; (10) The simulator interface unit generates new simulator input information from the design parameters and starts the simulation process; (11) Execute steps (5) to (7) until the current design meets the design requirements, end the optimization process, and output the optimization results.

Images