Chip Design Method and System, and Computer Program Product

Abstract

Embodiments of the present disclosure provide a chip design method, a system, and a computer program product. The chip design method includes: obtaining design information for a memory, where the design information includes: bit depth and bit width, area, power consumption, and read / write frequency; selecting a plurality of alternative databases from a standard cell database; selecting at least one target database from the plurality of alternative databases according to the bit depth and bit width of the memory; performing a layout generation operation for the memory according to the bit depth and bit width of the memory and the bit depth and bit width of at least one target database to generate at least one simulation layout; obtaining simulation information of the at least one simulation layout, comparing the simulation information of the simulation layout with the design information of the memory, and when it is determined that the simulation information of the simulation layout is the same as the design information of the memory, using the simulation layout as the target layout. By adopting the above technical solution, it is possible to comprehensively consider the balance among performance, power consumption, and area, thereby improving the performance of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and particularly to a chip design method, a system, and a computer program product. Background Art

[0002] In the design of integrated circuits, the selection of the layout plays an important role in the performance, power consumption, and area of memory chips. For example, for the same memory chip, when designed with different layouts, the performance, power consumption, and area exhibited by the memory chip are different, and it is even difficult to achieve a balance among the performance, power consumption, and area of the memory chip, resulting in poor performance of the memory chip. Therefore, how to provide a technical solution to improve the performance of the chip has become an urgent technical problem to be solved. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a chip design method, a system, and a computer program product, which can comprehensively consider the balance among the read / write frequency, power consumption, and area, and thus improve the performance of the chip.

[0004] Embodiments of the present disclosure provide a chip design method, including:

[0005] Obtaining design information for a memory, where the design information includes: bit depth and bit width, area, power consumption, and read / write frequency;

[0006] Selecting a plurality of alternative databases from a standard cell database;

[0007] Selecting at least one target database from the plurality of alternative databases according to the bit depth and bit width of the memory; wherein, the bit depth and bit width of at least one target database are adapted to the bit depth and bit width of the memory;

[0008] Performing a layout generation operation for the memory according to the bit depth and bit width of the memory and the bit depth and bit width of at least one target database, to generate at least one simulation layout;

[0009] Obtaining simulation information of at least one simulation layout, comparing the simulation information of the simulation layout with the design information of the memory, and when it is determined that the simulation information of the simulation layout is the same as the design information of the memory, using the simulation layout as the target layout.

[0010] Optionally, the selecting a plurality of alternative databases from a standard cell database includes:

[0011] Based on the type of the memory to be designed, selecting a plurality of databases at least including the type of the memory;

[0012] Plot the performance curves of each database, where the parameters in the performance curves include at least: area, power consumption, and read / write frequency;

[0013] While keeping the read / write frequency unchanged, by comparing the area and power consumption in the performance curves of each database, use the database that meets the design requirements as the alternative database.

[0014] Optionally, the performing a layout generation operation on the memory according to the bit depth and bit width of the memory, and the bit depth and bit width of at least one of the target databases, to generate at least one simulation layout, includes:

[0015] When it is determined that the bit depth of the target database is the same as the bit depth of the memory, and the bit width of the target database is the same as the bit width of the memory, perform a layout generation operation on the target database through a pre-constructed script to generate the simulation layout corresponding to the memory;

[0016] When it is determined that the bit depth of the target database is less than the bit depth of the memory, and / or the bit width of the target database is less than the bit width of the memory, after performing at least one splitting operation on the bit depth and / or bit width of the memory, generate at least one simulation layout corresponding to the memory through the pre-constructed script;

[0017] When it is determined that the bit depth of the target database is greater than the bit depth of the memory, and / or the bit width of the target database is greater than the bit width of the memory, after performing at least one combination operation on the bit depth and / or bit width of different memories, generate at least one simulation layout corresponding to the memory through the pre-constructed script.

[0018] Optionally, the when it is determined that the bit depth of at least one of the target databases is less than the bit depth of the memory, and / or the bit width of at least one of the target databases is less than the bit width of the memory, after performing at least one splitting operation on the bit depth and / or bit width of the memory, generate at least one simulation layout corresponding to the memory through the pre-constructed script, includes:

[0019] When it is determined that the bit depth of at least one of the target databases is less than the bit depth of the memory, and / or the bit width of at least one of the target databases is less than the bit width of the memory, determine the splitting method and the number of splitting times of the memory according to the proportional coefficient between the bit depth and bit width of the memory; including: when it is determined that the proportional coefficient between the bit depth and bit width of the memory is greater than the first set value, split the bit depth of the memory; otherwise, split the bit width of the memory;

[0020] According to the splitting times and the maximum splitting times of the memory, perform at least one split on the bit depth or bit width of the memory to obtain a plurality of sub-memories, including: when it is determined that the splitting times of the memory are less than or equal to the maximum splitting times, perform at least one split on the bit depth or bit width of the memory to obtain a plurality of sub-memories; otherwise, stop the current process; wherein, when splitting the bit depth of the memory, the maximum splitting times are determined by the bit depth of the memory and the bit depth of the target database, and when splitting the bit width of the memory, the maximum splitting times are determined by the bit width of the memory and the bit width of the target database;

[0021] According to the bit depth and bit width of the sub-memory, select at least one of the target databases, perform a layout generation operation to generate a sub-simulation layout, and perform a packaging operation after instantiating the sub-simulation layout to generate at least one simulation layout corresponding to the memory; wherein the number of times of instantiating the sub-simulation layout is the same as the splitting times.

[0022] Optionally, after generating at least one simulation layout corresponding to the memory, the chip design method further includes at least one of the following:

[0023] Obtain the simulation information of the simulation layout, where the simulation information includes: simulation power consumption, simulation read / write frequency, and simulation area;

[0024] When it is determined that the simulation information of the simulation layout does not meet the design information of the memory, based on performing at least one split operation on the bit depth or bit width of the memory, perform a split operation on the memory again; including: when it is determined that the simulation information of the simulation layout does not meet the design information of the memory, when the difference between the simulation read / write frequency of the simulation layout and the read / write frequency of the memory is in the first interval, based on performing at least one split operation on the bit depth or bit width of the memory, perform one more split operation on the bit depth or bit width of the memory; and when it is determined that the difference between the simulation read / write frequency in the simulation parameters of the simulation layout and the read / write frequency of the memory is in the second interval, and the splitting times are even and greater than the preset splitting times, based on performing at least one split operation on the bit depth or bit width of the memory, perform split operations on both the bit depth and bit width of the memory simultaneously.

[0025] Optionally, the chip design method further includes at least one of the following operations:

[0026] Add the simulation read / write frequency in the simulation parameters of the simulation layout to the design information of the memory;

[0027] Add the difference between the simulation read / write frequency in the simulation parameters of the simulation layout and the read / write frequency of the memory to the design information of the memory;

[0028] Record the simulation information of each simulation layout through the pre-constructed script and store it in a local file.

[0029] Optionally, at least one target database includes a first target database and a second target database, and the port types of the first target database and the second target database are different; at least one simulation layout includes a first simulation layout and a second simulation layout, and the first simulation layout corresponds to the first target database, and the first simulation layout corresponds to the second target database;

[0030] The method of obtaining the simulation information of at least one of the simulation layouts, comparing the simulation information of the simulation layout with the design information of the memory, and when it is determined that the simulation information of the simulation layout is the same as the design information of the memory, taking the simulation layout as the target layout includes:

[0031] Obtain the simulation information of the first simulation layout and the second simulation layout respectively, and the simulation information includes simulation power consumption, simulation read / write frequency, and simulation area;

[0032] Select the simulation layout corresponding to the simulation read / write frequency that is the same as the read / write frequency of the memory, and when it is determined that the simulation area of the simulation layout is the same as the area of the memory, then compare the simulation power consumption of the simulation layout with the power consumption of the memory until a simulation layout that is the same as the design information of the memory is generated as the target layout.

[0033] Optionally, after taking the simulation layout as the target layout when it is determined that the simulation information of the simulation layout is the same as the design information of the memory, the chip design method further includes: performing a timing analysis on the target layout.

[0034] The embodiments of the present disclosure further provide a chip design system, including:

[0035] An acquisition unit, adapted to acquire the design information for the memory, where the design information includes: bit depth and bit width, area, power consumption, and read / write frequency; and select a plurality of alternative databases from a standard cell database;

[0036] A selection unit, adapted to select at least one target database from the plurality of alternative databases according to the bit depth and bit width of the memory; wherein, the bit depth and bit width of at least one target database are adapted to the bit depth and bit width of the memory;

[0037] A simulation unit, adapted to perform a layout generation operation on the memory according to the bit depth and bit width of the memory and the bit depth and bit width of at least one of the target databases, and generate at least one simulation layout;

[0038] A processing unit, which obtains the simulation information of at least one of the simulation layouts, compares the simulation information of the simulation layout with the design information of the memory, and when it is determined that the simulation information of the simulation layout is the same as the design information of the memory, uses the simulation layout as the target layout.

[0039] The embodiments of the present disclosure further provide a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the steps of the method described in any one of the foregoing items are implemented.

[0040] Compared with the prior art, the technical solution of the embodiments of the present disclosure has the following advantages:

[0041] In the chip design method provided by the embodiments of the present disclosure, according to the bit depth and bit width of the memory, at least one target database adapted to the bit depth and bit width of the memory can be selected from multiple alternative databases. Furthermore, according to the bit depth and bit width of the memory and the bit depth and bit width of at least one target database, a layout generation operation on the memory can be performed to generate at least one simulation layout. When it is determined that the simulation information of the simulation layout is the same as the design information of the memory, it indicates that the memory corresponding to the target simulation layout meets the design requirements, and thus the simulation layout can be used as the target layout. In this way, the read / write frequency, power consumption, and area, as well as the balance among the three, can be comprehensively considered, thereby improving the performance of the chip. Description of the Drawings

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings required for describing the embodiments of the present disclosure or the prior art. Obviously, the following described drawings are only some embodiments of this specification. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 Shows a flowchart of a chip design method in the embodiments of the present disclosure;

[0044] Figure 2 Shows a flowchart of a method for selecting an alternative database in the embodiments of the present disclosure;

[0045] Figure 3 Shows a flowchart of a method for generating a simulation layout in the embodiments of the present disclosure;

[0046] Figure 4The figure shows a schematic structural diagram of a chip design system in an embodiment of the present disclosure. Detailed implementation manners

[0047] As described in the background art, currently, it is difficult to achieve a balance among the performance, power consumption, and area of the generated memory chips, resulting in poor performance of the memory chips. The reason is as follows:

[0048] The generation process of existing memory chips often only focuses on a single performance index (such as read / write frequency), ignoring the comprehensive optimization of power consumption and area, resulting in it being difficult to achieve the best balance among the performance, power consumption, and area of the designed memory chips, and thus it is impossible to meet the requirements of performance, power consumption, and area simultaneously.

[0049] To solve the above technical problems, an embodiment of the present disclosure provides a chip design method, including: obtaining design information for a memory, where the design information includes: bit depth and bit width, area, power consumption, and read / write frequency; selecting a plurality of alternative databases from a standard cell database; selecting at least one target database from the plurality of alternative databases according to the bit depth and bit width of the memory; where the bit depth and bit width of at least one target database are adapted to the bit depth and bit width of the memory; performing a layout generation operation for the memory according to the bit depth and bit width of the memory and the bit depth and bit width of at least one target database to generate at least one simulation layout; obtaining simulation information of at least one simulation layout, and comparing the simulation information of the simulation layout with the design information of the memory. When it is determined that the simulation information of the simulation layout is the same as the design information of the memory, using the simulation layout as the target layout.

[0050] It can be seen that in the chip design method provided by the embodiment of the present disclosure, the read / write frequency, power consumption, and area, as well as the balance among the three, are comprehensively considered, so that the performance of the chip can be improved.

[0051] In order to make the above objects, features, and advantages of the embodiments of the present disclosure more obvious and understandable, the following will describe in detail the specific embodiments of the present disclosure with reference to the accompanying drawings.

[0052] See Figure 1 The flowchart of a chip design method in an embodiment of the present disclosure shown in Figure 1 As shown, in some embodiments of the present disclosure, the following steps may be performed:

[0053] S11, obtaining design information for a memory.

[0054] In some embodiments of the present disclosure, the design information can reflect the parameter information of the memory to be formed in this design and the effect to be achieved by the memory.

[0055] In some embodiments, the design information may include bit depth, bit width, area, power consumption, and read / write frequency. Among them, bit depth refers to the number of bits of binary numbers that each memory cell in the memory can store, and bit width refers to the number of bits of binary numbers that each memory cell in the memory can store and transmit in parallel; the area determines the storage capacity of the memory, and it can be understood that the larger the area of the memory, the larger the corresponding storage capacity; power consumption reflects the energy consumed by the memory during operation; read / write frequency reflects the amount of data exchanged per unit time during the operation of the memory. The higher the read / write frequency, the faster the read / write speed of the memory, and it can access data more quickly, but its power consumption will also increase.

[0056] In some embodiments of the present disclosure, the format of the design information may exist in the form of a table. For example, the parameters of the design information can be filled in the table, and when reading is required, through format conversion, the content in the table is converted into data that meets the format requirements of the design.

[0057] It should be noted that the types of design information listed in the above examples are only for illustrative purposes. In some other examples, the design information may further include: information such as the type of the memory, the write mask of the memory, the error correction code of the memory, and the array of the memory.

[0058] S12, select multiple alternative databases from the standard cell database.

[0059] In some embodiments of the present disclosure, there are various different types of databases in the standard cell database, and the specifications and parameters of each database are included. By selecting different types and sizes of databases, memories with different areas, power consumptions, and read / write frequencies can be generated.

[0060] In some embodiments, multiple target databases can be obtained from the standard cell database according to information such as the type, specification, and parameter of each database.

[0061] In some other embodiments, when determining the standard cell database, target databases can also be selected based on design requirements.

[0062] It should be noted that the standard cell database can be established in real time or obtained from an existing database. The present disclosure embodiments do not impose any restrictions on the source of the standard cell database.

[0063] S13, select at least one target database from the multiple alternative databases according to the bit depth and bit width of the memory.

[0064] In some implementations of the present disclosure, when using a database to simulate a memory, it is necessary to consider the bit depth and bit width of the memory as a basis for selection, and select at least one target database from multiple alternative databases, so that the bit depth and bit width of the target database can match the bit depth and bit width of the memory.

[0065] That is, the bit depth and bit width of at least one target database match the bit depth and bit width of the memory, so that the memory is composed of at least one of the target databases.

[0066] In some embodiments, "matching" may mean that the bit depth of the target database is the same as the bit depth of the memory, and the bit width of the target database is the same as the bit width of the memory; or, the bit depth of the target database is the same as the bit depth of the memory, and there is a proportional relationship between the bit width of the target database and the bit width of the memory (the proportionality coefficient is greater than 1 and is an integer); or, there is a proportional relationship between the bit depth of the target database and the bit depth of the memory (the proportionality coefficient is greater than 1 and is an integer), and the bit width of the target database is the same as the bit width of the memory; or, there is a proportional relationship between the bit depth of the target database and the bit depth of the memory (the proportionality coefficient is greater than 1 and is an integer), and there is a proportional relationship between the bit width of the target database and the bit width of the memory (the proportionality coefficient is greater than 1 and is an integer).

[0067] In short, there is at least one target database whose bit width and bit depth can meet the requirements of the memory, and thus at least one simulation layout corresponding to the bit depth and bit width of the memory can be generated through at least one database.

[0068] S14. Perform a layout generation operation for the memory according to the bit depth and bit width of the memory and the bit depth and bit width of at least one of the target databases, and generate at least one simulation layout.

[0069] In some implementations of the present disclosure, through step S13, a target database that matches the bit depth and bit width of the memory can be obtained. Considering that the ratio coefficients of the bit depth and bit width of the memory and the bit depth and bit width of the target database are different, corresponding layout generation operations can be performed to generate at least one simulation layout.

[0070] S15. Obtain the simulation information of at least one of the simulation layouts, compare the simulation information of the simulation layout with the design information of the memory, and when it is determined that the simulation information of the simulation layout is the same as the design information of the memory, use the simulation layout as the target layout.

[0071] In some implementations of the present disclosure, a memory may be emulated through multiple databases of different types. The bit widths and bit depths of these emulated layouts are the same. At this time, the emulation information of the emulated layouts can be compared with the design information of the memory to determine the target emulated layout that is the same as the design information of the memory.

[0072] In some embodiments, when performing the comparison operation, the emulation read / write frequency of the emulated layout can be compared with the read / write frequency of the memory first. When the two are the same, then the emulation area of the emulated layout and the area of the memory, and the emulation power consumption of the emulated layout and the power consumption of the memory can be compared in sequence, so as to use the emulated layout when the emulation information of the emulated layout is the same as the design information of the memory as the target layout.

[0073] That is, the target emulated layout can be selected from at least one emulated layout by sequentially using the read / write frequency, area, and power consumption of the memory as the reference benchmarks. In this way, the read / write frequency, power consumption, and area, as well as the balance among the three, can be comprehensively considered, thus improving the performance of the chip.

[0074] In some embodiments of the present disclosure, for memories of the same type and the same specifications, when emulating using different databases, the read / write frequencies, areas, and power consumptions shown by the emulated layouts are also different.

[0075] For example, for a certain database, when emulating a memory with a bit width of 32 and a bit depth of 64, the performance is better than that of the memory emulated by other databases; while when emulating a memory with a bit width of 44 and a bit depth of 64, the performance is much worse than that of the memory emulated by other databases. Therefore, when selecting a database, the selected database needs to meet the selection requirements.

[0076] As an example, referring to Figure 2 the flowchart of a method for selecting an alternative database in an embodiment of the present disclosure shown in Figure 2 as shown, the following steps can be performed:

[0077] S21, based on the type of the memory to be designed, select multiple databases that at least include the type of the memory.

[0078] In some embodiments of the present disclosure, the type of the memory determines the type of the database to be used.

[0079] For example, if the memory is a single-port memory, the selected databases should at least include types such as spsram, sprf, and uhdsprf.

[0080] S22, draw the performance curves of each database, and the parameters in the performance curves at least include: area, power consumption, and read / write frequency.

[0081] In some embodiments of the present disclosure, through step S21, a large number of databases can be obtained, and there are significant differences between the databases. Therefore, by reading the local files corresponding to each memory, the performance curves of each database can be plotted to obtain different parameters and the performance of the database under different parameter values.

[0082] S23, while keeping the read / write frequency unchanged, by comparing the area and power consumption in the performance curves of each database, the databases that meet the design requirements are used as alternative databases.

[0083] In some embodiments of the present disclosure, with the read / write frequency as the reference benchmark, the area parameters and power consumption parameters of each database at different read / write frequencies can be obtained respectively. After multiple rounds of comparison, the databases that meet the design requirements (i.e., when the read / write frequencies are the same, the area is lower than the set area and the power consumption is lower than the set power consumption) are used as alternative databases.

[0084] In other words, at the same read / write frequency, compare the area and power consumption to obtain the priority of using databases in different intervals. If the area and power consumption of type-a databases are completely inferior to those of type-b databases in the same interval, then type-b databases are used as alternative databases.

[0085] Through the above selection method, multiple alternative databases that meet the design requirements can be obtained, thereby further improving the balance among the performance, power consumption, and area of the memory to be formed, and further improving the performance of the chip.

[0086] In some embodiments of the present disclosure, as mentioned above, the bit depth refers to the number of binary digits that each memory cell in the memory can store, and the bit width refers to the number of binary digits that each memory cell can store and transmit in parallel.

[0087] For example, a memory with a bit depth of 256 and a bit width of 64 can store 256 data with a width of 64 bits.

[0088] In this case, referring to Figure 3 the flowchart of a simulation layout generation method in the embodiments of the present disclosure shown in Figure 3 shown, the following steps can be executed:

[0089] S31, compare the relationship between the bit depth of the target database and the bit depth of the memory, and the relationship between the bit width of the target database and the bit width of the memory.

[0090] In some embodiments of the present disclosure, when performing layout generation operations, based on the relationship between the bit depth of the target database and the bit depth of the memory, and the relationship between the bit width of the target database and the bit width of the memory, the corresponding operation steps may be determined.

[0091] S32. When it is determined that the bit depth of the target database is the same as that of the memory and the bit width of the target database is the same as that of the memory, perform a layout generation operation on the target database through a pre-constructed script to generate a simulation layout corresponding to the memory.

[0092] In some embodiments of the present disclosure, when it is determined that the bit depth of the target database is the same as that of the memory and the bit width of the target database is the same as that of the memory, it indicates that the target database can be used for simulation operations. Thus, the design information of the memory can be read through a pre-constructed script, and a layout generation operation can be performed on at least one target database to obtain a corresponding simulation layout.

[0093] Among them, the "script" refers to a set of automated scripts for performing layout generation operations, which can automatically perform layout generation operations based on the design information of the memory and at least one target database.

[0094] In some embodiments, assume that the bit depth of the target database is 256 and the bit width is 64, while the bit depth of the memory is 256 and the bit width is 64. Then, this target database can be used to perform the generation operation of the simulation layout.

[0095] S33. When it is determined that the bit depth of the target database is less than that of the memory and / or the bit width of the target database is less than that of the memory, after performing at least one splitting operation on the bit depth and / or bit width of the memory, generate at least one simulation layout corresponding to the memory through the pre-constructed script.

[0096] In some embodiments of the present disclosure, if it is determined that the bit depth of the target database is less than that of the memory and / or the bit width of the target database is less than that of the memory, it indicates that a corresponding simulation layout cannot be generated using the currently selected target database. At this time, at least one splitting operation can be performed on the bit depth and / or bit width of the memory to reduce the bit depth and / or bit width of the memory to be processed, so that the bit depth and bit width of the memory after splitting are consistent with the bit depth and bit width of the target database. Thus, the design information of the memory can be read through a pre-constructed script, and a layout generation operation can be performed on at least one target database to obtain a corresponding simulation layout.

[0097] As an example, assume that the memory is a device with a bit depth of 256 and a bit width of 64, which can store 256 data with a width of 64 bits. When the currently selected target database cannot directly generate this memory, it can be split into two memories of 128x64 (i.e., bit depth split), or four memories of 64x64; or, split into two memories of 256x32 (i.e., bit width split), or four memories of 256x16, so that one of the split methods can be consistent with the bit depth and bit width of the target database.

[0098] It should be noted that, first, after at least one split operation on the bit depth and / or bit width of the memory, the bit depth and bit width of the split memory are consistent with the bit depth and bit width of at least one target database; second, when splitting the bit depth and / or bit width of the memory, multiple sub-memories with different bit depths and bit widths can be obtained. When selecting the target database through the sub-memory, the sub-memory with fewer split times can be preferentially selected to select the corresponding target database, because whether it is area or power consumption, the more splits, the more resources are wasted.

[0099] For example, for a memory device with a bit depth of 256 and a bit width of 64, it can be split into two memories of 128x64 (i.e., bit depth split), or four memories of 64x64. This is to preferentially select the split into two memories of 128x64 as a reference benchmark to select the target database.

[0100] S34. When it is determined that the bit depth of the target database is greater than the bit depth of the memory, and / or the bit width of the target database is greater than the bit width of the memory, after at least one combination operation on the bit depth and / or bit width of different memories, at least one simulation layout corresponding to the memory is generated through the pre-constructed script.

[0101] In some embodiments of the present disclosure, if it is determined that the bit depth of the target database is greater than the bit depth of the memory, and / or the bit width of the target database is greater than the bit width of the memory, it means that using a currently selected target database can generate a corresponding simulation layout, but the bit width and / or bit depth of the simulation layout to be generated is greater than the bit depth and / or bit width of the memory to be formed. At this time, at least one combination operation can be performed on the bit depth and / or bit width of different memories to increase the bit depth and / or bit width of the memory to be formed, so that the bit depth and bit width of the memory after the combination process are consistent with the bit depth and bit width of the target database, so that the design information of the memory can be read through the pre-constructed script, and a layout generation operation is performed on at least one target database to obtain a corresponding simulation layout.

[0102] Thus, according to the relationship between the bit depth of the target database and the bit depth of the memory, and the relationship between the bit width of the target database and the bit width of the memory, it is possible to ensure that the selected target database can generate a simulation layout that meets the requirements of the bit depth and bit width of the memory, thereby improving the generation efficiency and avoiding rework caused by the inability to generate the memory.

[0103] In some embodiments of the present disclosure, when it is determined that the bit depth of the target database is less than the bit depth of the memory and / or the bit width of the target database is less than the bit width of the memory, the splitting method can be determined according to the relationship between the bit depth and bit width of the memory, and after splitting, a corresponding simulation layout can be generated through a pre-constructed script.

[0104] In some embodiments of the present disclosure, step S33 may specifically include:

[0105] S331, when it is determined that the bit depth of at least one of the target databases is less than the bit depth of the memory and / or the bit width of at least one of the target databases is less than the bit width of the memory, determine the splitting method and the number of splitting times for the memory according to the proportional coefficient between the bit depth and bit width of the memory.

[0106] In some embodiments of the present disclosure, if it is determined that the bit depth of the target database is less than the bit depth of the memory and / or the bit width of the target database is less than the bit width of the memory, it means that a corresponding simulation layout cannot be generated using the currently selected target database. At this time, the bit depth and / or bit width of the memory can be split, and the number of splitting times can be determined simultaneously.

[0107] Furthermore, different proportional relationships between the bit depth and bit width of the memory result in different splitting methods.

[0108] In some embodiments, when it is determined that the proportional coefficient between the bit depth and bit width of the memory is greater than a first set value (the first set value is greater than 1, for example, the first set value can be 2), split the bit depth of the memory; otherwise, split the bit width of the memory.

[0109] Specifically, if the proportional coefficient between the bit depth and bit width of the memory is greater than the first set value, it means that the bit depth of the memory is greater than the bit width. At this time, the bit depth of the memory can be split while keeping the bit width unchanged.

[0110] As an example, if the memory is a device with a bit depth of 256 and a bit width of 64, it can store 256 data with a width of 64 bits. When the bit width of the selected target database is less than 256, this memory cannot be directly generated, and the ratio of 256 to 64 is 4, which is greater than the first set value of 2. Therefore, the memory can be split once to form two memories of 128x64.

[0111] In some embodiments of the present disclosure, the maximum number of splits can be determined by the bit depth of the memory and the bit depth of the target database, or by the bit width of the memory and the bit width of the target database. For example, when splitting the bit depth of the memory, the maximum number of splits is determined by the bit depth of the memory and the bit depth of the target database; when splitting the bit width of the memory, the maximum number of splits is determined by the bit width of the memory and the bit width of the target database.

[0112] In one example, the maximum number of splits can be the ratio of the bit depth of the memory to the bit depth of the target database, or the maximum number of splits can be the ratio of the bit width of the memory to the bit width of the target database.

[0113] In this case, in S332, according to the number of splits of the memory and the maximum number of splits, the memory is split by bit depth or bit width at least once to obtain a plurality of sub-memories.

[0114] In some embodiments of the present disclosure, when determining the splitting method and the number of splits performed on the memory, it may be necessary to judge whether the memory can be split according to the actual number of splits of the memory.

[0115] For example, when it is determined that the number of splits of the memory is less than or equal to the maximum number of splits, it indicates that the bit depth or bit width of the memory can be split at least once to obtain a plurality of sub-memories.

[0116] Specifically, when it is determined that the number of splits of the memory is less than or equal to the maximum number of splits, the bit depth or bit width of the memory is split at least once to obtain a plurality of sub-memories; otherwise, the current process is stopped.

[0117] In S333, according to the bit depth and bit width of the sub-memory, at least one of the target databases is selected, and a layout generation operation is performed to generate a sub-simulation layout, and after instantiating the sub-simulation layout, a packaging operation is performed to generate at least one simulation layout corresponding to the memory.

[0118] In some embodiments of the present disclosure, when the splitting operation is completed, a plurality of sub-memories can be obtained. Furthermore, a target database with the same bit depth and bit width as the sub-memory can be selected. After performing a layout generation operation on the selected target database to generate a sub-simulation layout, and after instantiating the sub-simulation layout, a plurality of sub-simulation layouts can be obtained, and then a packaging operation is performed to generate at least one simulation layout corresponding to the memory.

[0119] In some embodiments, the number of times of instantiating the sub-simulation layout is the same as the number of splits. That is, the total number of the sub-simulation layouts formed by instantiation and the initial sub-simulation layout is the same as the number of sub-memories formed by splitting.

[0120] In some embodiments of the present disclosure, the inventors further found that by adopting the above solution, a simulation layout that meets the bit depth and bit width requirements of the memory can be generated. Considering the influence of power consumption and read / write frequency, when generating the simulation layout, the simulation layout can also be verified to determine whether the power consumption and read / write frequency of the simulation layout meet the requirements, so as to further balance the power consumption, area, and read / write frequency of the memory.

[0121] As an example, the chip design method further includes: obtaining simulation information of the simulation layout, where the simulation information includes: simulation power consumption, simulation read / write frequency, and simulation area.

[0122] In some embodiments of the present disclosure, the simulation parameters of the simulation layout can be obtained by reading the local file corresponding to the simulation layout. Since the simulation layout corresponds to the memory, information such as the power consumption, read / write frequency, and area of the simulation layout formed by the current generation method can be obtained.

[0123] Next, when it is determined that the simulation information of the simulation layout does not meet the design information of the memory, based on performing at least one splitting operation on the bit depth or bit width of the memory, the splitting operation is performed on the memory again.

[0124] Specifically, by comparing the simulation parameters of the simulation layout with the design information of the memory, it can be determined whether the simulation parameters can meet the requirements of the design information of the memory, so as to determine whether it is necessary to perform the splitting operation on the memory again.

[0125] As an alternative example, when it is determined that the simulation information of the simulation layout does not meet the design information of the memory, when the difference between the simulation read / write frequency of the simulation layout and the read / write frequency of the memory is in the first interval, based on performing at least one splitting operation on the bit depth or bit width of the memory, an additional splitting operation on the bit depth or bit width of the memory is performed.

[0126] Specifically, when it is determined that the difference between the simulation read / write frequency of the simulation layout and the read / write frequency of the memory is in the first interval, it indicates that the simulation read / write frequency of the simulation layout is much lower than the read / write frequency of the memory (for example, the simulation read / write frequency is 800 mHz, while the read / write frequency is 1200 mHz). At this time, after re-splitting and processing, a simulation layout can be generated to increase the simulation read / write frequency.

[0127] As another alternative example, when it is determined that the difference between the simulation read / write frequency in the simulation parameters of the simulation layout and the read / write frequency of the memory is within the second interval, and the number of splitting times is even and greater than the preset number of splitting times, on the basis of performing at least one splitting operation on the bit depth or bit width of the memory, splitting operations are simultaneously performed on both the bit depth and bit width of the memory.

[0128] Among them, the first interval is much larger than the second interval.

[0129] In some embodiments of the present disclosure, when it is determined that the difference between the simulation read / write frequency in the simulation parameters of the simulation layout and the read / write frequency of the memory is within the second interval, it indicates that the frequency difference between the two is small, and the bit depth and bit width of the memory can be split simultaneously to make their frequencies consistent.

[0130] For example, when it is determined that the difference between the simulation read / write frequency in the simulation parameters of the simulation layout and the read / write frequency of the memory is within the second interval, it can be determined whether the current number of splitting times is even, and on the basis that the number of splitting times is even and greater than or equal to 4, splitting operations are simultaneously performed on both the bit depth and bit width of the memory.

[0131] As an alternative example, taking the number of splitting times as 6 times as an example, at the beginning, the bit depth is split into 6 - 2 - i (i with a base of 0), and the width is split into 2 + i; then, as i increases, there will be combinations such as the bit depth being split into 4 and the width being split into 2; the bit depth being split into 3 and the width being split into 3; the bit depth being split into 2 and the width being split into 4, etc., until a simulation layout that meets the requirements is generated.

[0132] In some embodiments of the present disclosure, after generating at least one simulation layout corresponding to the memory, the chip design method further includes adding the simulation read / write frequency in the simulation parameters of the simulation layout to the design information of the memory; or adding the difference between the simulation read / write frequency in the simulation parameters of the simulation layout and the read / write frequency of the memory to the design information of the memory.

[0133] In this way, during the subsequent generation process of the simulation layout, if the memory is split into the same size, through the pre-recorded data, the read / write frequencies can be directly compared, so that the simulation layout generation operation can be performed only when the read / write frequencies are the same.

[0134] For example, a memory with a frequency of 1000 mHz has been generated before, but now the requirement is modified, for example, a memory with 1200 mHz is required. By comparing the stored information values, it is found that if the previous formation method is adopted, the difference in the read / write frequency is 200 mHz. At this time, the splitting operation can be directly performed without having to perform the splitting operation after generating the simulation layout, improving the generation efficiency.

[0135] In some embodiments of the present disclosure, the simulation information of each simulation layout can also be recorded through the pre-built script and stored in a local file. In this way, all memory information can be obtained intuitively. If subsequent updates, optimizations, or regenerations are required, the local file can be directly called, reducing the required time and improving efficiency.

[0136] In some alternative examples, after the simulation layout is generated, all the information required by the user can be added to the design information in the form of a script. All the information required by the user includes split parameters, read / write frequencies, area, power consumption, etc.

[0137] In some embodiments of the present disclosure, when selecting the target database, at least one target database includes a first target database and a second target database, and the port types of the first target database and the second target database are different.

[0138] Correspondingly, at least one simulation layout includes a first simulation layout and a second simulation layout, and the first simulation layout corresponds to the first target database, and the first simulation layout corresponds to the second target database.

[0139] In this case, the method of obtaining the simulation information of at least one of the simulation layouts, comparing the simulation information of the simulation layout with the design information of the memory, and when it is determined that the simulation information of the simulation layout is the same as the design information of the memory, using the simulation layout as the target layout includes:

[0140] Obtain the simulation information of the first simulation layout and the second simulation layout respectively, where the simulation information includes simulation power consumption, simulation read / write frequency, and simulation area;

[0141] Select the simulation layout corresponding to the simulation read / write frequency that is the same as the read / write frequency of the memory, and when it is determined that the simulation area of the simulation layout is the same as the area of the memory, then compare the simulation power consumption of the simulation layout with the power consumption of the memory until a simulation layout that is the same as the design information of the memory is generated as the target layout.

[0142] Specifically, during the generation process of the simulation layout, the first simulation layout and the second simulation layout may be generated simultaneously. At this time, the read / write frequencies of the first simulation layout and the second simulation layout can be compared in advance, and the simulation layout with the larger read / write frequency can be selected therefrom. For example, at least one of the first simulation layout and / or the second simulation layout can be selected.

[0143] Next, compare the area and power consumption parameters of the simulated layout and the memory in sequence until a simulated layout identical to the design information of the memory is obtained as the target layout; otherwise, re - execute the layout generation operation.

[0144] As an optional example, the first simulated layout is sprf 1024x64, and the second simulated layout is spsram1024x64. Assuming that the read - write frequency of the first simulated layout is greater than that of the second simulated layout, the first simulated layout is used as the simulated layout for comparison with the memory. If the simulated read - write frequency, simulated area, and simulated power consumption of the first simulated layout are the same as the read - write frequency, area, and power consumption of the memory, then the first simulated layout is used as the target layout; otherwise, the memory is split again and a new simulated layout is regenerated.

[0145] In some optional examples, after determining the target simulated layout, perform timing analysis on the target layout, and when it is determined that the timing of the target simulated layout meets the set timing, use the memory corresponding to the target simulated layout as the target memory.

[0146] Specifically, by using the above steps, a simulated layout that meets the design information requirements can be designed. During the actual operation of the memory, the timing of the memory needs to meet the time relationship and timing constraints of the signals in the circuit or system to ensure that when the memory is applied to the circuit or system, the memory can operate normally according to the expected performance and timing specifications.

[0147] In some embodiments, timing analysis techniques (such as static timing analysis) can be used to ensure that the memory can meet the timing requirements from the perspective of the required process.

[0148] Among them, the timing requirements may include: timing constraints (such as clock frequency, maximum delay, and timing relationship); timing analysis, that is, the process of verifying whether the circuit timing requirements meet the design specifications; timing logic modeling, that is, the relationship involving registers, clock signals, and timing logic design; delay control, that is, allowing specific time delays to be introduced during statement execution, including conventional delays and embedded delays.

[0149] Furthermore, after it is determined that the timing of the target simulated layout meets the set timing, the actual chip design and test verification process can be carried out to ensure that its read - write frequency, power consumption, and area performance in actual applications meet the expectations.

[0150] The above chip design method has been described in detail through some embodiments. To enable those skilled in the art to better understand and implement it, the corresponding products are also described in detail through some embodiments below.

[0151] See Figure 4Schematic diagram of the structure of the chip design system shown. In the embodiments of the present disclosure, the chip design system 100 includes:

[0152] An acquisition unit 110, adapted to acquire design information for a memory, the design information including: bit depth and bit width, area, power consumption, and read / write frequency; and, select a plurality of alternative databases from a standard cell database;

[0153] A selection unit 120, adapted to select at least one target database from the plurality of alternative databases according to the bit depth and bit width of the memory; wherein, the bit depth and bit width of at least one target database are adapted to the bit depth and bit width of the memory;

[0154] A simulation unit 130, adapted to perform a layout generation operation for the memory according to the bit depth and bit width of the memory, and the bit depth and bit width of at least one of the target databases, to generate at least one simulation layout;

[0155] A processing unit 140, acquires the simulation information of at least one of the simulation layouts, and compares the simulation information of the simulation layout with the design information of the memory. When it is determined that the simulation information of the simulation layout is the same as the design information of the memory, the simulation layout is used as the target layout.

[0156] It can be understood that the above division of each unit is only a division of logical functions. In actual implementation, it can be fully or partially integrated into a physical entity, or physically separated. In addition, the above units can be implemented in the form of a processor invoking software.

[0157] For example, the system adopted includes a processor, which is connected to a memory. Instructions are stored in the memory, and the processor calls the instructions stored in the memory to implement any one of the methods in the above embodiments or to implement the functions of each unit. The processor is, for example, a general-purpose processor, such as a central processing unit (CPU), and the memory can be an in-device memory or an out-device memory of the device. Alternatively, the above units can be implemented in the form of hardware circuits, and the functions of some or all of the units can be implemented through the design of the hardware circuits, which can be understood as one or more processors. For example, in one implementation, the hardware circuit is an application specific integrated circuit (ASIC), and the functions of some or all of the above units are implemented through the design of the logical relationships of the internal components of the circuit; again, in another implementation, the hardware circuit can be implemented by a programmable logic device (PLD), which can include a large number of logic gate circuits, and the logical relationships between the logic gate circuits are configured through a configuration file to implement the functions of some or all of the above units. All units of the above system can be all implemented in the form of the processor calling a program, or all implemented in the form of hardware circuits, or some implemented in the form of the processor calling a program and the remaining part implemented in the form of hardware circuits.

[0158] Embodiments of the present disclosure also provide a computer system suitable for implementing a chip design method.

[0159] It should be noted that the computer system of the electronic device shown below is only an example and should not bring any limitations to the functions and usage scope of the embodiments of the present application.

[0160] Among them, the computer system includes a central processing unit (CPU), which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) or the program loaded from the storage part into the random access memory (RAM), such as performing the method described in the above embodiments. In the RAM, various programs and data required for system operation are also stored. The CPU, ROM, and RAM are connected to each other through a bus 304. The input / output (I / O) interface is also connected to the bus.

[0161] The following components are connected to the I / O interface: an input section including a keyboard, a mouse, etc.; an output section including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section including a hard disk, etc.; and a communication section including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section performs communication processing via a network such as the Internet. A drive is also connected to the I / O interface as needed. A removable medium such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is mounted on the drive as needed so that a computer program read therefrom is installed into the storage section as needed.

[0162] Specifically, according to an embodiment of the present application, the processes described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for performing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication section, and / or installed from a removable medium. When the computer program is executed by a central processing unit (CPU), various functions defined in the system of the present application are performed.

[0163] It should be noted that the computer-readable medium shown in the embodiments of the present application may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0164] In this application, a computer-readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in conjunction with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable computer program. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted by any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0165] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. Among them, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the above-mentioned module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0166] The units involved in the embodiments described in this application can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not, in some cases, constitute a limitation on the unit itself.

[0167] According to one aspect of the present application, a computer program product or a computer program is provided, which includes computer instructions stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods provided in the above various alternative implementation manners.

[0168] As another aspect, the present application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiments; or may exist separately without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the above embodiments.

[0169] It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present application, the features and functions of the two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0170] Through the description of the above embodiments, those skilled in the art can easily understand that the example embodiments described herein can be implemented by software, or by a combination of software and necessary hardware. Therefore, the technical solutions according to the embodiments of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (such as a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the embodiments of the present application.

[0171] Although the embodiments of the present disclosure are disclosed as above, the present disclosure is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of this specification should be subject to the scope defined by the claims.

Claims

1. A chip design method, characterized in that: include: Acquire design information for the memory, the design information including: bit depth and bit width, area, power consumption, and read / write frequency; Select multiple candidate databases from the standard unit database; Selecting at least one target database from the plurality of candidate databases according to the bit depth and bit width of the memory; wherein the bit depth and bit width of the at least one target database are adapted to the bit depth and bit width of the memory; According to the bit depth and bit width of the memory and the bit depth and bit width of at least one of the target databases, a layout generation operation is performed for the memory to generate at least one simulation layout; Acquire simulation information of at least one of the simulation layouts, and compare the simulation information of the simulation layout with the design information of the memory, and when it is determined that the simulation information of the simulation layout is the same as the design information of the memory, use the simulation layout as the target layout; The step of performing a layout generation operation for the memory according to the bit depth and bit width of the memory and the bit depth and bit width of at least one of the target databases to generate at least one simulation layout includes: When it is determined that the bit depth of the target database is the same as the bit depth of the memory, and the bit width of the target database is the same as the bit width of the memory, a layout generation operation is performed on the target database through a pre-built script to generate a simulation layout corresponding to the memory; When it is determined that the bit depth of the target database is smaller than the bit depth of the memory, and / or the bit width of the target database is smaller than the bit width of the memory, after performing at least one splitting operation on the bit depth and / or the bit width of the memory, at least one simulation layout corresponding to the memory is generated through the pre-built script; When it is determined that the bit depth of the target database is greater than the bit depth of the memory, and / or the bit width of the target database is greater than the bit width of the memory, after performing at least one combination operation on the bit depths and / or bit widths of different memories, at least one simulation layout corresponding to the memory is generated through the pre-built script; Wherein, when it is determined that the bit depth of the target database is smaller than the bit depth of the memory, and / or the bit width of the target database is smaller than the bit width of the memory, after performing at least one splitting operation on the bit depth and / or bit width of the memory, generating at least one simulation layout corresponding to the memory through the pre-built script, includes: When it is determined that the bit depth of at least one of the target databases is smaller than the bit depth of the memory, and / or the bit width of at least one of the target databases is smaller than the bit width of the memory, determining a splitting method and a splitting number of times of the memory according to a proportionality coefficient between the bit depth and the bit width of the memory; comprising: when it is determined that the proportionality coefficient between the bit depth and the bit width of the memory is greater than a first set value, splitting the bit depth of the memory; otherwise, splitting the bit width of the memory; According to the number of times the memory is split and the maximum number of times the memory is split, the memory is split at least once in bit depth or bit width to obtain a plurality of sub-memories; including: when it is determined that the number of times the memory is split is less than or equal to the maximum number of times the memory is split, the bit depth or bit width of the memory is split at least once to obtain a plurality of sub-memories; otherwise, the current process is stopped; wherein, when the bit depth of the memory is split, the maximum number of times the memory is split is determined by the bit depth of the memory and the bit depth of the target database, and when the bit width of the memory is split, the maximum number of times the memory is split is determined by the bit width of the memory and the bit width of the target database; According to the bit depth and bit width of the sub-memory, at least one of the target databases is selected, and a layout generation operation is performed to generate a sub-simulation layout, and a packaging operation is performed after the sub-simulation layout is instantiated to generate at least one simulation layout corresponding to the memory; wherein the number of times the sub-simulation layout is instantiated is the same as the number of splitting times.

2. The chip design method according to claim 1, characterized in that: The selecting a plurality of candidate databases from the standard unit database comprises: Based on the type of memory to be designed, selecting a plurality of databases including at least the type of memory; Draw a performance curve for each database, wherein the parameters in the performance curve include at least: area, power consumption, and read / write frequency; While keeping the read and write frequencies unchanged, the database that meets the design requirements is selected as the candidate database by comparing the area and power consumption in the performance curves of each database.

3. The chip design method according to claim 1, characterized in that: After generating at least one simulation layout corresponding to the memory, the chip design method further includes at least one of the following: Acquire simulation information of the simulation layout, the simulation information including: simulation power consumption, simulation read / write frequency and simulation area; When it is determined that the simulation information of the simulation layout does not meet the design information of the memory, on the basis of performing at least one splitting operation on the bit depth or bit width of the memory, performing a splitting operation on the memory again; including: when it is determined that the simulation information of the simulation layout does not meet the design information of the memory, when it is determined that the difference between the simulation read and write frequency of the simulation layout and the read and write frequency of the memory is in a first interval, on the basis of performing at least one splitting operation on the bit depth or bit width of the memory, adding one more bit depth or bit width splitting operation on the memory; and when it is determined that the difference between the simulation read and write frequency in the simulation parameters of the simulation layout and the read and write frequency of the memory is in a second interval, and the number of splitting times is an even number and greater than a preset number of splitting times, on the basis of performing at least one splitting operation on the bit depth or bit width of the memory, performing a splitting operation on both the bit depth and the bit width of the memory.

4. The chip design method according to claim 3, characterized in that: Also includes at least one of the following operations: Adding the simulation read and write frequencies in the simulation parameters of the simulation layout to the design information of the memory; Adding the difference between the simulation read / write frequency in the simulation parameters of the simulation layout and the read / write frequency of the memory to the design information of the memory; The simulation information of each simulation layout is recorded through the pre-built script and stored in a local file.

5. The chip design method according to claim 1, characterized in that: At least one target database includes a first target database and a second target database, and the port types of the first target database and the second target database are different; at least one simulation layout includes a first simulation layout and a second simulation layout, and the first simulation layout corresponds to the first target database, and the second simulation layout corresponds to the second target database; The acquiring simulation information of at least one of the simulation layouts, and comparing the simulation information of the simulation layout with the design information of the memory, and when it is determined that the simulation information of the simulation layout is the same as the design information of the memory, taking the simulation layout as the target layout, comprises: Respectively acquiring simulation information of the first simulation layout and the second simulation layout, the simulation information including simulation power consumption, simulation read / write frequency, and simulation area; Select the simulation layout corresponding to the simulation read and write frequency that is the same as the read and write frequency of the memory, and when it is determined that the simulation area of ​​the simulation layout is the same as the area of ​​the memory, compare the simulation power consumption of the simulation layout with the power consumption of the memory, until a simulation layout with the same design information as the memory is generated as the target layout.

6. The chip design method according to claim 1, characterized in that: When it is determined that the simulation information of the simulation layout is the same as the design information of the memory, after taking the simulation layout as the target layout, the chip design method further includes: performing timing analysis on the target layout.

7. A chip design system, characterized in that: include: An acquisition unit, adapted to acquire design information for a memory, the design information including: bit depth and bit width, area, power consumption, and read / write frequency; and select a plurality of candidate databases from a standard cell database; A selection unit, adapted to select at least one target database from the plurality of candidate databases according to the bit depth and bit width of the memory; wherein the bit depth and bit width of the at least one target database are adapted to the bit depth and bit width of the memory; A simulation unit, adapted to perform a layout generation operation for the memory according to the bit depth and bit width of the memory and the bit depth and bit width of at least one of the target databases, and generate at least one simulation layout; A processing unit, which obtains simulation information of at least one of the simulation layouts, and compares the simulation information of the simulation layout with the design information of the memory, and when it is determined that the simulation information of the simulation layout is the same as the design information of the memory, uses the simulation layout as the target layout; Wherein, the simulation unit is also used for: When it is determined that the bit depth of the target database is the same as the bit depth of the memory, and the bit width of the target database is the same as the bit width of the memory, a layout generation operation is performed on the target database through a pre-built script to generate a simulation layout corresponding to the memory; When it is determined that the bit depth of the target database is smaller than the bit depth of the memory, and / or the bit width of the target database is smaller than the bit width of the memory, after performing at least one splitting operation on the bit depth and / or the bit width of the memory, at least one simulation layout corresponding to the memory is generated through the pre-built script; When it is determined that the bit depth of the target database is greater than the bit depth of the memory, and / or the bit width of the target database is greater than the bit width of the memory, after performing at least one combination operation on the bit depths and / or bit widths of different memories, at least one simulation layout corresponding to the memory is generated through the pre-built script; Wherein, the simulation unit is also used for: When it is determined that the bit depth of at least one of the target databases is smaller than the bit depth of the memory, and / or the bit width of at least one of the target databases is smaller than the bit width of the memory, determining a splitting method and a splitting number of times of the memory according to a proportionality coefficient between the bit depth and the bit width of the memory; comprising: when it is determined that the proportionality coefficient between the bit depth and the bit width of the memory is greater than a first set value, splitting the bit depth of the memory; otherwise, splitting the bit width of the memory; According to the number of times the memory is split and the maximum number of times the memory is split, the memory is split at least once in bit depth or bit width to obtain a plurality of sub-memories; including: when it is determined that the number of times the memory is split is less than or equal to the maximum number of times the memory is split, the bit depth or bit width of the memory is split at least once to obtain a plurality of sub-memories; otherwise, the current process is stopped; wherein, when the bit depth of the memory is split, the maximum number of times the memory is split is determined by the bit depth of the memory and the bit depth of the target database, and when the bit width of the memory is split, the maximum number of times the memory is split is determined by the bit width of the memory and the bit width of the target database; According to the bit depth and bit width of the sub-memory, at least one of the target databases is selected, and a layout generation operation is performed to generate a sub-simulation layout, and a packaging operation is performed after the sub-simulation layout is instantiated to generate at least one simulation layout corresponding to the memory; wherein the number of times the sub-simulation layout is instantiated is the same as the number of splitting times.

8. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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