Chip power consumption evaluation method, device, equipment, storage medium and program product

Abstract

The present invention relates to the field of chip technology, and discloses a chip power consumption evaluation method, device, equipment, storage medium and program product. The method comprises: obtaining the RTL code and standard cell library information of the chip to be tested, performing power consumption profile simulation in the RTL dimension, obtaining power consumption profile data, generating multiple candidate time windows based on the power consumption profile data, performing waveform simulation on the chip to be tested, obtaining each gate-level waveform, performing power consumption calculation in the gate-level dimension based on the gate-level waveform, obtaining multiple power consumption calculation results, and generating target power consumption results based on the multiple power consumption calculation results based on preset conditions. The present invention realizes the fully automatic search and configuration of time windows based on power consumption profile data, and performs gate-level power consumption calculation on the selected candidate time windows respectively, and finally selects the target power consumption result that meets the preset conditions, which greatly reduces the possibility of manual intervention and error, and improves the accuracy and efficiency of power consumption analysis.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip power consumption evaluation method, device, equipment, storage medium and program product. Background Art

[0002] With the advancement of manufacturing processes and packaging technologies, the integration density (i.e., the number of transistors per unit volume) and power density of integrated circuits (ICs) continue to increase, making power consumption a key consideration in IC design. Power consumption analysis is essential at every stage of chip design. Understanding the chip's power consumption and the proportion of power consumption by component can be crucial for identifying areas that exceed expectations and providing optimization recommendations. This is crucial for ultimately achieving power consumption targets.

[0003] Power analysis can be divided into three phases, depending on the chip development stage: front-end RTL (Register Transfer Language), mid-end synthesis, and back-end PR. Depending on the presence of marker files reflecting signal flipping behavior, power analysis can be further categorized as vector-based (with waveforms) or vector-less (without waveforms). Because vector-less power analysis cannot guarantee accuracy, it is typically used only as a rough estimate when waveform files are unavailable. However, vector-based power analysis, based on the back-end PR netlist, is highly accurate and is often used as a standard for power analysis and signoff.

[0004] However, while power analysis using a vector-based backend PR netlist offers high accuracy, obtaining post-simulation waveforms based on the PR netlist typically occurs in the middle or late stages of chip development. Furthermore, post-simulation waveforms are time-consuming and difficult to debug, often taking weeks or more. This makes obtaining accurate power analysis results as quickly as possible a thorny issue.

[0005] On the other hand, waveform time windows are crucial in power scenario selection. Currently, commonly used selection methods include waveform analysis, toggle rate statistics, and power profiling. In waveform analysis, designers specify the time windows for power scenarios based on their understanding of the design. However, due to design complexity and insufficient understanding of physical information (such as the design's RLC and power model), the resulting windows often deviate significantly from the windows with the highest power consumption. Toggle rate statistics, because they fail to consider the netlist's physical and timing information, can also lead to significant errors in power calculations in some cases, resulting in inaccurate time window selection. While power profiling methods perform simple cell mapping and reconstruction of clock and buffer trees, they still exhibit significant errors compared to the power profiles derived from simulations on the actual back-end netlist. Existing methods do not address this error. Furthermore, these methods still rely on designers observing the power profile waveform to select the target time windows, making automated extraction and large-scale automatic regression difficult. Summary of the Invention

[0006] In view of this, the present invention provides a chip power consumption evaluation method, device, equipment, storage medium and program product to solve the problem of low efficiency and accuracy of chip power consumption analysis caused by the fact that the time window selection in traditional power consumption analysis relies on manual selection and the selection accuracy is not high.

[0007] In a first aspect, the present invention provides a method for evaluating chip power consumption, the method comprising:

[0008] Obtain the RTL code and standard cell library information of the chip to be tested;

[0009] Based on the RTL code of the chip under test and the standard cell library information, perform RTL dimension power consumption profile simulation to obtain power consumption profile data;

[0010] Based on the power consumption profile data, multiple candidate time windows are generated;

[0011] Performing waveform simulation on the chip under test based on multiple candidate time windows to obtain gate-level waveforms corresponding to the multiple candidate time windows;

[0012] Perform gate-level power consumption calculation based on gate-level waveforms to obtain multiple power consumption calculation results;

[0013] Based on preset conditions and multiple power consumption calculation results, a target power consumption result is generated.

[0014] The chip power consumption evaluation method provided by the embodiment of the present invention generates power consumption profile data based on the physical information obtained by pre-synthesis of the RTL code and standard cell library information of the chip to be tested, combined with the RTL pre-simulation waveform, to select candidate windows. The method realizes fully automatic time window search and configuration, performs namemapping-based post-simulation based on the candidate time windows, and then performs gate-level power consumption calculation. Finally, the target power consumption result that meets the preset conditions is selected, which greatly reduces the possibility of manual intervention and errors, and improves the accuracy and efficiency of power consumption analysis.

[0015] In an optional embodiment, power consumption profile simulation is performed based on the RTL code and standard cell library information of the chip to be tested to obtain power consumption profile data, including:

[0016] Input the RTL code and standard cell library information of the chip to be tested into the preset synthesis tool to obtain preliminary synthesis results;

[0017] Based on the preliminary synthesis results, preliminary layout and routing results are obtained;

[0018] Perform power consumption profile simulation based on preliminary layout and routing results to obtain power consumption profile data.

[0019] The chip power consumption evaluation method provided by the embodiment of the present invention implements a fully automated process from RTL code to power consumption profile data, reducing the need for manual intervention. Automated processing not only improves work efficiency but also reduces the risk of human error, making the entire power consumption evaluation process more reliable and stable. Furthermore, power consumption profile data forms the basis for subsequent generation of candidate time windows and gate-level power consumption calculations. Therefore, accurate power consumption profile data also ensures the rationality of candidate time window selection.

[0020] In an optional implementation, multiple candidate time windows are generated based on the power consumption profile data, including:

[0021] The power consumption profile data is divided into sub-time windows according to the specified time interval;

[0022] Among the sub-time windows, several sub-time windows with the largest average values ​​of the power consumption profile data are determined as candidate time windows.

[0023] The chip power consumption evaluation method provided by the embodiment of the present invention can adjust the specified time interval and the number of candidate windows according to different design requirements and constraints. By selecting the sub-time window with the highest average power consumption as the candidate window, it can focus on the time period with the highest overall power consumption, thereby improving the efficiency of power consumption analysis and making subsequent power consumption analysis more targeted. At the same time, the automated selection of candidate time windows reduces errors caused by manual intervention and subjective judgment, helping to ensure the accuracy and reliability of power consumption analysis results.

[0024] In an optional implementation, based on a preset condition and according to a plurality of power consumption calculation results, generating a target power consumption result includes:

[0025] The maximum power consumption among the multiple power consumption calculation results is selected as the target power consumption result.

[0026] The chip power consumption evaluation method provided in the embodiment of the present invention should, in certain application scenarios, select the maximum power consumption as the target power consumption result to ensure that the chip can still meet the power consumption requirements under extreme conditions, so as to ensure the reliability and stability of the chip.

[0027] In an optional implementation, multiple candidate time windows are generated based on the power consumption profile data, including:

[0028] The power consumption profile data is divided into sub-time windows according to the specified time interval;

[0029] In each sub-time window, a sub-time window is selected as a candidate time window at every preset time length.

[0030] The chip power consumption evaluation method provided by the present invention ensures a relatively even distribution of candidate windows over time by selecting sub-time windows at preset intervals. This helps comprehensively cover the entire power consumption profile data and avoids missing periods of high power consumption. Furthermore, by adjusting the specified time interval and the preset time interval according to actual needs, the number and distribution of candidate windows can be flexibly controlled.

[0031] In an optional implementation, based on a preset condition and according to a plurality of power consumption calculation results, generating a target power consumption result includes:

[0032] The average power consumption of the multiple power consumption calculation results is used as the target power consumption result.

[0033] The chip power consumption evaluation method provided by an embodiment of the present invention calculates the average value of multiple power consumption calculation results to obtain a representative power consumption indicator. This average value can reflect the average power consumption level of the chip in different time windows or operating states. Because, in some cases, the power consumption calculation results may contain some extreme values, these extreme values ​​may be caused by specific workloads, operating modes, or environmental conditions. By calculating the average value, the impact of these extreme values ​​on the overall power consumption evaluation can be reduced, making the evaluation results more stable and reliable.

[0034] In a second aspect, the present invention provides a device for evaluating chip power consumption, the device comprising:

[0035] The acquisition module is used to obtain the RTL code and standard cell library information of the chip to be tested;

[0036] The simulation module is used to perform RTL-dimensional power consumption profile simulation based on the RTL code of the chip to be tested and the standard cell library information to obtain power consumption profile data;

[0037] A window selection module is used to generate multiple candidate time windows based on power consumption profile data;

[0038] A waveform generation module is used to perform waveform simulation on the chip under test based on multiple candidate time windows to obtain gate-level waveforms corresponding to the multiple candidate time windows;

[0039] A calculation module, used to perform gate-level power consumption calculation based on gate-level waveforms to obtain multiple power consumption calculation results;

[0040] The result generation module is used to generate a target power consumption result based on a plurality of power consumption calculation results based on preset conditions.

[0041] In a third aspect, the present invention provides a computer device comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the chip power consumption evaluation method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0042] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the chip power consumption evaluation method of the first aspect or any corresponding embodiment thereof.

[0043] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute the chip power consumption evaluation method of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 is a flow chart of a method for evaluating chip power consumption according to an embodiment of the present invention;

[0046] Figure 2 is a flow chart of a method for evaluating chip power consumption according to an embodiment of the present invention;

[0047] Figure 3 is a flow chart of another chip power consumption evaluation method provided by an embodiment of the present invention;

[0048] Figure 4 is a flow chart of another chip power consumption evaluation method according to an embodiment of the present invention;

[0049] Figure 5 is a flow chart of another chip power consumption evaluation method according to an embodiment of the present invention;

[0050] Figure 6 is a structural block diagram of a device for evaluating chip power consumption according to an embodiment of the present invention;

[0051] Figure 7 Schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present invention.

[0053] With advancements in manufacturing and packaging technology, the integration and power density of integrated circuits have increased significantly, making power consumption a critical design factor. Detailed power consumption analysis at each stage, clarifying the total amount and distribution, identifying areas where power consumption exceeds standards, and developing optimization strategies are crucial to achieving the ultimate power consumption target for chips.

[0054] Here we first explain the more common power consumption analysis methods.

[0055] On the one hand, power consumption analysis can be divided into three stages according to the development stage of the chip: front-end RTL level, mid-end synthesis, and back-end PR. According to the presence or absence of an identification file that reflects the signal flip behavior, it is further divided into two types: vector-based (with waveform) and vector-less (without waveform). Since vector-less power consumption analysis cannot guarantee accuracy, it is usually only used as a rough estimation method when there is no waveform file. However, vector-based power consumption analysis based on the back-end PR netlist is often used as a standard for power consumption analysis and sign-off due to its high accuracy. The details are shown in Table 1:

[0056] Table 1: Comparison of input files and accuracy characteristics required for each stage

[0057]

[0058] Among them, sdc stands for Synopsys Design Constraints file; liberty is a file format used to describe physical unit timing and power information, typically with a .lib file extension; spef (Standard Parasitic Exchange Format) is a standard exchange format used to describe parasitic parameters in integrated circuit design; PR netlist is a netlist file generated during the place and route (PR) phase; and synthesized netlist is the output of the synthesis step in the design flow. Although vector-based power analysis based on the back-end PR netlist offers high accuracy, obtaining post-simulation waveforms based on the PR netlist is usually performed in the middle or late stages of chip development. Furthermore, post-simulation waveforms are long to simulate and difficult to debug, often taking more than several weeks. Therefore, some power analysis methods use correlation database extraction (CRDB) technology to record the modifications to relevant registers during the RTL synthesis process. Through name mapping and waveform propagation, these RTL waveforms can be mapped to post-simulation waveforms. This technology can greatly shorten the time to obtain the post-simulation waveform, achieving an acceleration of 10 to 100 times or more, while the power consumption analysis accuracy and the power consumption error based on the post-simulation waveform can be controlled within 5%.

[0059] On the other hand, depending on the purpose of power consumption analysis, power consumption analysis scenarios can be divided into the following categories:

[0060] Maximum power consumption: refers to the power consumption of the chip when the business volume is the largest and the activities are the most frequent. It is an important reference for the chip's power network design and packaging design.

[0061] Average power consumption: The long-term average power consumption of the chip, which is an important reference for the selection of batteries for external power supply of the chip and the usage time.

[0062] Idle power consumption: The power consumption of the chip when it is not in use. It is an important reference for the chip's power saving design and standby time.

[0063] Scenario selection is reflected in the time window or toggle rate setting of the power analysis input waveform file. The choice of time window has a significant impact on the final power analysis value.

[0064] Currently, commonly used time window selection methods include waveform analysis, toggle rate statistics, and power profiling selection. Waveform analysis requires designers to understand the design to specify the time window for power consumption scenarios. However, due to design complexity and insufficient understanding of physical information (such as the design's RLC and power model), the window defined by the maximum operating mode often deviates significantly from the window with maximum power consumption. EDA tools generally provide statistics on signal toggle rates in waveform files, allowing designers to specify power consumption scenario waveforms based on toggle rate statistics. However, this method significantly impacts the accuracy of power analysis due to the lack of corresponding netlist physical and timing information. Power profiling selection, while performing simple cell mapping and clock tree and buffer tree reconstruction, still exhibits significant discrepancies compared to the power profile derived from simulation on the actual back-end netlist. Most methods also fail to consider the fault tolerance of the time window derived from RTL.

[0065] It can be seen that the existing analysis methods all have the defects of difficulty in selecting the time window and low selection accuracy due to reliance on manual selection.

[0066] An embodiment of the present invention provides a chip power consumption evaluation method. By obtaining the RTL code of the chip to be tested and the standard cell library information for pre-synthesis, the physical information obtained generates power consumption profile data to select candidate windows, realizes fully automatic time window search and configuration, and performs gate-level power consumption calculation based on the selection of candidate time windows, and finally selects the target power consumption result that meets the preset conditions.

[0067] According to an embodiment of the present invention, an embodiment of a method for evaluating chip power consumption is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0068] In this embodiment, a chip power consumption evaluation method is provided, which can be used in mobile terminals such as mobile phones and tablet computers. Figure 1 FIG. 1 is a flow chart of a method for evaluating chip power consumption according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0069] Step S101: Obtain the RTL code and standard cell library information of the chip to be tested.

[0070] Specifically, RTL is a level of abstraction in hardware description language (HDL) that describes the data transfer and logical operations between registers in digital circuits. RTL code is a crucial stage in the chip design process, situated between the behavioral and gate levels, and provides the foundation for subsequent circuit synthesis. Typically, RTL code is provided by chip designers or retrieved from existing design libraries. The code files are typically source code files written in Verilog or VHDL.

[0071] A standard cell library is a set of predefined, verified, and reusable logic gates and storage elements, such as AND gates, OR gates, and flip-flops. The standard cell library information records the power consumption information of each cell.

[0072] Step S102 : performing RTL dimension power consumption profile simulation based on the RTL code and standard cell library information of the chip to be tested to obtain power consumption profile data.

[0073] Specifically, the RTL code describes the chip's logical functions, while the standard cell library provides the physical cells required to build these logical functions, along with their power consumption, area, delay, and other characteristics. These are then fed into a pre-defined synthesis tool, which converts the RTL code into a gate-level netlist, taking into account physical information such as power consumption.

[0074] Furthermore, the synthesis tool is used to combine the RTL code with the standard cell library information to perform a pre-synthesis step to generate a preliminary circuit layout. Although the layout has not been optimized in detail, it is sufficient for a preliminary evaluation of the power profile.

[0075] Furthermore, the power consumption model is run through a simulation tool to simulate the chip's power consumption behavior in different operating modes. The simulation process generates a series of time series data that reflects the changes in chip power consumption over time. The power consumption profile data is extracted from the simulation results to form text data. This text data includes power consumption values ​​at each time point, as well as possible peak and average power consumption information.

[0076] In an optional implementation, the above step S102 includes:

[0077] Step a1: input the RTL code and standard cell library information of the chip to be tested into a preset synthesis tool to obtain preliminary synthesis results;

[0078] Step a2, obtaining preliminary layout and routing results based on the preliminary synthesis results;

[0079] Step a3: Perform power consumption profile simulation based on the preliminary layout and routing results to obtain power consumption profile data.

[0080] Specifically, this process requires the following steps. First, the RTL code and standard cell library information of the chip to be tested are input into the preset synthesis tool for synthesis to convert the RTL code into a gate-level netlist. Then, a special clock tree construction tool is used to generate a clock tree based on the synthesis results and the target clock frequency. In addition, appropriate buffers are inserted into the signal path to balance the signal propagation delay and improve circuit performance. Based on the synthesis results, clock tree and buffer tree, logic gates, triggers and other components are placed on the chip. Then, the various components are connected to form a preliminary layout and routing result. Finally, the above preliminary layout and routing results and the RTL pre-simulation waveform are imported into the power consumption simulation tool to obtain power consumption profile data.

[0081] Optionally, the preset synthesis tool may be a mainstream RTL power analysis tool such as Power Artist, Power Pro, Spyglass Power, or a combination of a synthesis tool such as Design compiler, Genus, Joules, and a power analysis tool.

[0082] Step S103: generating a plurality of candidate time windows based on the power consumption profile data.

[0083] Specifically, the power consumption profile data is analyzed in detail. The power consumption profile data usually includes a series of time points and the power consumption values ​​at the corresponding time points, reflecting the power consumption changes of the chip in different time periods. The power consumption profile data is analyzed through a preset script file to identify significant feature points of power consumption changes, such as power consumption peaks.

[0084] Furthermore, based on the characteristics of the power consumption profile data, an appropriate time window division strategy is selected. Based on multiple factors such as power consumption peak value, power consumption threshold, and time interval, the time window division parameters, such as time window length, overlap, and starting point, are determined to generate multiple candidate time windows. Each time window covers a specific period of time in the power consumption profile data.

[0085] Step S104 , performing waveform simulation on the chip to be tested based on the multiple candidate time windows to obtain gate-level waveforms corresponding to the multiple candidate time windows.

[0086] Specifically, using a pre-defined name mapping tool or script, name mapping and waveform propagation are performed to map the RTL waveform into a post-simulation waveform to obtain a gate-level waveform. Name mapping is a technique that maps signal names in a high-level design to signal names in the underlying implementation during simulation.

[0087] The steps of this process are as follows: First, the start and end times of the simulation are set based on multiple candidate time windows. Then, the gate-level netlist containing the simulation content required within the current candidate time window is loaded into the simulator, the gate-level netlist is simulated, and the previously established name mapping relationship is used to track and record signal changes. Finally, the gate-level waveform data within the current candidate time window is captured and recorded.

[0088] Step S105 , performing gate-level power consumption calculation based on the gate-level waveform to obtain multiple power consumption calculation results.

[0089] Specifically, it is necessary to obtain the PR netlist after layout and routing from the back-end design tool, select a suitable power consumption analysis tool, read the PR netlist and standard cell library information and the gate-level post-simulation waveform obtained in step S104 into the power consumption analysis tool for power consumption analysis, and obtain multiple power consumption calculation results.

[0090] Optionally, the power consumption analysis tool used in the embodiment of the present application may be PrimeTime PX, or a commonly used gate-level power consumption tool such as Voltus.

[0091] Step S106 : generating a target power consumption result based on a plurality of power consumption calculation results based on preset conditions.

[0092] The preset conditions are power consumption determination rules pre-set by the developer. For example, when the developer needs to measure the maximum power consumption level of the chip under test, the developer can select the largest power consumption calculation result from multiple power consumption calculation results as the target power consumption result; or when the developer needs to measure the average power consumption level of the chip under test, the developer can calculate the average value based on multiple power consumption calculation results to generate the target power consumption result.

[0093] In summary, if Figure 2As shown, the present application obtains RTL code and standard cell library information, synthesizes the RTL code, completes cell mapping and simple routing, and this process is equivalent to weighting the toggle rate with physical information. Unlike conventional power profiling methods, which perform trial calculations on the RTL or synthesis level to provide a time window, this process may still have errors compared to the power waveform calculation on the actual back-end PR netlist. Therefore, the present invention performs power profile simulation, obtains power profile text data, selects multiple candidate time windows based on a preset script file, and maps the RTL waveform into a post-simulation waveform based on name mapping and waveform propagation to obtain a gate-level waveform. Combined with the back-end PR netlist, power analysis corresponding to each candidate time window is performed to obtain multiple sets of power consumption calculation results corresponding to each candidate time window. Finally, the result that best meets the expectations is selected according to preset conditions as the target power consumption result, reducing the error caused by RTL power profiling positioning time window. The present invention performs power profile simulation to obtain power profile text data. It is a method based on outputting power profile text and supports automatic search and comparison of power consumption values ​​in each time period to find the time window that meets the expected time window. This process does not rely on manual labor and is executed automatically, which facilitates process automation and automatic regression.

[0094] Figure 3 FIG. 1 is a flow chart of another chip power consumption evaluation method provided by an embodiment of the present invention. Figure 3 As shown in Figure 1, this method can be used to evaluate the maximum power consumption level that a chip may reach under given conditions. The process includes the following steps:

[0095] Step S301: Obtain the RTL code and standard cell library information of the chip to be tested.

[0096] Step S302 : Based on the RTL code and standard cell library information of the chip to be tested, power consumption profile simulation is performed in the RTL dimension to obtain power consumption profile data.

[0097] Step S303 : Segment the power consumption profile data according to a specified time interval to obtain sub-time windows.

[0098] Optionally, the specified time interval may be determined according to the time length of the power consumption profile data.

[0099] Alternatively, the specified time interval can be preset by the developer, that is, the power consumption profile data can be divided into various sub-time windows using the preset time interval, and each sub-time window can represent the power consumption of the chip in a certain time period.

[0100] Step S304 : Determine, among the sub-time windows, several sub-time windows with the largest average values ​​of the power consumption profile data as candidate time windows.

[0101] That is, in the embodiment of the present application, it is necessary to determine a suitable time interval. The time interval should be as small as possible to capture subtle changes in power consumption, but not too small to avoid generating too many sub-time windows and increasing the amount of calculation. Then, the power consumption profile data is evenly divided according to this time interval, and each segment of data corresponds to a sub-time window. In this way, the original power consumption profile data is divided into multiple continuous sub-time windows with a fixed time length. Then, for each sub-time window, the average value or total power consumption of its power consumption profile data is calculated. Finally, all sub-time windows are sorted from large to small according to the average power consumption or total power consumption, and a number of sub-time windows are selected from the sorted sub-time windows according to a preset number or ratio as candidate time windows.

[0102] Step S305 , performing waveform simulation on the chip to be tested based on the candidate time windows to obtain gate-level waveforms corresponding to the multiple candidate time windows.

[0103] Step S306 , performing gate-level power consumption calculation based on the gate-level waveform to obtain multiple power consumption calculation results.

[0104] Step S307 : selecting the maximum power consumption among the multiple power consumption calculation results as the target power consumption result.

[0105] In summary, the chip power consumption evaluation method provided by the embodiment of the present invention realizes a fully automated process from RTL code to power consumption profile data, reducing the links of manual intervention. In some cases, it makes sense to select the maximum power consumption as the target power consumption result, such as evaluating the power consumption performance of the chip under the worst case scenario. Specifically, this step needs to first complete the gate-level power consumption calculation of multiple candidate time windows and obtain the corresponding power consumption calculation result set. Then, all the power consumption calculation results in this set are traversed, compared, and the maximum value is found. Finally, the maximum power consumption found is determined as the target power consumption result. This value represents the maximum power consumption level that the chip under test may reach under given conditions according to the current evaluation method.

[0106] In an embodiment of the present invention, the candidate time window selected according to the power consumption profile data corresponds to a time period in which the chip has higher power consumption. Gate-level power consumption calculation is used in this candidate time window, which improves the accuracy of calculating the maximum power consumption level that the chip under test can achieve under given conditions. Determining the maximum power consumption of the chip is of great reference significance for the power supply network design and packaging design of the chip.

[0107] The chip power consumption assessment method provided by the embodiments of the present invention not only improves work efficiency but also reduces the risk of human error, making the entire power consumption assessment process more reliable and stable. Furthermore, power consumption profile data is the basis for the subsequent generation of candidate time windows and gate-level power consumption calculations. Therefore, accurate power consumption profile data also ensures the rationality of candidate time window selection.

[0108] Figure 4 This is a flow chart of another chip power consumption evaluation method provided by an embodiment of the present invention, such as Figure 4 As shown in Figure 1, this method can be used to evaluate the average power consumption level of a chip under given conditions. The process includes the following steps:

[0109] Step S401, obtaining the RTL code and standard cell library information of the chip to be tested;

[0110] Step S402 , performing RTL dimension power consumption profile simulation based on the RTL code and standard cell library information of the chip to be tested to obtain power consumption profile data;

[0111] Step S403, dividing the power consumption profile data into designated time intervals to obtain sub-time windows;

[0112] Step S404: In each sub-time window, a sub-time window of a preset time length is selected as a candidate time window;

[0113] Step S405 , performing waveform simulation on the chip to be tested based on the candidate time windows to obtain gate-level waveforms corresponding to the multiple candidate time windows.

[0114] Step S406 , performing gate-level power consumption calculation based on the gate-level waveform to obtain multiple power consumption calculation results.

[0115] Step S407 : taking the average power consumption of the multiple power consumption calculation results as the target power consumption result.

[0116] In summary, the chip power consumption evaluation method provided by the embodiment of the present invention obtains RTL code and standard cell library information, synthesizes the RTL code, and completes cell mapping and simple wiring. This process is equivalent to weighting the physical information of togglerate. Different from the conventional Power Profiling method, the power consumption waveform is calculated at the RTL or synthesis level to provide a time window. This process may still have errors compared with the power consumption waveform calculation on the actual back-end PR netlist. Therefore, the present invention performs power consumption profile simulation. After obtaining the power consumption profile text data, according to the preset script file, first, a suitable time interval is determined. The time interval should be as small as possible to capture subtle changes in power consumption, but not too small to avoid generating too many sub-time windows and increasing the amount of calculation. Then, the power consumption profile data is evenly divided according to the time interval. Each divided data segment represents a sub-time window, which contains the power consumption information within the time period. Then, within all sub-time windows, a preset time length is determined. This length can be an integer multiple of the time interval. This length is used to select candidate time windows from the sub-time windows. For example, starting from the first sub-time window, a sub-time window is selected as a candidate time window after each preset time length, skipping a certain number of sub-time windows until all sub-time windows have been traversed or the preset number of candidate time windows has been reached. Based on name mapping and waveform propagation, the RTL waveform is mapped into a post-simulation waveform to obtain a gate-level waveform. Combined with the back-end PR netlist, power consumption analysis corresponding to each candidate time window is performed to obtain multiple sets of power consumption calculation results for each candidate time window.

[0117] While selecting the maximum power consumption as the target power consumption result makes sense in some cases, it may not always reflect the average or typical power consumption of the chip in actual applications. Therefore, the average power consumption can be used as the target power consumption result to provide a general assessment of the chip's overall power consumption performance. In addition, determining the chip's long-term average power consumption is also important for selecting batteries for external chip power supply and its usage time.

[0118] Specifically, this step first requires calculating gate-level power consumption for multiple candidate time windows and obtaining a corresponding set of power consumption calculation results. Next, all power consumption calculation results in this set are summed and divided by the number of candidate time windows to obtain the average power consumption. This average reflects the average level of chip power consumption within the multiple candidate time windows. Finally, this calculated average power consumption is determined as the target power consumption result.

[0119] Figure 5 This is a flow chart of another chip power consumption evaluation method provided by an embodiment of the present invention, such as Figure 5 As shown in FIG, this method can be used to evaluate the idle power consumption level of a chip under given conditions. The process includes the following steps:

[0120] Step S501, obtaining the RTL code and standard cell library information of the chip to be tested;

[0121] Step S502 , performing RTL dimension power consumption profile simulation based on the RTL code and standard cell library information of the chip to be tested to obtain power consumption profile data;

[0122] Step S503 , dividing the power consumption profile data into designated time intervals to obtain sub-time windows;

[0123] Step S504 : Determine, among the sub-time windows, several sub-time windows with the smallest average values ​​of the power consumption profile data as candidate time windows.

[0124] Step S505 , performing waveform simulation on the chip to be tested based on the multiple candidate time windows to obtain gate-level waveforms corresponding to the multiple candidate time windows.

[0125] Step S506 , performing gate-level power consumption calculation based on the gate-level waveform to obtain multiple power consumption calculation results.

[0126] Step S507 : selecting the minimum power consumption value among the multiple power consumption calculation results as the target power consumption result.

[0127] The chip power consumption evaluation method provided by the embodiment of the present invention selects the sub-time window with the smallest average power consumption as the candidate time window. This method can more accurately locate the time period when the chip power consumption is relatively low to determine the idle power consumption of the chip. The idle power consumption is used to characterize the power consumption of the chip when there is no business. By accurately measuring the idle power consumption of the chip, it has important reference significance for the chip's power-saving design, standby time, etc.

[0128] In this embodiment, a device for evaluating chip power consumption is also provided, which is used to implement the above-mentioned embodiments and preferred implementation methods. The details that have been described will not be repeated here. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

[0129] This embodiment provides a device for evaluating chip power consumption, such as Figure 6 Shown, including:

[0130] The acquisition module 601 is used to acquire the RTL code and standard cell library information of the chip to be tested.

[0131] The simulation module 602 is used to perform RTL dimension power consumption profile simulation based on the RTL code and standard cell library information of the chip to be tested to obtain power consumption profile data.

[0132] The window selection module 603 is configured to generate a plurality of candidate time windows based on the power consumption profile data.

[0133] The waveform generation module 604 is configured to perform waveform simulation on the chip under test based on multiple candidate time windows to obtain gate-level waveforms corresponding to the multiple candidate time windows.

[0134] The calculation module 605 is used to perform gate-level power consumption calculation based on the gate-level waveform to obtain multiple power consumption calculation results.

[0135] The result generation module 606 is configured to generate a target power consumption result based on a plurality of power consumption calculation results and a preset condition.

[0136] In some optional implementations, the simulation module 602 includes:

[0137] The preliminary layout submodule is used to input the RTL code and standard cell library information of the chip to be tested into the preset synthesis tool to obtain preliminary layout results.

[0138] The data acquisition submodule is used to perform power consumption profile simulation based on the preliminary layout results to obtain power consumption profile data.

[0139] In some optional implementations, the window selection module 603 includes:

[0140] The segmentation submodule is used to segment the power consumption profile data according to the specified time interval to obtain each sub-time window.

[0141] The average value screening submodule is used to determine several sub-time windows with the largest average values ​​of power consumption profile data among the sub-time windows as candidate time windows.

[0142] In some optional implementations, the result generation module 606 includes:

[0143] The maximum value selection submodule is used to select the maximum power consumption among multiple power consumption calculation results as the target power consumption result.

[0144] In some optional implementations, the window selection module 603 includes:

[0145] The sub-window obtaining sub-module is used to divide the power consumption profile data into specified time intervals to obtain various sub-time windows.

[0146] The time length screening submodule is used to select a sub-time window as a candidate time window at every preset time length in each sub-time window.

[0147] In some optional implementations, the result generation module 606 includes:

[0148] An average value submodule is selected to use the average power consumption of multiple power consumption calculation results as the target power consumption result.

[0149] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0150] The chip power consumption evaluation device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0151] The embodiment of the present invention also provides a computer device having the above Figure 6 The chip power consumption is shown as an evaluation device.

[0152] See also Figure 7 , Figure 7 is a structural diagram of a computer device provided by an optional embodiment of the present invention, such as Figure 7 As shown, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components utilize different buses to communicate with each other and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in the memory or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Equally, multiple computer devices can be connected, and each device provides part of the necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0153] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0154] The memory 20 stores instructions that can be executed by at least one processor 10, so as to enable at least one processor 10 to execute the method shown in the above embodiment.

[0155] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0156] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0157] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 7 The bus connection is taken as an example.

[0158] The input device 30 can receive input digital or character information and generate key signal input related to user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touch pad, an indicator stick, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), and a tactile feedback device (e.g., a vibration motor). The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display, and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0159] The embodiment of the present invention also provides a computer-readable storage medium. The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0160] A portion of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the form in which the computer program instruction exists in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc. Accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium that can be accessed by the computer.

[0161] Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention. Such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A chip power consumption evaluation method, characterized in that: The method comprises: Obtain the RTL code and standard cell library information of the chip to be tested; Based on the RTL code and standard cell library information of the chip to be tested, a power consumption profile simulation in the RTL dimension is performed to obtain power consumption profile data; the power consumption profile data includes a series of time points and power consumption values ​​at corresponding time points; generating a plurality of candidate time windows based on the power consumption profile data; Performing waveform simulation on the chip under test based on the multiple candidate time windows to obtain gate-level waveforms corresponding to the multiple candidate time windows; Perform gate-level power consumption calculation based on the gate-level waveform to obtain multiple power consumption calculation results; Based on preset conditions, a target power consumption result is generated according to the multiple power consumption calculation results.

2. The method according to claim 1, characterized in that The power consumption profile simulation is performed based on the RTL code and standard cell library information of the chip to be tested to obtain power consumption profile data, including: Inputting the RTL code and standard cell library information of the chip to be tested into a preset synthesis tool to obtain a preliminary synthesis result; Based on the preliminary synthesis result, a preliminary layout and routing result is obtained; Power consumption profile simulation is performed based on the preliminary layout and routing results to obtain power consumption profile data.

3. The method according to claim 1 or 2, characterized in that The generating a plurality of candidate time windows based on the power consumption profile data includes: Segmenting the power consumption profile data according to specified time intervals to obtain sub-time windows; Among the sub-time windows, several sub-time windows with the largest average values ​​of the power consumption profile data are determined as the candidate time windows.

4. The method according to claim 3, characterized in that The generating a target power consumption result based on the preset conditions and the plurality of power consumption calculation results includes: The maximum power consumption value among the multiple power consumption calculation results is selected as the target power consumption result.

5. The method according to claim 1 or 2, characterized in that The generating a plurality of candidate time windows based on the power consumption profile data includes: Segmenting the power consumption profile data according to specified time intervals to obtain sub-time windows; In each of the sub-time windows, a sub-time window is selected as the candidate time window at every preset time length.

6. The method according to claim 5, characterized in that The generating a target power consumption result based on the preset conditions and the plurality of power consumption calculation results includes: The average power consumption value of the plurality of power consumption calculation results is used as the target power consumption result.

7. A chip power consumption evaluation device, characterized in that: The device comprises: The acquisition module is used to obtain the RTL code and standard cell library information of the chip to be tested; A simulation module is used to perform RTL dimension power consumption profile simulation based on the RTL code and standard cell library information of the chip to be tested to obtain power consumption profile data; the power consumption profile data includes a series of time points and power consumption values ​​at corresponding time points; A window selection module is used to generate a plurality of candidate time windows based on the power consumption profile data; A waveform generation module is used to perform waveform simulation on the chip under test based on the multiple candidate time windows to obtain gate-level waveforms corresponding to the multiple candidate time windows; A calculation module, configured to perform gate-level power consumption calculation based on the gate-level waveform to obtain a plurality of power consumption calculation results; The result generating module is configured to generate a target power consumption result based on a preset condition and the plurality of power consumption calculation results.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the chip power consumption evaluation method according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the chip power consumption evaluation method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the chip power consumption estimation method according to any one of claims 1 to 6.

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