A VCSEL chip and a VCSEL laser

Abstract

The application relates to the technical field of semiconductor lasers, in particular to a VCSEL chip and a VCSEL laser. The VCSEL chip for a semiconductor laser comprises an N electrode, an N-type DBR part, an active part, a P-type DBR part and a P electrode, and the N electrode, the N-type DBR part, the active part, the P-type DBR part and the P electrode are sequentially stacked from bottom to top; wherein the P-type DBR part is arranged as a multilayer structure which is sequentially stacked, the lateral area of each layer of the multilayer structure gradually decreases from bottom to top; and the distance between the upper end surface edge of the DBR layer in the lower position and the lower end surface edge of the DBR layer in the upper position is arranged. According to the embodiment, the surface of the P-type DBR part of the VCSEL is arranged as a stepped structure, so that the equivalent resistance of the whole VCSEL can be effectively reduced, the heat dissipation is improved, and the thermal stability and high-speed modulation performance of the chip are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor laser technology, specifically to a VCSEL chip and a VCSEL laser. Background Technology

[0002] VCSEL is a semiconductor laser structure in which an optical resonant cavity is formed in a direction perpendicular to the semiconductor epitaxial wafer, and the emitted laser beam is perpendicular to the substrate surface.

[0003] Vertical cavity surface-emitting lasers often use GaAs (gallium arsenide) as a substrate. However, it is well known that GaAs has poor heat dissipation performance and its refractive index changes with increasing temperature. Therefore, operating the chip at high temperatures will lead to a decrease in device performance.

[0004] In the process of developing this invention, the inventors discovered that high-speed modulated VCSELs are currently a hot topic in the industry. While 25GHz bandwidth VCSELs are already in mass production, further increasing the modulation speed of VCSELs faces many challenges. To further improve the modulation bandwidth of VCSELs, two main aspects need to be considered: firstly, the internal resistance of these chips needs to be further reduced, as conventional designs struggle to significantly lower the internal resistance and thus increase the modulation bandwidth; secondly, the heat dissipation performance of these devices needs to be further improved. However, current VCSEL chip structures cannot simultaneously and effectively address both excessive internal resistance and poor heat dissipation, thus hindering the development of high-speed modulated VCSELs. Summary of the Invention

[0005] In view of the above problems, the present invention is proposed to provide a VCSEL chip, a VCSEL chip semiconductor laser, and a control method for overcoming or at least partially solving the above problems.

[0006] In a first aspect, embodiments of the present invention provide a VCSEL chip for use in a semiconductor laser, comprising:

[0007] The N-electrode, the N-type DBR section, the active section, the P-type DBR section, and the P-electrode are arranged in a stacked manner from bottom to top.

[0008] The P-type DBR section is configured as a multi-layer structure stacked sequentially, and the lateral area of ​​each layer of the multi-layer structure gradually decreases from bottom to top;

[0009] Furthermore, the adjacent layers of the multilayer structure are configured such that the edge of the upper surface of the lower DBR layer is at a distance from the edge of the lower surface of the upper DBR layer.

[0010] Further, the distance control is 0.8-2um.

[0011] Further, the transverse cross-sectional shape of the P-type DBR part includes a circle, an ellipse or a rectangle.

[0012] Further, the number of layers of the P-type DBR part is 16-40 layers.

[0013] Further, the thickness of each layer of the P-type DBR part is controlled to be 1-1.5um.

[0014] Further, the P-type DBR part is made of material

[0015] Further, the N electrode is AuGeNi alloy plating material with a thickness of 500A; the P electrode is Ti / Au with a thickness of 500A / 3000A.

[0016] The second aspect further discloses a VCSEL laser, comprising the VCSEL chip.

[0017] The beneficial effects of the above technical solutions provided by the embodiments of the present application at least include:

[0018] The embodiment of the present application provides a VCSEL chip, by setting the surface of the P-type DBR part of the VCSEL into a stepped structure, and each step of the stepped structure corresponds to each layer in the P-type DBR part, thereby effectively improving the overall performance of the P-type DBR part. Thus, the overall equivalent resistance of the VCSEL can be effectively reduced, and the heat dissipation is also improved, thereby realizing the improvement of the thermal stability and high-speed modulation performance of the chip.

[0019] In order to obtain the surface of the P-type DBR part into a stepped structure, the embodiment is designed by designing the pattern structure on the mask, and the pattern is etched into the P-type DBR part by etching process, thereby obtaining the stepped structure.

[0020] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be achieved and obtained by the structure particularly pointed out in the written description and the accompanying drawings.

[0021] The technical solutions of the present application will be further described in detail below by means of the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the drawings needed to be used in the specific embodiments or prior art description will be briefly introduced. In all the drawings, similar elements or parts are generally identified by similar reference signs. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0023] Figure 1 is a structural schematic diagram of a conventional VCSEL chip;

[0024] Figure 2 is a schematic diagram of a VCSEL chip of the first embodiment of the present application;

[0025] Figure 3 is a schematic diagram of another view of the present application; Figure 2

[0026] Figure 4 is a D partial enlarged view of the present application; Figure 4

[0027] Figure 5 is a LIV curve diagram of a conventional VCSEL chip;

[0028] Figure 6 is a LIV curve diagram of a VCSEL chip of the present embodiment;

[0029] Figure 7 is a schematic diagram of a first mask of the first embodiment of the present application;

[0030] Figure 8 is an A partial enlarged view of the present application; Figure 7

[0031] Figure 9 is a schematic diagram of another view of the present application; Figure 7

[0032] Figure 10 is a B partial enlarged view of the present application; Figure 9

[0033] is a schematic diagram of a first mask of the second embodiment of the present application; Figure 11

[0034] Figure 12 is a C partial enlarged view of the present application; Figure 11

[0035] Figure 13 is a flowchart of a preparation method of a VCSEL chip of the present application.

[0036] Indicated in the drawings:

[0037] ​​​​​​10, P-type DBR section; 11, active section; 12, N-type DBR section; 13, substrate; 14, P-electrode;

[0038] 20, first mask; 21, pattern layer; 22, substrate; 210, convex structure; 211, boss. DETAILED DESCRIPTION

[0039] The embodiments of the technical solutions of the present application will be described in detail below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application, and therefore only serve as examples, and cannot limit the protection scope of the present application.

[0040] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in the present application should be understood as the usual meaning understood by the skilled person in the field to which the present application belongs.

[0041] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like are based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0042] In addition, the terms "first", "second", and the like are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0043] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0044] In the present application, unless specifically stated and qualified to the contrary, a first feature is "on" or "under" a second feature if the first and second features are in direct contact, or the first and second features are in indirect contact via an intermediate medium. Moreover, a first feature is "over", "above" and "on top of" a second feature if the first feature is directly above or obliquely above the second feature, or simply indicates that the first feature is horizontally higher than the second feature. A first feature is "under", "below" and "underneath" a second feature if the first feature is directly below or obliquely below the second feature, or simply indicates that the first feature is horizontally lower than the second feature.

[0045] In an embodiment, the VCSEL is a semiconductor laser structure in which an optical resonant cavity is formed in a direction perpendicular to a semiconductor epitaxial wafer, and a laser beam emitted is perpendicular to the surface of the substrate. It is widely used in consumer electronics, military, medical and other fields, such as 3D sensing, AR / VR, robots, laser radar, consumer electronics, intelligent manufacturing, Internet of Things, data centers and other fields. Specific applications include intelligent driving, video surveillance, laser radar, machine vision, gesture recognition, face recognition and other fields.

[0046] The DBR, as a mirror of the resonant cavity, is formed by alternating epitaxial growth of high and low refractive index media or semiconductor materials, and the optical thickness of each layer of material is 1 / 4 of the laser wavelength. Using the principles of thin film interference and reflection phase change, when light passes through a thin film, it will be reflected twice on the upper and lower surfaces. The thickness of the thin film will affect the optical path difference of the two reflections. If the thickness of the thin film is controlled to be an integer multiple of (1 / 4+N) wavelengths, the optical path difference of the two reflections is (1 / 2+2N), and the optical path difference corresponds to a phase change of 180°. Therefore, the two reflections on the upper and lower interfaces are eventually in phase, and the superposition is enhanced, that is, the overall reflectivity is increased. The high and low refractive index media or semiconductor materials are alternately epitaxially grown, and the light from the optical dense medium to the optical sparse medium will also undergo a phase change of 180° at the interface. Therefore, the light passes through each layer of DBR and increases the reflectivity by a certain amount. For the light exit surface DBR, a smaller reflectivity is obtained by appropriately reducing the number of layers to ensure that the laser is transmitted and emitted.

[0047] The current VCSEL chip can be divided into two parts in the whole process, epitaxial growth and chip process, and the epitaxial process is crucial. The performance of the VCSEL device is basically determined by the quality of the epitaxial structure. At present, most manufacturers generally use MOCVD to grow, and the total thickness is about 8-10um. The whole structure has more than 200 layers. Generally, each single layer is grown first, and then the quality, composition, carrier concentration and growth rate of the single layer are determined by various test equipment. The whole structure is further epitaxially grown. The change of each layer parameter, such as the number of DBR layers, doping concentration or the change of the heterostructure of the active region, will have a greater impact on the overall characteristics of the VCSEL.

[0048] Referring to the drawingsFigure 1 As shown, a typical VCSEL includes a substrate 13, a first reflecting portion, an active portion, a second reflecting portion, and an electrode.

[0049] The substrate 13 allows the growth of each layer constituting the VCSEL. The substrate 13 provides a space in which each layer can grow, and obtains a power source from an electrode to be arranged at the lower end of the substrate 13 and transmits it to the first reflecting portion. Accordingly, a laser (light) can be output from the active portion from the power source recognized to each reflecting portion. Among them, the substrate 13 can be implemented with GaAs, but is not necessarily limited thereto, and can be implemented with GaN, SiC, ZnC, Si, sapphire, or the like.

[0050] The first reflecting portion can be implemented as an n-type semiconductor layer coated with an n-type coating agent, and can be composed of any one of semiconductor materials including Al, AlGaAs, AlGaInP, and AlInP. The first reflecting portion can be composed of at least one n-type semiconductor layer, and can include a layer forming a distributed Bragg reflector or a "distributed Bragg reflector" (DBR). The first reflecting portion can be formed on a substrate by any one of Epitaxy, Chemical Vapor Deposition (CVD), Sputtering, Metal Organic Chemical Vapor Deposition (MOCVD), or Hydrogen Vapor Phase Epitaxy (HVPE) methods.

[0051] The active portion is a layer in which electrons generated in the first reflecting portion meet holes generated in the second reflecting portion and recombine, and light is generated by the recombination of the electrons and the holes. The active portion can include a Single Quantum Well (SQW) or a Multiple Quantum Well (MQW) structure having a plurality of quantum well layers. If the multiple quantum well structure is included, the cavity layer has a structure in which well layers (micro guide times) and barrier layers (micro guide times) having different energy bands are alternately stacked one or more times.

[0052] The well / barrier layer of the active portion can be composed of AlGaInP / AlGaInP, AlGaInP / AlInP, AlGaAs / AlGaAs, AlGaAs / GaAs, or AlGaAs / InGaAs, or the like.

[0053] An oxide film layer is formed on the top of the active portion.

[0054] The oxide film layer is formed by an oxidation process to form an oxide portion of a certain length, and the diameter of the opening is determined according to the length of the oxide portion. The oxide film layer is composed of aluminum (Al) with a higher concentration than the first and second reflective portions. The higher the aluminum concentration, the greater the oxidation rate. With the oxide film layer realized as a relatively high aluminum concentration than the positive reflective portion, selective oxidation can be performed when subsequent oxidation is performed. For example, the oxide film layer can be realized with 98% AlGaAs, and each reflective portion can be realized with 92% AlGaAs.

[0055] The second reflective portion can be composed of a semiconductor material coated by a p-type coating agent, or composed of any one of semiconductor materials containing Al, such as AlGaAs, AlGaInP, and AlInP, or composed of GaP. The second reflective portion can be composed of at least one layer, or can include layers formed by a DBR. The second reflective portion can be formed by any one of Epitaxy, Chemical Vapor Deposition (CVD), Sputtering, Metal Organic Chemical Vapor Deposition (MOCVD), or Hydride Vapor Phase Epitaxy (HVPE).

[0056] An electrode is formed on the second reflective portion to supply power to the second reflective portion.

[0057] The inventors of the present application continue to study how to effectively solve the problem that the VCSEL chip structure cannot simultaneously better solve the problems of excessive internal resistance and poor heat dissipation effect. The inventors' research at least includes: how to change the DBR layer number, the doping concentration, or the heterostructure of the active region, and change the internal resistance and heat dissipation effect of the overall VCSEL by changing the structure of the DBR layer. After a large number of repeated studies, the inventors propose the VCSEL chip and the laser of the present application.

[0058] Referring to the accompanying Figure 2 The VCSEL chip provided in the embodiments of the present application is used for a semiconductor laser, and includes:

[0059] An N electrode, an N-type DBR portion 12, an active portion 11, a P-type DBR portion 10, and a P electrode 14 are sequentially stacked from bottom to top.

[0060] The P-type DBR portion 10 is provided as a multi-layer structure that is sequentially stacked, and the lateral area of each layer of the multi-layer structure gradually decreases from bottom to top.

[0061] Further, the multi-layer structure is provided with a distance between the edges of the upper end surface of the lower DBR layer and the lower end surface of the upper DBR layer.

[0062] It can be understood that, in order to solve the problem of large internal resistance and poor heat dissipation of the current high-speed modulated VCSEL, the embodiment is that the cross section of the P-type DBR part 10 is set to gradually decrease from bottom to top, and the outer surface of the P-type DBR part 10 is set to a stepped structure. The stepped structure effectively increases the outer surface area of the P-type DBR part 10, thereby effectively solving the problem of poor heat dissipation. The stepped P-type DBR part 10 can effectively reduce the equivalent series resistance of the chip as a whole, that is, reduce the internal resistance of the VCSEL chip, thereby improving the thermal stability and high-speed modulation performance of the chip.

[0063] In the embodiment, the active part 11 is specifically a non-doped active region, and the active part 11 includes light-emitting quantum wells and barrier layers thereof. The N-type DBR part 12 and the P-type DBR part 10 are both composed of two different components of materials (such as Al0.1GaAs and Al0.9GaAs), and the two different components of materials are arranged alternately layer by layer. Because the two different components of materials are used, different refractive indexes are obtained.

[0064] Referring to FIGS. 1 to 3, Figure 3 and 4 As shown in the embodiments, the stepped structure can be considered as follows: the upper end face edge of the lower DBR layer is set to have a distance from the lower end face edge of the upper DBR layer. The stepped structure can also be considered as follows: the lower DBR layer protrudes a part from the upper DBR layer, thereby forming a staggered stepped structure.

[0065] At the same time, it can also be considered that the two adjacent layers from bottom to top are set as follows: a part of the upper end face of the lower DBR layer is exposed outside, that is, the lower DBR layer protrudes a part from the upper DBR layer arranged above the lower DBR layer, thereby setting the outer surface of the P-type DBR part 10 to a stepped structure.

[0066] Here, the lower position refers to the position of the lower layer of the two adjacent layers in the multilayer structure, and the upper position refers to the position of the upper layer of the two adjacent layers in the multilayer structure. For example, in an embodiment, two DBR layers are stacked together, and the position of the lower layer is called the lower position, and the position of the upper layer is called the upper position.

[0067] It can be understood that the VCSEL chip of the embodiment is basically the same as the existing VCSEL chip structure, and it can also be understood that the embodiment is an improvement based on the existing VCSEL chip. The difference between the VCSEL chip of the embodiment is that a step structure is arranged on the outer surface of the P-type DBR part 10 to solve the defects existing in the existing high-speed modulated VCSEL chip, effectively reduce the internal resistance of the VCSEL chip, and at the same time, the heat dissipation effect can be increased, and the thermal stability and high-speed modulation performance of the VCSEL chip can be effectively guaranteed.

[0068] Figure 5 is the LIV curve diagram of the traditional VCSEL chip; Figure 6 is the LIV curve diagram of the VCSEL chip of the embodiment. The LIV curve diagram here refers to the curve relationship diagram between the laser current (I), voltage (V) and light output power (P). Through the LIV curve diagram, the output power of the laser at different operating points can be understood, and then the performance can be evaluated.

[0069] wherein, Figure 5 The number of layers of the P-type DBR part 10 of the VCSEL laser in Figure 6 The number of layers of the P-type DBR part 10 of the VCSEL laser in

[0070] Through the relationship between the output voltage and the output current, it can be obtained that the VCSEL chip in Figure 5 The internal resistance R of the VCSEL chip in Figure 6 The internal resistance R of the VCSEL chip in

[0071] As described above, by arranging the outer surface of the P-type DBR part 10 as a step structure, the overall internal resistance of the VCSEL is reduced. After the internal resistance is reduced, the heat generated by the internal resistance is reduced, thereby reducing the heat to a certain extent.

[0072] Referring to Figure 4 It is shown that the embodiment further controls the distance L to be 0.8-2um. At the same time, the height H of the step protrusion can also be controlled, and the control height is 0.8-2um.

[0073] The difference between the cross sections of the two adjacent layers in the P-type DBR part 10 of the multi-layer structure is set appropriately, and the difference between the two adjacent layers is controlled effectively to reduce the internal resistance of the VCSL chip and increase the heat dissipation effect of the VCSL chip.

[0074] In some embodiments, the distance between the edge of the upper end surface of the lower layer and the edge of the lower surface of the upper layer in the two adjacent layers of the P-type DBR part 10 of the multi-layer structure is controlled to be 1 um; in other embodiments, the distance between the edge of the upper end surface of the lower layer and the edge of the lower surface of the upper layer in the two adjacent layers of the P-type DBR part 10 of the multi-layer structure is controlled to be 1.5 um; in still other embodiments, the distance between the edge of the upper end surface of the lower layer and the edge of the lower surface of the upper layer in the two adjacent layers of the P-type DBR part 10 of the multi-layer structure is controlled to be 2 um.

[0075] Referring to the accompanying Figure 2 The cross-sectional shape of the P-type DBR part 10 includes a circle, an ellipse, or a rectangle, according to the embodiments.

[0076] That is, the cross section of the P-type DBR part 10 can be etched into different shapes according to actual needs. In this example, the cross section of the P-type DBR part 10 is etched into a circle by the first mask 20, and can also be etched into other shapes such as an ellipse or a rectangle.

[0077] The number of layers of the P-type DBR part 10 is 16-40, according to the embodiments.

[0078] That is, the actual number of layers of the P-type DBR part 10 can be set according to actual needs. In actual use, in some embodiments, the actual number of layers of the P-type DBR part 10 is set to 32, i.e., 16 pairs of structures; in other embodiments, the actual number of layers of the P-type DBR part 10 is set to 16, i.e., 8 pairs of structures; and in still other embodiments, the actual number of layers of the P-type DBR part 10 is set to 40, i.e., 20 pairs of structures. Since the number of layers of the P-type DBR part 10 can also change the overall performance of the VCSEL, the actual number of layers needs to be set according to actual conditions.

[0079] The thickness H of each layer of the P-type DBR part 10 is controlled to be 1-1.5 um, according to the embodiments.

[0080] In some embodiments, the thickness of each layer of the P-type DBR section 10 is controlled to be 1.2 um, and when the P-type DBR section 10 is a 32-layer structure, the total thickness is 38.4 um; in other embodiments, the thickness of each layer of the P-type DBR section 10 is controlled to be 0.8 um, and when the P-type DBR section 10 is a 40-layer structure, the total thickness is 32 um; and in further embodiments, the thickness of each layer of the P-type DBR section 10 is controlled to be 1.6 um, and when the P-type DBR section 10 is a 16-layer structure, the total thickness is 25.6 um.

[0081] In further embodiments, the P-type DBR section 10 is made of Al0.1GaAs and Al0.9GaAs.

[0082] In embodiments, the P-type DBR section 10 is composed of two different components of materials (Al0.1GaAs and Al0.9GaAs), and the two different components of materials are arranged alternately layer by layer to obtain the P-type DBR section 10.

[0083] In further embodiments, the N electrode is an AuGeNi alloy plating material with a thickness of 500 Å, and the P electrode is a Ti / Au electrode with a thickness of 500 Å / 3000 Å.

[0084] Based on the same inventive concept, a VCSEL laser is also disclosed, comprising the VCSEL chip of any one of the above.

[0085] The specific examples and beneficial effects of the VCSEL laser in the embodiments can be referred to the description of the VCSEL chip above, and will not be repeated here.

[0086] Based on the same inventive concept, a method for preparing a VCSEL chip is also disclosed, comprising the following steps:

[0087] S001: preparing an epitaxial wafer, and obtaining a required epitaxial wafer through epitaxial growth technology.

[0088] In embodiments, when preparing the VCSEL chip, a complex multi-layer film structure is deposited on the substrate 13 through a metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) process.

[0089] The growth of the substrate 13 is a key step in the whole process, which directly determines the quality and performance of the device. The substrate 13 is usually gallium arsenide. In some embodiments, GaAs and AlAs are alternately grown on the substrate 13, and the alternately grown layers eventually form a Bragg reflector. Since GaAs and AlAs have significantly different refractive indices, but their lattice constants are basically the same, they can be alternately grown for many layers without dislocations, which is why a high-reflectivity mirror effect can be achieved. During the growth process, parameters such as growth rate, temperature and pressure need to be controlled to obtain high-quality epitaxial layers.

[0090] Epitaxial growth: The cut silicon wafer is placed in a high-temperature furnace, and semiconductor materials with specific energy level structures are grown on the epitaxial layer by vapor deposition, i.e. an epitaxial wafer is obtained.

[0091] In some embodiments, the epitaxial wafer needs to be cleaned before the next process, and the cleaning of the epitaxial wafer needs to be detected to prevent foreign matter from affecting other processes and causing defective products.

[0092] The specific steps include: sequentially cleaning the epitaxial wafer with acetone and isopropyl alcohol reagents for 5 minutes, then sequentially cleaning with deionized water, and finally drying. Then, the cleaned and dried epitaxial wafer is examined under a microscope to check for foreign matter, dust, contamination, color patterns, water stains, etc. to ensure the cleanliness of the epitaxial wafer and prevent it from affecting the next process step and reducing the occurrence of defective products.

[0093] S002: Preparation of a mask, a photoresist is made on the substrate to form a corresponding pattern, and a first mask and a second mask are obtained.

[0094] In some embodiments, the structure of the first mesa is different from that of the existing VCSEL chip, and the structure of the second mesa and the electrode is the same as that of the existing VCSEL chip, i.e. during lithography, the etching process of the first mesa is different from that of the existing VCSEL chip, while the etching process of the second mesa and the electrode is the same as that of the traditional VCSEL chip.

[0095] In order to obtain the stepped structure of the outer surface of the VCSEL chip, the first mask 20 is prepared in some embodiments, and the stepped structure can be etched on the epitaxial wafer through the first mask 20 during lithography. The other structures are the same as the traditional structures, so the mask required for lithography at other stages, such as the second mask, can be manufactured by referring to the existing mask manufacturing process. The manufacturing process steps of the first mask 20 are as follows:

[0096] Further, the first mask 20 is made by a two-photon polymerization 3D printing process, and the specific steps include:

[0097] On the substrate 22, a positive photoresist is printed as a soft mask by using a 3D printing process;

[0098] A plurality of uniform protruding structures 210 are printed above the soft mask, and a plurality of bosses 211 are printed on the surface of each protruding structure 210 and are uniformly distributed along a direction.

[0099] Referring to FIG. 1, the embodiment further comprises a first mask 20 for VCSEL chip photolithography pattern, which comprises: Figure 7

[0100] The substrate 22 and a pattern layer 21 are arranged on one side of the substrate 22;

[0101] The pattern layer 21 is provided with a plurality of protruding structures 210 away from the side of the substrate 22, and the protruding structures 210 are arranged in a linear direction in sequence and side by side, and bosses 211 are uniformly arranged on the surface of the protruding structures 210.

[0102] It can be understood that, due to the current structure of the high-speed modulated VCSEL chip, there are problems of large internal resistance and poor heat dissipation effect. In order to be able to obtain a P-type DBR part 10 with reduced internal resistance and good heat dissipation effect when performing P-type DBR part 10 photolithography on the VCSEL chip, the embodiment is to arrange a pattern layer 21 above the substrate 22, and the pattern layer 21 is provided with a plurality of protruding structures 210 away from the side of the substrate 22, and the protruding structures 210 are arranged in a linear direction in sequence and side by side, and bosses 211 are uniformly arranged on the surface of the protruding structures 210. In this way, the protruding structures 210 of the pattern layer 21 and the bosses 211 on the protruding structures 210 can obtain the required structure of the P-type DBR part 10 through etching technology, so that the VCSEL chip has better heat dissipation effect and reduces the internal resistance of the VCSEL chip.

[0103] When working in real time, when preparing the VCSEL chip, the mask is arranged on the photolithography machine to perform photolithography on the epitaxial wafer, so that the pattern on the pattern layer 21 of the mask is etched on the epitaxial wafer to obtain the required shape and pattern, so that the VCSEL chip prepared by using the mask can realize reducing the internal resistance and has better heat dissipation.

[0104] ​Since the pattern layer 21 of the mask is away from the side of the substrate 22, a plurality of protruding structures 210 are arranged, and the protruding structures 210 are arranged in a straight line direction in turn and side by side, and the bosses 211 are uniformly arranged on the surface of the protruding structure 210. During lithography, the thinner position of the pattern layer 21 disappears first, and then other parts also gradually disappear, so that the pattern on the pattern layer 21 is lithographed on the epitaxial wafer, so that the outer surface of the P-type DBR part 10 is stepped. The protruding structure 210 is arranged as a structure gradually protruding to the center from both sides

[0105] Referring to the drawings Figure 8 It is further shown that the bosses 211 are uniformly arranged in turn and end to end along the side of the protruding structure 210.

[0106] It can be understood that the bosses 211 are arranged in turn along the edge of the side of the protruding structure 210, and the bosses 211 are arranged in end-to-end, that is, by arranging the pattern layer 21 on the upper side of the substrate 22, the pattern layer 21 is arranged with a plurality of protruding structures 210, and during lithography, the protruding structure 210 is a gradually protruding structure, and the bosses 211 are uniformly arranged on the protruding structure 210, so that during continuous lithography, the stepped structure can be effectively formed on the surface of the P-type DBR part 10. The accuracy during lithography is guaranteed, and the stepped structure formed on the surface of the P-type DBR part 10 can effectively reduce the internal resistance of the chip as a whole and improve the heat dissipation efficiency.

[0107] Referring to the drawings Figure 9 and 10 It is further shown that the bosses 211 are controlled to have a protruding height of 1-1.5um.

[0108] It can be understood that the height difference between the two sides parallel to the substrate 22 of the two adjacent bosses 211 is 0.8-2um. By controlling the protruding height of the bosses 211, the structure height of the P-type DBR part 10 during lithography is realized, which can also be considered as controlling the height of the bosses 211, so that the height of the stepped structure formed on the surface of the P-type DBR part 10 during lithography is realized.

[0109] In some embodiments, the height of the protrusion 211 can be set according to the thickness of each layer in the P-type DBR section 10 obtained by epitaxial growth. For example, when the thickness of each layer in the P-type DBR section 10 is 1 um, the height of the protrusion 211 is set to 1 um when the protrusion 211 is made; when the thickness of each layer in the P-type DBR section 10 is 2 um, the height of the protrusion 211 is set to 2 um when the protrusion 211 is made; when the thickness of each layer in the P-type DBR section 10 is 0.8 um, the height of the protrusion 211 is set to 0.8 um when the protrusion 211 is made.

[0110] Referring to the accompanying drawings Figure 10 As shown in the drawings, in some embodiments, the protrusion 211 further includes a first side surface, which is parallel to the substrate 22.

[0111] In some embodiments, the protrusion 211 is provided with at least one first side surface, and the first side surface is parallel to the substrate 22. This ensures the step shape of the P-type DBR section 10 of the VCSEL chip, so that the overall structure of the VCSEL chip is as required, so that the overall internal resistance of the P-type DBR section 10 can be effectively reduced, and the heat dissipation effect is better.

[0112] In some embodiments, the first side surface can be a plane or other plane. It can be understood that by setting the shape of the first side surface of the protrusion 211, the desired selection can be obtained on the P-type DBR section 10 during lithography. For example, in some embodiments, the first side surface is set to be a plane, and the first side surface is parallel to the substrate 22. During lithography of the epitaxial wafer, a corresponding plane can be obtained on the P-type DBR section 10.

[0113] In some embodiments, the distance between the protrusions 210 is 0-1 um.

[0114] It can be understood that the distance between the protrusions 210 can be considered as the distance between the closest positions of two protrusions 210 close to each other. The distance can be 0, or the two protrusions can be separated by a certain distance.

[0115] In some embodiments, the distance between two adjacent protrusions 210 is set to 0, i.e. the closest positions of the two protrusions are in contact with each other. In some other embodiments, the distance between two adjacent protrusions 210 is set to 0.5 um, i.e. the closest positions of the two protrusions have a certain distance. In some other embodiments, the distance between two adjacent protrusions 210 is set to 0.8 um, i.e. the closest positions of the two protrusions have a certain distance.

[0116] Referring to the accompanying drawings Figure 11As shown, the embodiment is further, the cross section shape of the convex structure 210 is triangular or trapezoidal.

[0117] It can be understood that the cross section here can be considered as the cross section opposite to the end surface of the convex structure 210, and can also be considered as the cross section perpendicular to the extending direction of the convex structure 210.

[0118] In an embodiment, the cross section of the convex structure 210 is set to a triangular structure, and the triangular angle here can be rounded. When performing photolithography, the pattern will show that the cross section area of the triangular shape gradually decreases, or the cross section of the triangular shape shows a proportional reduction. In another embodiment, the cross section of the convex structure 210 is set to a trapezoidal structure, and the trapezoidal angle here can be rounded. When performing photolithography, the pattern will show that the cross section area of the trapezoidal shape gradually decreases. Of course, the convex structure 210 can also be designed into other shapes according to actual chip design requirements, which are not listed one by one here.

[0119] The embodiment is further, the pattern layer 21 is a film layer made of positive photoresist.

[0120] It can be understood that in order to ensure that the P-type DBR part 10 of the VCSEL chip can obtain a stepped shape, the embodiment is to use positive photoresist to make the pattern layer 21. During photolithography, the convex structure 210 on the pattern layer 21 is a gradually convex structure, and the convex structure 210 is provided with a boss 211. Due to the positive photoresist pattern layer 21, the pattern gradually disappears during photolithography. Here, the disappearance is from the part closest to the substrate 22, and gradually to the highest part of the boss 211 structure.

[0121] It should be noted that the characteristics of positive photoresist are that after coating and exposing, the exposed part is dissolved, and the unexposed part remains. Therefore, when using positive photoresist for photolithography, the photoresist in the exposed part will gradually disappear, and the photoresist in the unexposed part will remain, forming the required image.

[0122] The embodiment is further, the substrate 22 is a quartz plate.

[0123] S003: By etching, the pattern on the first mask 20 is etched on the VCSEL to obtain a first mesa.

[0124] In the embodiment, the etching can be realized by using the existing etching process, which is not described in detail here. The embodiment is to use the existing etching process to etch the pattern on the first mask 20 on the epitaxial wafer, so as to obtain a stepped shape on the P-type DBR part 10.

[0125] Further, after the first mesa is obtained, the convex 211 on the first mesa is measured for accuracy by a step meter. Specifically, the etching depth of four to six points on the surface of the first mesa is measured randomly to determine the accuracy of etching.

[0126] S004: After the first mesa is obtained, the VCSEL is placed in a wet oxidation device for oxidation.

[0127] In the embodiment, the VCSEL is subjected to wet oxidation between the etching of the first mesa and the etching of the second mesa. Specifically, the VCSEL after the etching of the first mesa is placed in a wet oxidation device for oxidation. The high-aluminum component layer in the epitaxial structure of the VCSEL is oxidized by a large amount of water vapor carried by nitrogen. Then, by controlling the oxidation time and rate and assisted by an infrared light source charge-coupled device image sensor (CCD) system for real-time observation, the purpose of accurately controlling the aperture size of the oxidation is achieved.

[0128] S005: The pattern on the second mask is etched onto the VCSEL by etching to obtain a second mesa.

[0129] In the embodiment, the etching process includes three parts, including etching to obtain the first mesa, the second mesa, and the P-type electrode area conductive layer, respectively. In the embodiment, the etching process can refer to the existing etching process, which will not be described in detail here.

[0130] In addition, in the embodiment, the etching process steps and parameters of the first mesa, the second mesa, and the P-type electrode area conductive layer are consistent, except that different mask plates with different patterns are used for photolithography.

[0131] That is, after the etching of the second mesa, the etching of the P-type electrode area conductive layer is performed, and thus the etching step is completed.

[0132] S006: The VCSEL is provided with an N electrode by evaporation and provided with a P electrode and a P / N ohmic contact by sputtering.

[0133] After the etching process, in order to provide circuit transmission and reflection, the VCSEL is provided with corresponding electrodes by metal evaporation and plating processes. Specifically as follows:

[0134] First, an N electrode is obtained on the VCSEL by electron beam evaporation. The metal material used for the N electrode is AuGeNi alloy plating material, and the thickness of the N electrode is 500Å.

[0135] Next, the VCSEL with the N electrode plated thereon is subjected to a BCB planarization process for planarization.

[0136] Again, on the top of the first mesa of the VCSEL, a P-type electrode is set by using a magnetron sputtering coating process, wherein the metal material of the P-type electrode is Ti / Au, and the thickness of the P-type electrode is 500 Å / 3000 Å;

[0137] Finally, the VCSEL with the electrode is put into a rapid annealing furnace for rapid annealing to achieve the purpose of alloying, so that the electrode and the semiconductor material form a good ohmic contact, and the electrical characteristics of the device are improved.

[0138] In the embodiment, after the evaporation process, the VCSEL needs to be deposited with a silica dioxide protective layer, specifically, a thin film deposition process is used to deposit silicon nitride (Si3N4) or silica dioxide (SiO2) as a passivation insulating protective layer and an emission window protection and antireflection layer. The thickness of the passivation insulating protective layer is generally about 2000 Å; the emission window protection and antireflection layer is generally coated with a thin film with an optical thickness of λ / 4.

[0139] In the application, the surface of the P-type DBR part 10 of the VCSEL is set to a stepped structure, and each step of the stepped structure corresponds to each layer in the P-type DBR part 10, thereby effectively improving the overall performance of the P-type DBR part 10. Therefore, the overall equivalent resistance of the VCSEL can be effectively reduced, and the heat dissipation is also improved, thereby realizing the improvement of the thermal stability and high-speed modulation performance of the chip.

[0140] In order to obtain the stepped structure of the surface of the P-type DBR part 10, in the embodiment, the pattern is etched into the P-type DBR part 10 by etching process through the design of the pattern structure on the mask, thereby obtaining the stepped structure.

[0141] In the embodiment, each step of the stepped structure corresponds to each layer in the P-type DBR part 10, for example, the P-type DBR part 10 has a total of 32 layers, each layer has a height of 1 um, and the stepped structure also has 32 steps, each step has a step height of 1 um. It can also be considered that the steps are the layers in the P-type DBR part 10, which are gradually staggered from right to top.

[0142] The specific examples and beneficial effects of the method in the embodiment can be referred to the description of the saturable absorber above, and will not be repeated here.

[0143] It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. The present disclosure is not limited to the precise construction described above and shown in the accompanying drawings and various modifications and changes can be effected therein by those skilled in the art without departing from the scope of the application. The scope of the present disclosure is limited only by the claims appended hereto. Thus, it is intended that the present application cover modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A VCSEL chip for use in a semiconductor laser, characterized in that, include: The N-electrode, the N-type DBR section, the active section, the P-type DBR section, and the P-electrode are arranged in a stacked manner from bottom to top. The P-type DBR section is configured as a multi-layer structure stacked sequentially, and the lateral area of ​​each layer of the multi-layer structure gradually decreases from bottom to top; Furthermore, the adjacent layers of the multilayer structure are configured such that the edge of the upper surface of the lower DBR layer is at a distance from the edge of the lower surface of the upper DBR layer, so that the horizontal area of ​​each layer of the P-type DBR section gradually increases from top to bottom, forming a stepped structure.

2. The VCSEL chip according to claim 1, characterized in that, The distance control is 0.8-2 μm.

3. The VCSEL chip according to claim 1, characterized in that, The transverse cross-sectional shape of the P-type DBR section includes circular, elliptical, or rectangular shapes.

4. The VCSEL chip according to claim 1, characterized in that, The number of layers in the P-type DBR section is 16-40.

5. The VCSEL chip according to claim 1, characterized in that, The thickness of each layer of the P-type DBR is controlled to be 1-1.5 μm.

6. The VCSEL chip according to claim 1, characterized in that, The P-type DBR section is made of a material.

7. The VCSEL chip according to claim 1, characterized in that, The N electrode is an AuGeNi alloy plating material with a thickness of 500 Å; the P electrode is a Ti / Au material with a thickness of 500 Å / 3000 Å.

8. A VCSEL laser, characterized in that, include: The VCSEL chip according to any one of claims 1-7.

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