Signal delay module, electronic circuit and circuit system

Abstract

The present invention provides a signal delay module, an electronic circuit and a circuit system, wherein the signal delay module comprises: a conversion and adjustment unit for converting an input signal from voltage to current; a capacitor charge / discharge unit connected to the conversion and adjustment unit for performing capacitor charge / discharge operations according to the converted input signal to obtain a capacitor voltage and a charge / discharge current; a voltage comparison unit connected to the capacitor charge / discharge unit for comparing the capacitor voltage with a reference voltage to obtain a voltage comparison result; a current comparison unit connected to the capacitor charge / discharge unit for comparing the charge / discharge current with a reference current to obtain a current comparison result; and a logic processing unit connected to the voltage comparison unit and the current comparison unit, respectively, for performing logic operations on the voltage comparison result and the current comparison result to obtain an output signal, thereby increasing a delay in the output signal. The present invention solves the problem that the existing signal delay design has a large circuit board volume due to the addition of passive components.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuit design, and in particular to a signal delay module, an electronic circuit and a circuit system. Background Art

[0002] In the design and application of integrated circuits, the signal can be delayed by adjusting the parameters of the circuit components to ensure the stability and reliability of the circuit operation.

[0003] Typically, integrated circuits with signal ports will have a comparator and a reference voltage source integrated inside the chip. The positive input of the comparator is connected to the signal port, and the negative input is connected to the reference voltage source, such as Figure 1 As shown in the figure, when the input voltage VIN of the signal port is greater than the reference voltage VREF, the comparator outputs a high level. When the input voltage VIN of the signal port is less than the reference voltage VREF, the comparator outputs a low level. Because the comparator has a small response delay and the input voltage rises and falls quickly, there is basically no delay from the input voltage to the comparator output.

[0004] In actual applications, there is no signal delay circuit reserved inside the integrated circuit. When the signal needs to be delayed, a signal delay circuit consisting of resistor R0, diode D0 and capacitor C0 can be added to the chip periphery, such as Figure 2 As shown in the figure, by changing the values ​​of resistor R0 and capacitor C0, the charging time and discharging time of the capacitor are adjusted, thereby changing the delay time from the input voltage to the comparator output. However, the disadvantage of this design is that several passive components need to be added to the circuit board, which will increase the size of the circuit board and increase the cost.

[0005] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a signal delay module, an electronic circuit and a circuit system for solving the problem that the existing signal delay design results in a large circuit board volume due to the addition of passive components.

[0007] To achieve the above-mentioned and other related purposes, the present invention provides a signal delay module, comprising:

[0008] Conversion and regulation unit, capacitor charge / discharge unit, voltage comparison unit, current comparison unit and logic processing unit;

[0009] The conversion and regulation unit is used to convert the input signal from voltage to current;

[0010] The capacitor charging / discharging unit is connected to the conversion and regulation unit, and is used to perform capacitor charging / discharging operations according to the converted input signal and obtain capacitor voltage and charging / discharging current;

[0011] The voltage comparison unit is connected to the capacitor charge / discharge unit, and is used to compare the capacitor voltage with a reference voltage and obtain a voltage comparison result;

[0012] The current comparison unit is connected to the capacitor charge / discharge unit, and is used to compare the charge / discharge current with a reference current and obtain a current comparison result;

[0013] The logic processing unit is connected to the voltage comparison unit and the current comparison unit respectively, and is used to perform logic operations on the voltage comparison result and the current comparison result to obtain an output signal, thereby adding a delay to the output signal.

[0014] Optionally, the conversion adjustment unit is further used to adjust the delay time of the output signal.

[0015] Optionally, the conversion adjustment unit includes a resistor, a first end of which receives the input signal and a second end of which outputs the converted input signal; wherein the delay time of the output signal is adjusted by adjusting the resistance value of the resistor.

[0016] Optionally, the capacitor charging / discharging unit includes a capacitor, a first NMOS transistor and a constant current source; the first end of the capacitor receives the converted input signal and outputs the capacitor voltage, and the second end is connected to the drain end of the first NMOS transistor; the gate end of the first NMOS transistor is connected to the constant current source and outputs a bias voltage, the drain end is short-circuited with its gate end, and the source end is grounded; wherein, the bias voltage is related to the charging / discharging current of the capacitor.

[0017] Optionally, the capacitor charge / discharge unit further includes a diode, a cathode end of which is connected to the second end of the capacitor, and an anode end of which is grounded.

[0018] Optionally, the voltage comparison unit includes a comparator and a reference voltage source; a first input terminal of the comparator receives the capacitor voltage, a second input terminal is connected to the reference voltage source, and an output terminal outputs the voltage comparison result.

[0019] Optionally, the current comparison unit includes a second NMOS tube, a reference current source and a Schmitt trigger; the gate terminal of the second NMOS tube receives a bias voltage, the drain terminal is connected to the reference current source and the input terminal of the Schmitt trigger, and the source terminal is grounded; the output terminal of the Schmitt trigger outputs the current comparison result; wherein the bias voltage is related to the charge / discharge current.

[0020] Optionally, the logic processing unit includes an OR gate, a first input terminal receives the voltage comparison result, a second input terminal receives the current comparison result, and an output terminal outputs the output signal.

[0021] The present invention also provides an electronic circuit, comprising: a signal delay module as described in any one of the above items, wherein the capacitor charging / discharging unit, the voltage comparison unit, the current comparison unit and the logic processing unit are integrated into a chip, and the conversion and adjustment unit is arranged outside the chip and is connected to the capacitor charging / discharging unit through the signal port of the chip.

[0022] The present invention also provides a circuit system, comprising: the electronic circuit as described above.

[0023] As described above, the signal delay module, electronic circuit, and circuit system of the present invention propose a new signal delay design. When applied to integrated circuit design, since only one resistor is provided outside the chip, it is beneficial to reduce the circuit volume. Moreover, changing the resistance value can also adjust the delay time of the output signal, especially the delay time for the output signal to change from a high level to a low level. In addition, by selecting whether to connect a resistor in series outside the chip, the addition of a signal delay function in the integrated circuit can be realized, which is beneficial to increase application flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 Shown is a schematic diagram of a conventional integrated circuit.

[0025] Figure 2 The diagram shows a schematic diagram of adding a signal delay circuit to the periphery of an existing integrated circuit.

[0026] Figure 3 Shown is a schematic diagram of the signal delay module of the present invention.

[0027] Figure 4 Shown is a schematic diagram of the electronic circuit of the present invention.

[0028] Figure 5 Shown is a waveform diagram of the relevant signals in the signal delay module of the present invention.

[0029] Description of component numbers: 100 electronic circuit, 110 signal delay module, 111 conversion adjustment unit, 112 capacitor charging / discharging unit, 113 voltage comparison unit, 114 current comparison unit, 115 logic processing unit, 120 chip. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] See also Figures 3 to 5 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the form, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0032] like Figure 3 As shown, this embodiment provides a signal delay module 110 , which includes a conversion adjustment unit 111 , a capacitor charge / discharge unit 112 , a voltage comparison unit 113 , a current comparison unit 114 and a logic processing unit 115 .

[0033] The conversion and adjustment unit 111 is used to convert the input signal IN from voltage to current; further, the conversion and adjustment unit 111 is also used to adjust the delay time of the output signal OUTPUT.

[0034] In one embodiment, the conversion and adjustment unit 111 includes a resistor R1; wherein the first end of the resistor R1 receives the input signal IN, and the second end of the resistor R1 outputs the converted input signal IN. In this embodiment, the delay time of the output signal OUTPUT can be adjusted by adjusting the resistance value of the resistor R1. In practical applications, the resistor R1 can be implemented by a single resistor or by at least two resistors, wherein when at least two resistors are implemented, each resistor can be connected in series, in parallel, or in a mixed connection (including both series and parallel connections). The input signal IN is usually a control signal, and its voltage rises and falls at a relatively fast speed, and the switching time is generally less than 10ns; in addition, the control signal has a large output current capability, generally greater than 1mA.

[0035] The capacitor charge / discharge unit 112 is connected to the conversion and regulation unit 111 and is configured to perform capacitor charge / discharge operations according to the converted input signal IN and obtain a capacitor voltage VC1 and a charge / discharge current IC1 (including a charging current and a discharging current).

[0036] In one embodiment, the capacitor charge / discharge unit 112 includes a capacitor C1, a first NMOS transistor N1, and a constant current source I0; wherein the first end of the capacitor C1 receives the converted input signal IN and outputs a capacitor voltage VC1, the second end of the capacitor C1 is connected to the drain end of the first NMOS transistor N1, the gate end of the first NMOS transistor N1 is connected to the constant current source I0 and outputs a bias voltage, the drain end of the first NMOS transistor N1 is short-circuited with its gate end, and the source end of the first NMOS transistor N1 is grounded. In this embodiment, the capacitor voltage VC1 and the charge / discharge current IC1 are obtained by charging / discharging the capacitor C1, wherein the bias voltage is related to the charge / discharge current IC1 of the capacitor C1. In practical applications, the delay time of the output signal OUTPUT can also be adjusted by adjusting the capacitance of the capacitor C1. However, when the signal delay module 110 of this embodiment is designed as an integrated circuit, the capacitor C1 is usually integrated into the chip, making it difficult to adjust the capacitance. Therefore, the delay time of the output signal OUTPUT is generally adjusted only by adjusting the resistance of the resistor R1.

[0037] Furthermore, the capacitor charge / discharge unit 112 further includes a diode D1; wherein the cathode terminal of the diode D1 is connected to the second terminal of the capacitor C1, and the anode terminal of the diode D1 is grounded; the diode D1 is used to clamp the minimum voltage at the second terminal of the capacitor C1. Typically, the forward voltage of the diode D1 is generally approximately 0.7V. When the potential at the second terminal of the capacitor C1 drops below -0.7V, the diode D1 conducts, clamping the minimum potential at the second terminal of the capacitor C1 at -0.7V. In practical applications, other structures with a clamping function may be used to replace the diode D1, which has no substantial impact on the implementation of the solution of this embodiment.

[0038] The voltage comparison unit 113 is connected to the capacitor charge / discharge unit 112 and is configured to compare the capacitor voltage VC1 with the reference voltage VREF and obtain a voltage comparison result OUT1 .

[0039] In one embodiment, the voltage comparison unit 113 includes a comparator CMP and a reference voltage source VREF. A first input terminal of the comparator CMP receives the capacitor voltage VC1, a second input terminal of the comparator CMP is connected to the reference voltage source VREF, and an output terminal of the comparator CMP outputs a voltage comparison result OUT1. In this embodiment, the first input terminal of the comparator CMP is a positive input terminal, and the second input terminal of the comparator CMP is a negative input terminal. When the capacitor voltage VC1 is greater than the reference voltage VREF, the voltage comparison result OUT1 output by the comparator CMP is a high level. When the capacitor voltage VC1 is less than the reference voltage VREF, the voltage comparison result OUT1 output by the comparator CMP is a low level.

[0040] The current comparison unit 114 is connected to the capacitor charge / discharge unit 112 and is configured to compare the charge / discharge current IC1 with the reference current IREF and obtain a current comparison result OUT2 .

[0041] In one embodiment, the current comparison unit 114 includes a second NMOS transistor N2, a reference current source IREF, and a Schmitt trigger SMIT. The gate terminal of the second NMOS transistor N2 receives a bias voltage. The drain terminal of the second NMOS transistor N2 is connected to the reference current source IREF and the input terminal of the Schmitt trigger SMIT. The source terminal of the second NMOS transistor N2 is grounded. The output terminal of the Schmitt trigger SMIT outputs a current comparison result OUT2. In this embodiment, the gate terminal of the second NMOS transistor N2 is connected to the gate terminal of the first NMOS transistor N1. The first NMOS transistor N1 and the second NMOS transistor N2 form a current mirror structure. The width-to-length ratios of the first NMOS transistor N1 and the second NMOS transistor N2 are 1:M (M is a natural number greater than or equal to 1). Therefore, the ratio of the drain currents of the first NMOS transistor N1 and the second NMOS transistor N2 is 1:M, that is, ID1 = ID2 / M. And the drain current of the first NMOS transistor N1 also satisfies ID1 = IC1 + I0. Thus, the charging / discharging current IC1 of the capacitor C1 can be introduced into the current comparison unit 114, that is, ID2 = M(IC1 + I0). When the charging / discharging current IC1 and the reference current IREF satisfy IC1 < (IREF / M - I0), that is, IREF > ID2, the current comparison result OUT2 output by the Schmitt trigger SMIT is at a low level. When the charging / discharging current IC1 and the reference current IREF satisfy IC1 > (IREF / M - I0), that is, IREF < ID2, the current comparison result OUT2 output by the Schmitt trigger SMIT is at a high level. Here, ID1 is the drain current of the first NMOS transistor, ID2 is the drain current of the second NMOS transistor, I0 is the current value of the constant current source, and IREF is the current value of the reference current source. In practical applications, when designing the module, it is necessary to ensure that IREF / M > I0 so that when IC1 ≤ 0, the Schmitt trigger SMIT outputs a low level. It is also necessary to ensure that △VIN / R1 + I0 > IREF / M so that when the charging current of the capacitor C1 is greater than a certain value, the output of the Schmitt trigger SMIT can be flipped to a high level, where △VIN is the difference between the maximum voltage and the minimum voltage of the input signal IN.

[0042] The logic processing unit 115 is respectively connected to the voltage comparison unit 113 and the current comparison unit 114, and is used to perform a logic operation on the voltage comparison result OUT1 and the current comparison result OUT2 and obtain an output signal OUTPUT, so as to add a delay to the output signal OUTPUT.

[0043] In one embodiment, the logic processing unit 115 includes an OR gate; wherein a first input terminal of the OR gate OR receives the voltage comparison result OUT1, a second input terminal of the OR gate OR receives the current comparison result OUT2, and an output terminal of the OR gate OR outputs an output signal OUTPUT. In this embodiment, when both the voltage comparison result OUT1 and the current comparison result OUT2 are low, the output signal OUTPUT is low; when at least one of the voltage comparison result OUT1 and the current comparison result OUT2 is high, the output signal OUTPUT is high.

[0044] Correspondingly, such as Figure 4 As shown, this embodiment further provides an electronic circuit 100, including the signal delay module 110 as described above; wherein, the capacitor charging / discharging unit 112, the voltage comparison unit 113, the current comparison unit 114 and the logic processing unit 115 are integrated in the chip 120, and the conversion and regulation unit 111 is arranged outside the chip 120 and is connected to the capacitor charging / discharging unit 112 through the signal port PORT of the chip 120.

[0045] In practical applications, if the signal delay function is not required, the conversion and regulation unit 111 can be removed and the input signal IN can be directly connected to the signal port PORT of the chip 120. In this case, the voltage of the signal port PORT is the voltage VIN of the input signal. When the voltage of the input signal IN is greater than the reference voltage VREF, the comparator CMP outputs a high level, and the output signal OUTPUT is a high level. When the voltage of the input signal IN is less than the reference voltage VREF, the comparator CMP outputs a low level, and the output signal OUTPUT is a low level. Because the comparator has a small response delay, the voltage of the input signal IN rises and falls quickly. Therefore, there is essentially no delay from the input signal IN to the output signal OUTPUT.

[0046] Accordingly, this embodiment also provides a circuit system (not shown in the figure), including the electronic circuit 100 as described above; of course, the circuit system can also include other functional circuits, and the circuit type is specifically determined by the system function, which is not limited in this embodiment.

[0047] Next, please combine Figure 3 and Figure 4 , see Figure 5 , the working principle of the signal delay module 110 of this embodiment is described in detail.

[0048] At time t0, the input signal IN changes from low level to high level, and the voltage VIN of the input signal starts to rise from the minimum voltage. At this time, the input signal IN charges the capacitor C1 through the resistor R1, and the charging current satisfies IC1 = (VIN - VC1) / R1; since the rising speed of VIN is relatively fast, as VIN rises, the voltage difference between VIN and VC1 increases, and the charging current of the capacitor C1 increases. At this moment, since the capacitor voltage VC1 of the capacitor C1 < VREF, the comparator CMP outputs a low level, and since IC1 < IREF / M - I0, the Schmitt trigger SMIT outputs a low level, and the output signal OUTPUT is at a low level.

[0049] At time t1, the charging current increases to make IC1 > IREF / M - I0 > 0. Since ID1 = IC1 + I0 = ID2 / M, then ID2 > IREF. At this time, the output of the Schmitt trigger SMIT changes from low level to high level, and the output signal OUTPUT changes from low level to high level.

[0050] At time t2, the capacitor C1 is charged to satisfy VC1 > VREF. At this time, the output of the comparator CMP changes from low level to high level, and the output signal OUTPUT remains at a high level.

[0051] At time t3, the voltage VIN of the input signal rises to the maximum value, and the voltage difference between VIN and VC1 reaches the maximum; after time t3, since VIN no longer rises while VC1 continues to rise, therefore, the voltage difference between VIN and VC1 gradually decreases, and the charging current of the capacitor C becomes gradually decreases.

[0052] [[ID=##]]At time t4, the charging current of the capacitor C1 decreases to make IC1 < IREF / M - I0. Since ID1 = IC1 + I0 = ID2 / M, then ID2 < IREF. At this time, the output of the Schmitt trigger SMIT changes from high level to low level; but since the output of the comparator CMP is at a high level, the output signal OUTPUT remains at a high level.

[0053] At time t5, the capacitor C1 is charged to a voltage that is basically equal to the maximum voltage of the input signal IN. At this time, the charging current of the capacitor C1 drops to 0.

[0054] It should be noted that there seems to be a typo in the original text where "电容C1的充电电流逐渐下降" was written as "电容C的充电电流逐渐下降" in the translation of ID=9. It should be "电容C1的充电电流逐渐下降". And there is also a potential error in the numbering in the translation of ID=12 where it says "ID=##" instead of "ID=12". The above translation has been corrected accordingly.At time t6, the input signal IN changes from high level to low level, and the voltage VIN of the input signal starts to drop from the maximum voltage. At this time, the voltage value of VIN is lower than the voltage value of capacitor C1. The input signal IN discharges capacitor C1 through resistor R1, and the discharge current satisfies IC1 = (VIN - VC1) / R1, IC1 < 0; Since ID1 = IC1 + I0 = ID2 / M and IC1 < 0, so ID2 < IREF, the output of the Schmitt trigger SMIT remains low level. Also, because VC1 > VREF, the output of the comparator CMP remains high level, so the output signal OUTPUT remains high level.

[0055] At time t7, the input signal IN drops to the minimum voltage, and the input signal IN still discharges capacitor C1 through resistor R1, and the voltage value of capacitor C1 continues to drop; Since ID1 = IC1 + I0 = ID2 / M and IC1 < 0, so ID2 < IREF, the output of the Schmitt trigger SMIT remains low level. Also, because VC1 > VREF, the output of the comparator CMP remains high level, so the output signal OUTPUT remains high level.

[0056] At time t8, capacitor C1 continues to be discharged, and the voltage value drops to VC1 < VREF. At this time, the output of the comparator CMP changes from high level to low level, and the output signal OUTPUT changes from high level to low level.

[0057] At time t9, capacitor C1 is discharged to a voltage basically equal to the minimum voltage of the input signal IN. At this time, the discharge current of capacitor C1 becomes 0.

[0058] From the process analysis of the above times t0 to t9, it can be seen that:

[0059] When the input signal IN transitions from a low level to a high level, the output signal OUTPUT transitions from a low level to a high level after a delay. This delay is determined by the time it takes for the output of the Schmitt trigger SMIT to transition from a low level to a high level. When the input signal IN transitions from a low level to a high level, the charging current of capacitor C1 increases to a value greater than (IREF / M-I0), and then the output of the Schmitt trigger SMIT transitions from a low level to a high level. The delay at this time is (t1-t0). This delay is related to the voltage rise rate of the input signal IN and the resistance value of resistor R1. The faster the voltage rise rate of the input signal IN, the greater the voltage difference between VIN and VC1, the faster the charging current of capacitor C1 increases, and the shorter the delay time. Furthermore, the smaller the resistance value of resistor R1, the greater the charging current of capacitor C1, and the shorter the delay time. In practical applications, the input signal IN rises from a low level to a high level very quickly, generally less than 10ns. This causes the charging current of the capacitor C1 to increase rapidly enough to cause the output of the Schmitt trigger SMIT to change from a low level to a high level. At this time, the delay time for the output signal OUTPUT to change from a low level to a high level can be ignored.

[0060] When the input signal IN transitions from high to low, the output signal OUTPUT transitions from high to low after a delay. This delay is determined by the time it takes the comparator CMP output to transition from high to low. When the input signal IN transitions from high to low, the capacitor voltage VC1 drops below the reference voltage VREF, and the comparator CMP output transitions from high to low. The delay at this point is (t8 - t6). This delay is related to the time constant τ (τ = R1 * C1). A larger τ means a slower discharge of capacitor C1, a longer transition from high to low, and a longer delay. In practical applications, the delay time for the output signal OUTPUT to transition from high to low can be increased by increasing R1 * C1—that is, by increasing at least one of R1 and C1.

[0061] When the signal delay module 110 is applied to an integrated circuit design, the capacitor C1 is integrated inside the chip. In this case, the value of the capacitor C1 can be set as large as possible; increasing the value of the capacitor C1 has little effect on the delay time (t1-t0), while increasing the delay time (t8-t6). In addition, the resistor R1 is set outside the chip, and the delay time for the input signal IN to change from a high level to a low level can be changed by adjusting the value of the resistor R1. The larger the value of the resistor R1, the longer the delay time; at the same time, the delay time for the input signal IN to change from a low level to a high level is basically negligible due to the effect of the resistor R1 value.

[0062] In summary, the signal delay module, electronic circuit, and circuit system of the present invention propose a novel signal delay design. When applied to integrated circuit design, since only one resistor is placed outside the chip, this helps reduce circuit size. Furthermore, changing the resistor value can adjust the output signal delay time, particularly the delay time for the output signal to change from a high level to a low level. Furthermore, by selecting whether to connect a resistor in series outside the chip, the signal delay function can be added or not to the integrated circuit, which helps increase application flexibility. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial application value.

[0063] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A signal delay module, characterized in that: include: Conversion and regulation unit, capacitor charging / discharging unit, voltage comparison unit, current comparison unit and logic processing unit; The conversion and regulation unit is used to convert the input signal from voltage to current; The capacitor charging / discharging unit is connected to the conversion and regulation unit, and is used to perform capacitor charging / discharging operations according to the converted input signal and obtain capacitor voltage and charging / discharging current; The voltage comparison unit is connected to the capacitor charge / discharge unit and is used to compare the capacitor voltage with a reference voltage and obtain a voltage comparison result; The current comparison unit is connected to the capacitor charging / discharging unit and is used to compare the charging / discharging current with a reference current and obtain a current comparison result; The logic processing unit is connected to the voltage comparison unit and the current comparison unit respectively, and is used to perform logic operations on the voltage comparison result and the current comparison result to obtain an output signal, so as to increase a delay in the output signal; Wherein, the capacitor charging / discharging unit includes a capacitor, a first NMOS tube and a constant current source; the first end of the capacitor receives the converted input signal and outputs the capacitor voltage, and the second end is connected to the drain end of the first NMOS tube; the gate end of the first NMOS tube is connected to the constant current source and outputs a bias voltage, the drain end is short-circuited with its gate end, and the source end is grounded; wherein the bias voltage is related to the charging / discharging current of the capacitor; The current comparison unit includes a second NMOS tube, a reference current source and a Schmitt trigger; the gate terminal of the second NMOS tube receives a bias voltage, the drain terminal is connected to the reference current source and the input terminal of the Schmitt trigger, and the source terminal is grounded; the output terminal of the Schmitt trigger outputs the current comparison result.

2. The signal delay module according to claim 1, characterized in that: The conversion adjustment unit is also used to adjust the delay time of the output signal.

3. The signal delay module according to claim 2, characterized in that: The conversion adjustment unit includes a resistor, a first end of which receives the input signal, and a second end of which outputs the converted input signal; wherein the delay time of the output signal is adjusted by adjusting the resistance value of the resistor.

4. The signal delay module according to claim 1, characterized in that: The capacitor charging / discharging unit further comprises a diode, a cathode end of which is connected to the second end of the capacitor, and an anode end of which is grounded.

5. The signal delay module according to claim 1, characterized in that: The voltage comparison unit includes a comparator and a reference voltage source; the first input terminal of the comparator receives the capacitor voltage, the second input terminal is connected to the reference voltage source, and the output terminal outputs the voltage comparison result.

6. The signal delay module according to claim 1, characterized in that: The logic processing unit comprises an OR gate, a first input terminal receives the voltage comparison result, a second input terminal receives the current comparison result, and an output terminal outputs the output signal.

7. An electronic circuit, characterized in that: include: The signal delay module according to any one of claims 1 to 6, wherein the capacitor charge / discharge unit, the voltage comparison unit, the current comparison unit and the logic processing unit are integrated in a chip, and the conversion adjustment unit is arranged outside the chip and connected to the capacitor charge / discharge unit through a signal port of the chip.

8. A circuit system, characterized in that: include: The electronic circuit as claimed in claim 7.

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