A storage chip aging prediction method and device based on topological sorting

Abstract

The present invention discloses a storage chip aging prediction method and device based on topological sorting, S1, constructing an operation parameter set; S2, establishing a dependency graph between modules inside the storage chip based on the operation parameter set; S3, applying topological sorting to sort the dependency graph and generating an execution sequence of the module; S4, performing data preprocessing and feature extraction on the operation parameter set to generate a feature data set; S5, constructing a double-layer generative adversarial network model; S6, applying the trained double-layer generative adversarial network model to the operation parameter set obtained in real time, combining the execution sequence and the topological sorting results, predicting the overall aging trend of the storage chip, and generating a failure time estimate; S7, when the aging trend reaches a preset threshold, triggering an early warning mechanism, including instructions to prompt the user to perform preventive maintenance or data backup. The present invention can dynamically adjust the prediction results to ensure the synchronization of the aging trend prediction with the actual operation situation.

Description

Technical Field

[0001] The present invention relates to the field of storage chip technology, and in particular to a storage chip aging prediction method and device based on topological sorting. Background Art

[0002] In modern computer systems, storage chips are core components, and their performance and reliability are directly related to the overall stability and life of the system. With the continuous popularization of electronic devices and the wide expansion of their application fields, the working environment and load conditions of storage chips have become more complex and changeable, resulting in increasingly prominent chip aging problems. The aging of storage chips is usually manifested as decreased data storage stability, slower read and write speeds, and increased power consumption. The final result of these phenomena may lead to system crashes and serious data loss. Therefore, how to accurately predict the aging trend of storage chips and take corresponding preventive measures in a timely manner has become a focus of general concern for electronic equipment manufacturers and users.

[0003] In the prior art, the aging prediction method of storage chips mainly focuses on the analysis of a single parameter or a single module, and usually uses temperature, voltage, and frequency indicators as the main basis for aging evaluation. However, this method has obvious limitations, because the modules inside the storage chip do not work independently, but interact with each other through complex dependencies. The traditional aging prediction method fails to fully consider the dependencies between modules, which easily leads to misjudgment of the overall aging trend of the system or omission of key aging issues. When a key module ages, it may cause a chain reaction in other subsystems or modules that depend on the module, and traditional methods are often unable to effectively capture and analyze this chain effect.

[0004] In addition, the storage chip aging prediction in the existing technology is mostly based on the analysis of static data or historical data, and lacks effective monitoring and dynamic adjustment of real-time operation data. Since the aging of storage chips is a dynamic process affected by many factors, real-time acquisition and analysis of operation data is crucial to accurately predict the aging trend of chips. However, traditional aging prediction methods often lack real-time performance and cannot promptly reflect the health status of storage chips under actual working conditions, resulting in the prediction results lagging behind the actual aging process, and thus failing to provide timely warnings and effective decision support.

[0005] Another significant flaw of the existing technology is that it fails to fully utilize modern algorithm technology to optimize the prediction model when dealing with complex storage chip architectures. The dependencies between modules within the storage chip constitute a complex system. How to effectively identify and sort the dependencies is crucial to improving the accuracy of aging predictions. Traditional prediction models usually use simple statistical or regression analysis methods, which cannot handle such complex dependencies, making it difficult to achieve accurate aging predictions in complex systems.

[0006] In summary, the existing storage chip aging prediction technology has deficiencies in many aspects, including failure to fully consider the dependencies between modules, lack of dynamic analysis of real-time operation data, and insufficient algorithms when processing complex chip architectures. This not only limits the accuracy of the prediction, but may also lead to delays in system maintenance and management, thereby increasing the risk of system failure and data loss. Therefore, there is an urgent need for a technology that can comprehensively analyze the internal dependencies of the chip, combine real-time data for dynamic prediction, and use advanced algorithms to optimize the prediction model, so as to address the defects in the existing technology and improve the accuracy and reliability of storage chip aging prediction. Summary of the invention

[0007] One object of the present invention is to propose a storage chip aging prediction method and device based on topological sorting, which can dynamically adjust the prediction results to ensure the synchronization of aging trend prediction and actual operating conditions.

[0008] A storage chip aging prediction method based on topological sorting according to an embodiment of the present invention comprises the following steps:

[0009] S1. Obtain temperature data, voltage data, operating frequency data and load data of each module in the storage chip and construct an operating parameter set;

[0010] S2. Establish a dependency graph between modules inside the storage chip based on the operating parameter set. The dependency graph is a directed acyclic graph, in which the nodes of the dependency graph represent the modules and the edges represent the dependency relationships between the modules.

[0011] S3. Apply topological sorting to sort the dependency graph and generate an execution sequence of the modules. The execution sequence reflects the priority and dependency order between the modules.

[0012] S4, performing data preprocessing and feature extraction on the operating parameter set to generate a feature data set, the feature data set including the historical aging mode, current state and mutual influence of each module;

[0013] S5. Construct a two-layer generative adversarial network model:

[0014] The first generator generates a module aging path based on an input feature data set. The module aging path refers to the execution sequence of the module during the generation process to ensure that the generated path matches the module dependency relationship;

[0015] A first discriminator, which evaluates the authenticity of the module aging path generated by the first generator and performs feedback optimization on the first generator;

[0016] A second generator generates an aging trend prediction of the overall storage chip based on the module aging path and execution sequence generated by the first generator, and the execution sequence is used to guide the second generator to identify and prioritize key modules that have a significant impact on the overall aging trend;

[0017] a second discriminator, which evaluates the reliability of the aging trend prediction generated by the second generator and performs feedback optimization on the second generator;

[0018] S6. Apply the trained two-layer generative adversarial network model to the real-time acquired operation parameter set, combine the execution sequence and topological sorting results, predict the overall aging trend of the storage chip, and generate failure time estimation;

[0019] S7. When the aging trend reaches a preset threshold, an early warning mechanism is triggered, including instructions to prompt the user to perform preventive maintenance or data backup.

[0020] Optionally, the S1 includes:

[0021] S11. The temperature data of each module is collected in real time through the sensor integrated in the storage chip. i (t), voltage data V i (t), working frequency data f i (t) and load data L i (t), where i represents the i-th module in the storage chip and t represents time;

[0022] S12, collect the temperature data T of each module i (t), voltage data V i (t), working frequency data f i (t) and load data L i (t) is normalized to obtain the normalized temperature data ( Voltage data Operating frequency data and load data

[0023] S13, the normalized temperature data ( Voltage data Operating frequency data and load data According to the time series storage, the operating parameter set P(t) of all modules of the storage chip is constructed:

[0024]

[0025] Where n is the number of modules in the storage chip.

[0026] Optionally, S2 includes:

[0027] S21, based on the data of each module in the operating parameter set P(t), analyze the interdependence between the modules and determine the dependency weight W between the modules ij (t):

[0028]

[0029] Among them, α, β, γ and λ are weight coefficients; ∈ is the minimum constant to avoid division by zero, σ L is the standard deviation of the load difference; S ij Represents the structural similarity between module i and module j;

[0030] S22, according to the dependency weight W ij (t), construct a multi-level dependency graph G k (V k ,E k ), the multi-level dependency graph is a directed acyclic graph:

[0031]

[0032] Among them, d ij Represents the physical distance or communication delay between module i and module j. By minimizing the logarithm of the total weight in the dependency graph, the dependency graph structure G at each level is determined. k (V k ,E k );

[0033] S23. A multi-level dependency graph includes at least two levels, and the nodes and edges of each level are associated by the following formula:

[0034]

[0035] Among them, φ ij represents the connection strength between module i at level k and module j at level k+1.

[0036] Optionally, the S3 includes:

[0037] S31. Multi-level dependency graph G k (V k ,Ek ) Apply the topological sorting algorithm to determine the node order in each level of dependency graph and generate a preliminary module sorting sequence {v i1 ,v i2 ,…,v im}, where v ij represents the jth module in level k, and m is the number of nodes in level k;

[0038] S32, based on the preliminary module sorting sequence, according to the dependency weight W ij (t) and physical distance or communication delay d ij , optimize and adjust the order of the preliminary module sorting sequence to form the final module execution sequence v i1 ',v i2 ',,v im '}, the optimization criterion is to minimize the global dependency delay, that is:

[0039]

[0040] Among them, δ(v ij '→v il ') is an indicator function, when the module v ij 'In module v il 'When executed before, δ takes the value of 1, otherwise it takes the value of 0.

[0041] Optionally, the S4 includes:

[0042] S41, perform data cleaning and normalization processing on the operating parameter set P(t), remove abnormal data points and noise data, and obtain the cleaned operating parameter set P c (t);

[0043] S42, based on the operating parameter set P after cleaning c (t), extract the historical aging pattern H of each module i (t), including temperature aging model Voltage aging mode Operating frequency aging mode and load aging mode

[0044]

[0045] in, represents the normalized operating parameters of module i at time point τ, α X is the weight coefficient of the corresponding parameter, which is used to measure the influence of different parameters on aging. X is the historical attenuation coefficient, which is used to control the influence of earlier data on the current aging pattern. It means that at time t, a certain operating parameter X i The historical aging pattern of module i is formed;

[0046] S43, by analyzing historical aging patterns i (t) and the current state Calculate the aging trend and status score S of each module i (t):

[0047]

[0048] Among them, w X is the weight of different aging modes, which is used to reflect the importance of each aging mode in the module aging trend, ∈ is the minimum constant to avoid division by zero;

[0049] S44, combining the mutual influence relationship between modules, using the dependency weight W ij (t) Modify the state score and generate the feature data set F(t):

[0050]

[0051] Optionally, the S5 includes:

[0052] S51, constructing a two-layer generative adversarial network model, which includes a first generator, a first discriminator, a second generator and a second discriminator, wherein the input and output of each generator and discriminator are respectively used to generate module aging paths and overall aging trend predictions, and to evaluate and optimize authenticity and reliability;

[0053] S52, the first generator G1, input is the feature data set and the module execution sequence, generates the module aging path P i (t), the dependencies between integrated modules during the generation process:

[0054]

[0055] Among them, T i (t) is the target aging path, L dep (P i (t),W ij (t)) is the dependency loss function, which reflects the matching degree of module dependency, and λ1 is the coefficient that controls the influence of dependency loss;

[0056] S53, the first discriminator D1, the input is the module aging path P generated by the first generator G1 i (t) and the actual aging path T i (t), judge the authenticity of the generated path through the binary classification task and generate the loss function:

[0057]

[0058] S54, the second generator G2, inputs the module aging path P generated by the first generator G1 i (t) and execution sequence to generate the aging trend prediction of the overall storage chip The generation process identifies and prioritizes key modules that have a significant impact on the overall aging trend:

[0059]

[0060] Among them, T real (t) is the overall aging trend of the target, is the key module impact loss function, which reflects the influence of the key module on the overall aging trend, and λ2 is the coefficient controlling the loss influence of the key module;

[0061] S55, second discriminator D2, input is the overall aging trend prediction generated by the second generator G2 The real aging trend real (t), the reliability of the generated trend is judged through the binary classification task, and the loss function is generated:

[0062]

[0063] S56, repeatedly iteratively train the first generator G1, the first discriminator D1, the second generator G2 and the second discriminator D2 until the generated module aging path P i (t) and overall aging trend prediction All met the predetermined requirements.

[0064] Optionally, the S6 includes:

[0065] S61, deploy the first generator G1 and the second generator G2 in the trained two-layer generative adversarial network model to the real-time prediction system, and obtain and input the current operating parameter set P in real time r (t) and the current execution sequence v r1 ,v r2 ,…,v rm To the first generator G1;

[0066] S62: The first generator G1 generates a feature data set F based on the real-time input r (t) Generate the current module aging path P r,i (t):

[0067] P r,i (t) = G1(F r (t),{v r1 ,vr2 ,…,v rm},θ1);

[0068] Among them, θ1 is the parameter set of the first generator, and the real-time input feature data set F r (t) include current historical aging patterns and status scores;

[0069] S63, the generated current module aging path P r,i (t) and the current execution sequence v r1 ,v r2 ,…,v rm Input the second generator G2 to generate the overall aging trend prediction T of the current storage chip r,chip (t):

[0070] T r,chip (t) = G2(P r,i (t),{v r1 ,v r2 ,…,v rm},θ2);

[0071] Among them, θ2 is the parameter set of the second generator, and the generated aging trend prediction reflects the overall aging process of the storage chip in the current state;

[0072] S64. Predict T based on aging trend r,chip (t) Generate failure time estimate E of storage chip fail :

[0073]

[0074] Among them, T threshold is the preset aging threshold, is the rate of change of the current aging trend, and the failure time is estimated to be E fail It indicates the estimated time point when the storage chip reaches the failure threshold if the current aging trend is maintained.

[0075] A storage chip aging prediction device based on topological sorting, comprising:

[0076] The data acquisition module is used to collect the operating parameter sets of each module in the storage chip in real time, including temperature data, voltage data, operating frequency data and load data, and transmit the data to the data processing module;

[0077] The data processing module is used to receive and process the operating parameter set provided by the data acquisition module, perform data cleaning, normalization processing and feature extraction, generate the cleaned operating parameter set and feature data set, and transmit them to the prediction module;

[0078] A dependency analysis module is used to construct a dependency graph between modules in the storage chip based on the generated operating parameter set, and to generate a module execution sequence by applying a topological sorting algorithm to determine the priority and dependency order between modules;

[0079] A prediction module, integrating a two-layer generative adversarial network model, including a first generator and a second generator, is used to generate module aging paths and overall aging trend predictions of storage chips based on feature data sets and module execution sequences, and to predict and generate failure time estimates;

[0080] The early warning module is used to trigger the early warning mechanism when the aging trend forecast reaches the preset aging threshold, reminding the user to perform preventive maintenance or data backup.

[0081] The beneficial effects of the present invention are:

[0082] (1) The present invention utilizes a topological sorting algorithm to effectively solve the problem of complex dependency analysis between modules within a storage chip. By establishing a multi-level dependency graph and performing topological sorting on this basis, the key modules within the chip can be accurately identified and sorted. The aging of key modules often has a significant impact on the entire system. Traditional methods fail to fully consider this dependency. The present invention uses topological sorting to ensure that the prediction model accurately reflects the priority and dependency between modules, thereby significantly improving the accuracy of aging prediction, which is of great significance for preventing systemic failures and extending chip life.

[0083] (2) The present invention integrates a two-layer generative adversarial network model. By constructing a two-layer generator and a discriminator, it realizes efficient prediction of the aging path and overall aging trend of the storage chip. The first generator generates the module aging path based on the input feature data set and optimizes it through the feedback of the first discriminator to ensure that the generated aging path is highly matched with the actual dependency relationship of the module. The second generator uses the aging path generated by the first generator and the module execution sequence obtained by topological sorting to generate the aging trend prediction of the overall storage chip. The two-layer network structure can not only capture the aging pattern of individual modules more accurately, but also effectively reflect the aging process of the entire chip.

[0084] (3) The present invention places special emphasis on real-time performance in algorithm design. By acquiring the operating parameters of the storage chip in real time and inputting them into the trained two-layer generative adversarial network model, the prediction results can be dynamically adjusted to ensure the synchronization of aging trend prediction and actual operating conditions, thereby greatly improving the health monitoring effect of the storage chip and enabling the system to identify potential failure risks at an early stage and trigger the early warning mechanism in a timely manner. Traditional methods usually rely on static data and are difficult to cope with dynamic changes in actual operations. The real-time data integration and analysis mechanism of the present invention effectively overcomes this limitation. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0086] Figure 1 A flowchart of a storage chip aging prediction method and device based on topological sorting proposed by the present invention;

[0087] Figure 2 A schematic diagram of a double-layer generative adversarial network model in a storage chip aging prediction method and device based on topological sorting proposed by the present invention. DETAILED DESCRIPTION

[0088] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0089] refer to Figure 1-2 , a storage chip aging prediction method based on topological sorting, comprising the following steps:

[0090] S1. Obtain temperature data, voltage data, operating frequency data and load data of each module in the storage chip and construct an operating parameter set;

[0091] S2. Establish a dependency graph between modules inside the storage chip based on the operating parameter set. The dependency graph is a directed acyclic graph, in which the nodes of the dependency graph represent the modules and the edges represent the dependency relationships between the modules.

[0092] S3. Apply topological sorting to sort the dependency graph and generate an execution sequence of the modules. The execution sequence reflects the priority and dependency order between the modules.

[0093] S4, performing data preprocessing and feature extraction on the operating parameter set to generate a feature data set, the feature data set including the historical aging mode, current state and mutual influence of each module;

[0094] S5. Construct a two-layer generative adversarial network model:

[0095] The first generator generates a module aging path based on an input feature data set. The module aging path refers to the execution sequence of the module during the generation process to ensure that the generated path matches the module dependency relationship;

[0096] A first discriminator, which evaluates the authenticity of the module aging path generated by the first generator and performs feedback optimization on the first generator;

[0097] A second generator generates an aging trend prediction of the overall storage chip based on the module aging path and execution sequence generated by the first generator, and the execution sequence is used to guide the second generator to identify and prioritize key modules that have a significant impact on the overall aging trend;

[0098] a second discriminator, which evaluates the reliability of the aging trend prediction generated by the second generator and performs feedback optimization on the second generator;

[0099] S6. Apply the trained two-layer generative adversarial network model to the real-time acquired operation parameter set, combine the execution sequence and topological sorting results, predict the overall aging trend of the storage chip, and generate failure time estimation;

[0100] S7. When the aging trend reaches a preset threshold, an early warning mechanism is triggered, including instructions to prompt the user to perform preventive maintenance or data backup.

[0101] In this implementation, S1 includes:

[0102] S11. The temperature data of each module is collected in real time through the sensor integrated in the storage chip. i (t), voltage data V i (t), working frequency data f i (t) and load data L i (t), where i represents the i-th module in the storage chip and t represents time;

[0103] S12, collect the temperature data T of each module i (t), voltage data V i (t), working frequency data f i (t) and load data L i (t) is normalized to obtain the normalized temperature data ( Voltage data Operating frequency data and load data

[0104] S13, the normalized temperature data Voltage data Operating frequency data and load data According to the time series storage, the operating parameter set P(t) of all modules of the storage chip is constructed:

[0105]

[0106] Where n is the number of modules in the storage chip.

[0107] In this implementation, S2 includes:

[0108] S21, based on the data of each module in the operating parameter set P(t), analyze the interdependence between the modules and determine the dependency weight W between the modules ij (t):

[0109]

[0110] Among them, α, β, γ and λ are weight coefficients; ∈ is the minimum constant to avoid division by zero, σ L is the standard deviation of the load difference; S ij Represents the structural similarity between module i and module j;

[0111] S22, according to the dependency weight W ij (t), construct a multi-level dependency graph G k (V k ,E k ), the multi-level dependency graph is a directed acyclic graph:

[0112]

[0113] Among them, d ij Represents the physical distance or communication delay between module i and module j. By minimizing the logarithm of the total weight in the dependency graph, the dependency graph structure G at each level is determined. k (V k ,E k );

[0114] S23. A multi-level dependency graph includes at least two levels, and the nodes and edges of each level are associated by the following formula:

[0115]

[0116] Among them, φ ij represents the connection strength between module i at level k and module j at level k+1.

[0117] In this implementation, S3 includes:

[0118] S31. Multi-level dependency graph G k (V k ,E k ) Apply the topological sorting algorithm to determine the node order in each level of dependency graph and generate a preliminary module sorting sequence {v i1 ,v i2 ,…,v im}, where v ij represents the jth module in level k, and m is the number of nodes in level k;

[0119] S32, based on the preliminary module sorting sequence, according to the dependency weight W ij (t) and physical distance or communication delay d ij , optimize and adjust the order of the preliminary module sorting sequence to form the final module execution sequence v i1 ',v i2 ',,v im '}, the optimization criterion is to minimize the global dependency delay, that is:

[0120]

[0121] Among them, δ(v ij '→v il ') is an indicator function, when the module v ij 'In module v il 'When executed before, δ takes the value of 1, otherwise it takes the value of 0.

[0122] In this implementation, S4 includes:

[0123] S41, perform data cleaning and normalization processing on the operating parameter set P(t), remove abnormal data points and noise data, and obtain the cleaned operating parameter set P c (t);

[0124] S42, based on the operating parameter set P after cleaning c (t), extract the historical aging pattern H of each module i (t), including temperature aging model Voltage aging mode Operating frequency aging mode and load aging mode

[0125]

[0126] in, represents the normalized operating parameters of module i at time point τ, α X is the weight coefficient of the corresponding parameter, which is used to measure the influence of different parameters on aging. X is the historical attenuation coefficient, which is used to control the influence of earlier data on the current aging pattern. It means that at time t, a certain operating parameter X i The historical aging pattern of module i is formed;

[0127] S43, by analyzing historical aging patterns i (t) and the current state Calculate the aging trend and status score S of each module i (t):

[0128]

[0129] Among them, w X is the weight of different aging modes, which is used to reflect the importance of each aging mode in the module aging trend, ∈ is the minimum constant to avoid division by zero;

[0130] S44, combining the mutual influence relationship between modules, using the dependency weight W ij (t) Modify the state score and generate the feature data set F(t):

[0131]

[0132] In this implementation, S5 includes:

[0133] S51, constructing a two-layer generative adversarial network model, which includes a first generator, a first discriminator, a second generator and a second discriminator, wherein the input and output of each generator and discriminator are respectively used to generate module aging paths and overall aging trend predictions, and to evaluate and optimize authenticity and reliability;

[0134] S52, the first generator G1, input is the feature data set and the module execution sequence, generates the module aging path P i (t), the dependencies between integrated modules during the generation process:

[0135]

[0136] Among them, T i (t) is the target aging path, L dep (P i (t),W ij (t)) is the dependency loss function, which reflects the matching degree of module dependency, and λ1 is the coefficient that controls the influence of dependency loss;

[0137] S53, the first discriminator D1, the input is the module aging path P generated by the first generator G1 i (t) and the actual aging path T i (t), judge the authenticity of the generated path through the binary classification task and generate the loss function:

[0138]

[0139] S54, the second generator G2, inputs the module aging path P generated by the first generator G1 i (t) and execution sequence to generate the aging trend prediction of the overall storage chip The generation process identifies and prioritizes key modules that have a significant impact on the overall aging trend:

[0140]

[0141] Among them, T real (t) is the overall aging trend of the target, is the key module impact loss function, which reflects the influence of the key module on the overall aging trend, and λ2 is the coefficient controlling the loss influence of the key module;

[0142] S55, second discriminator D2, input is the overall aging trend prediction generated by the second generator G2 The real aging trend real (t), the reliability of the generated trend is judged through the binary classification task, and the loss function is generated:

[0143]

[0144] S56, repeatedly iteratively train the first generator G1, the first discriminator D1, the second generator G2 and the second discriminator D2 until the generated module aging path P i (t) and overall aging trend prediction All met the predetermined requirements.

[0145] In this implementation, S6 includes:

[0146] S61, deploy the first generator G1 and the second generator G2 in the trained two-layer generative adversarial network model to the real-time prediction system, and obtain and input the current operating parameter set P in real time r (t) and the current execution sequence v r1 ,v r2 ,…,v rm To the first generator G1;

[0147] S62: The first generator G1 generates a feature data set F based on the real-time input r (t) Generate the current module aging path P r,i (t):

[0148] P r,i (t) = G1(F r (t),{v r1 ,v r2 ,…,v rm},θ1);

[0149] Among them, θ1 is the parameter set of the first generator, and the real-time input feature data set F r (t) include current historical aging patterns and status scores;

[0150] S63, the generated current module aging path P r,i(t) and the current execution sequence v r1 ,v r2 ,…,v rm Input the second generator G2 to generate the overall aging trend prediction T of the current storage chip r,chip (t):

[0151] T r,chip (t) = G2(P r,i (t),{v r1 ,v r2 ,…,v rm},θ2);

[0152] Among them, θ2 is the parameter set of the second generator, and the generated aging trend prediction reflects the overall aging process of the storage chip in the current state;

[0153] S64. Predict T based on aging trend r,chip (t) Generate failure time estimate E of storage chip fail :

[0154]

[0155] Among them, T threshold is the preset aging threshold, is the rate of change of the current aging trend, and the failure time is estimated to be E fail It indicates the estimated time point when the storage chip reaches the failure threshold if the current aging trend is maintained.

[0156] A storage chip aging prediction device based on topological sorting, comprising:

[0157] The data acquisition module is used to collect the operating parameter sets of each module in the storage chip in real time, including temperature data, voltage data, operating frequency data and load data, and transmit the data to the data processing module;

[0158] The data processing module is used to receive and process the operating parameter set provided by the data acquisition module, perform data cleaning, normalization processing and feature extraction, generate the cleaned operating parameter set and feature data set, and transmit them to the prediction module;

[0159] A dependency analysis module is used to construct a dependency graph between modules in the storage chip based on the generated operating parameter set, and to generate a module execution sequence by applying a topological sorting algorithm to determine the priority and dependency order between modules;

[0160] A prediction module, integrating a two-layer generative adversarial network model, including a first generator and a second generator, is used to generate module aging paths and overall aging trend predictions of storage chips based on feature data sets and module execution sequences, and to predict and generate failure time estimates;

[0161] The early warning module is used to trigger the early warning mechanism when the aging trend forecast reaches the preset aging threshold, reminding the user to perform preventive maintenance or data backup.

[0162] Embodiment 1:

[0163] The present invention is applied in a world-leading data center operating company, which is responsible for managing hundreds of large data centers and providing cloud storage and data processing services to global customers. The company recently faced a serious problem: as storage chips run under high load conditions for a long time, aging problems gradually emerge, resulting in an increasing risk of system failure. In the past 6 months, the failure rate of storage chips in data centers due to aging problems has increased significantly, especially during the high temperatures in summer.

[0164] During the working day of Example 1, the data center monitoring system detected abnormal fluctuations in the temperature data, voltage data, operating frequency data, and load data of a group of key storage chips. This group of storage chips is located in one of the busiest server clusters in the data center and mainly processes real-time data requests from customers in the East China region.

[0165] During the peak load period from 2:30 to 4:00 a.m. on July 15, 2023, the monitoring system recorded that the temperature of one of the storage chips (numbered SC-0789) continued to rise from 70°C to 85°C, and the operating frequency also began to become unstable. At this time, the system automatically called the storage chip aging prediction algorithm based on topological sorting. Through real-time data processing and analysis, the system generated the aging path of chip SC-0789 and predicted that it might fail within the next 72 hours.

[0166] According to the analysis results of the algorithm, the system generated the first fault warning at 4:10 am on July 15, 2023. The warning content showed that the failure probability of SC-0789 had reached 85%, and hardware failure was expected to occur around 3:00 am on July 17, 2023. The warning information was immediately sent to the network administrator, who quickly took measures to reduce the load and optimize the heat dissipation, reducing the temperature and load of the chip, successfully delaying the aging process, and avoiding potential system crashes.

[0167] In order to verify the effectiveness of the method of the present invention, we compared the aging prediction results of the storage chip SC-0789 within 6 months using the traditional method and the method of the present invention. The following Table 1 is the detailed comparison data, which respectively shows the prediction error, warning time and failure rate under different conditions.

[0168] Table 1 Prediction error, warning time and failure rate of the traditional method and the method of the present invention under different conditions

[0169]

[0170]

[0171] Traditional method: The predicted failure time has a large error, especially when the load and temperature fluctuate greatly, the error can be up to 3-4 hours, the warning time is short, usually within 2-6 hours before the failure occurs, the administrator has insufficient time to respond, and the failure rate is relatively high. The average failure rate during the test period was 13.5%.

[0172] The method of the present invention has a small error in predicting failure time, which is usually within 1 hour, and the error is 0 in multiple tests. The warning time is greatly advanced, usually within 48 hours before the failure occurs, giving the administrator sufficient time to take preventive measures, and the failure rate is significantly reduced, with an average failure rate of only 2.75%.

[0173] It can be seen from the above data that the method of the present invention shows significant advantages in the storage chip aging prediction and early warning mechanism, especially in terms of prediction accuracy, early warning timeliness and reduction of failure rate. This embodiment effectively verifies the feasibility and superiority of the storage chip aging prediction method and device based on topological sorting, provides reliable aging prediction technical support for similar data center operators, and ensures the long-term stable operation of the system.

[0174] The present invention utilizes a topological sorting algorithm to effectively solve the problem of complex dependency analysis between modules within a storage chip. By establishing a multi-level dependency graph and performing topological sorting on this basis, the key modules within the chip can be accurately identified and sorted. The aging of key modules often has a significant impact on the entire system. Traditional methods fail to fully consider this dependency. The present invention, through topological sorting, can ensure that the prediction model accurately reflects the priority and dependency between modules, thereby significantly improving the accuracy of aging prediction, which is of great significance for preventing systemic failures and extending chip life.

[0175] The present invention integrates a two-layer generative adversarial network model. By constructing a two-layer generator and a discriminator, it realizes the efficient prediction of the aging path and the overall aging trend of the storage chip. The first generator generates the module aging path based on the input feature data set, and optimizes it through the feedback of the first discriminator to ensure that the generated aging path is highly matched with the actual dependency relationship of the module. The second generator uses the aging path generated by the first generator and the module execution sequence obtained by topological sorting to generate the aging trend prediction of the overall storage chip. The two-layer network structure can not only capture the aging mode of individual modules more accurately, but also effectively reflect the aging process of the entire chip.

[0176] The present invention places special emphasis on real-time performance in algorithm design. By acquiring the operating parameters of the storage chip in real time and inputting them into the trained two-layer generative adversarial network model, the prediction results can be dynamically adjusted to ensure the synchronization of aging trend prediction and actual operating conditions, thereby greatly improving the health monitoring effect of the storage chip. The system can identify potential failure risks at an early stage and trigger the early warning mechanism in a timely manner. Traditional methods usually rely on static data and are difficult to cope with dynamic changes in actual operations. The real-time data integration and analysis mechanism of the present invention effectively overcomes this limitation.

[0177] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A storage chip aging prediction method based on topological sorting, characterized in that: The steps include: S1. Obtain temperature data, voltage data, operating frequency data and load data of each module in the storage chip and construct an operating parameter set; S2. Establish a dependency graph between modules inside the storage chip based on the operating parameter set. The dependency graph is a directed acyclic graph, in which the nodes of the dependency graph represent the modules and the edges represent the dependency relationships between the modules. S3. Apply topological sorting to sort the dependency graph and generate an execution sequence of the modules. The execution sequence reflects the priority and dependency order between the modules. S4, performing data preprocessing and feature extraction on the operating parameter set to generate a feature data set, the feature data set including the historical aging mode, current state and mutual influence of each module; S5. Construct a two-layer generative adversarial network model: The first generator generates a module aging path based on an input feature data set. The module aging path refers to the execution sequence of the module during the generation process to ensure that the generated path matches the module dependency relationship; A first discriminator, which evaluates the authenticity of the module aging path generated by the first generator and performs feedback optimization on the first generator; A second generator generates an aging trend prediction of the overall storage chip based on the module aging path and execution sequence generated by the first generator, and the execution sequence is used to guide the second generator to identify and prioritize key modules that have a significant impact on the overall aging trend; a second discriminator, which evaluates the reliability of the aging trend prediction generated by the second generator and performs feedback optimization on the second generator; S6. Apply the trained two-layer generative adversarial network model to the real-time acquired operation parameter set, combine the execution sequence and topological sorting results, predict the overall aging trend of the storage chip, and generate failure time estimation; S7. When the aging trend reaches a preset threshold, an early warning mechanism is triggered, including instructions to prompt the user to perform preventive maintenance or data backup.

2. The storage chip aging prediction method based on topological sorting according to claim 1, characterized in that: The S1 includes: S11. The temperature data of each module is collected in real time through the sensor integrated in the storage chip. i (t), voltage data V i (t), working frequency data f i (t) and load data L i (t), where i represents the i-th module in the storage chip and t represents time; S12, collect the temperature data T of each module i (t), voltage data V i (t), working frequency data f i (t) and load data L i (t) is normalized to obtain normalized temperature data Voltage data Operating frequency data and load data S13, the normalized temperature data Voltage data Operating frequency data and load data According to the time series storage, the operating parameter set P(t) of all modules of the storage chip is constructed: Where n is the number of modules in the storage chip.

3. The storage chip aging prediction method based on topological sorting according to claim 1, characterized in that: The S2 includes: S21, based on the data of each module in the operating parameter set P(t), analyze the interdependence between the modules and determine the dependency weight W between the modules ij (t): Among them, α, β, γ and λ are weight coefficients; ε is the minimum constant to avoid division by zero, σ L is the standard deviation of the load difference; S ij Represents the structural similarity between module i and module j; S22, according to the dependency weight W ij (t), construct a multi-level dependency graph G k (V k ,E k ), the multi-level dependency graph is a directed acyclic graph: Among them, d ij Represents the physical distance or communication delay between module i and module j. By minimizing the logarithm of the total weight in the dependency graph, the dependency graph structure G at each level is determined. k (V k ,E k ); S23. A multi-level dependency graph includes at least two levels, and the nodes and edges of each level are associated by the following formula: Among them, φ ij represents the connection strength between module i at level k and module j at level k+1.

4. The storage chip aging prediction method based on topological sorting according to claim 1, characterized in that: The S3 includes: S31. Multi-level dependency graph G k (V k ,E k ) Apply the topological sorting algorithm to determine the order of nodes in the dependency graph at each level and generate a preliminary module sorting sequence {v i1 ,v i2 ,…,v im }, where v ij represents the jth module in level k, and m is the number of nodes in level k; S32, based on the preliminary module sorting sequence, according to the dependency weight W ij (t) and physical distance or communication delay d ij , optimize and adjust the order of the preliminary module sorting sequence to form the final module execution sequence {v i1 ',v i2 ',...,v im '}, the optimization criterion is to minimize the global dependency delay, that is: Among them, δ(v ij '→v il ') is an indicator function, when the module v ij 'In module v il 'When executed before, δ takes the value of 1, otherwise it takes the value of 0.

5. The storage chip aging prediction method based on topological sorting according to claim 1, characterized in that: The S4 includes: S41, perform data cleaning and normalization processing on the operating parameter set P(t), remove abnormal data points and noise data, and obtain the cleaned operating parameter set P c (t); S42, based on the operating parameter set P after cleaning c (t), extract the historical aging pattern H of each module i (t), including temperature aging model Voltage aging mode Operating frequency aging mode and load aging mode in, represents the normalized operating parameters of module i at time point τ, α X is the weight coefficient of the corresponding parameter, which is used to measure the influence of different parameters on aging. X is the historical attenuation coefficient, which is used to control the influence of earlier data on the current aging pattern. It means that at time t, a certain operating parameter X i The historical aging pattern of module i is formed; S43, by analyzing historical aging patterns i (t) and the current state Calculate the aging trend and status score S of each module i (t): Among them, w X is the weight of different aging modes, which is used to reflect the importance of each aging mode in the module aging trend, and ε is the minimum constant to avoid division by zero; S44, combining the mutual influence relationship between modules, using the dependency weight W ij (t) Modify the state score and generate the feature data set F(t):

6. The storage chip aging prediction method based on topological sorting according to claim 1, characterized in that: The S5 includes: S51, constructing a two-layer generative adversarial network model, which includes a first generator, a first discriminator, a second generator and a second discriminator, wherein the input and output of each generator and discriminator are respectively used to generate module aging paths and overall aging trend predictions, and to evaluate and optimize authenticity and reliability; S52, the first generator G1, input is the feature data set and the module execution sequence, generates the module aging path P i (t), the dependencies between integrated modules during the generation process: Among them, T i (t) is the target aging path, L dep (P i (t),W ij (t)) is the dependency loss function, which reflects the matching degree of module dependency, and λ1 is the coefficient that controls the influence of dependency loss; S53, the first discriminator D1, the input is the module aging path P generated by the first generator G1 i (t) and the actual aging path T i (t), judge the authenticity of the generated path through the binary classification task and generate the loss function: S54, the second generator G2, inputs the module aging path P generated by the first generator G1 i (t) and execution sequence to generate the aging trend prediction of the overall storage chip The generation process identifies and prioritizes key modules that have a significant impact on the overall aging trend: Among them, T real (t) is the overall aging trend of the target, is the key module impact loss function, which reflects the influence of the key module on the overall aging trend, and λ2 is the coefficient controlling the impact of key module loss; S55, second discriminator D2, input is the overall aging trend prediction generated by the second generator G2 The real aging trend real (t), the reliability of the generated trend is judged through the binary classification task, and the loss function is generated: S56, repeatedly iteratively train the first generator G1, the first discriminator D1, the second generator G2 and the second discriminator D2 until the generated module aging path P i (t) and overall aging trend prediction All met the predetermined requirements.

7. The storage chip aging prediction method based on topological sorting according to claim 1, characterized in that: The S6 includes: S61, deploy the first generator G1 and the second generator G2 in the trained two-layer generative adversarial network model to the real-time prediction system, and obtain and input the current operating parameter set P in real time r (t) and the current execution sequence v r1 ,v r2 ,…,v rm To the first generator G1; S62: The first generator G1 generates a feature data set F based on the real-time input r (t) Generate the current module aging path P r,i (t): P r,i (t)=G1(F r (t),{v r1 ,v r2 ,…,v rm },θ1); Among them, θ1 is the parameter set of the first generator, and the real-time input feature data set F r (t) include current historical aging patterns and status scores; S63, the generated current module aging path P r,i (t) and the current execution sequence v r1 ,v r2 ,…,v rm Input the second generator G2 to generate the overall aging trend prediction T of the current storage chip r,chip (t): T r,chip (t)=G2(P r,i (t),{v r1 ,v r2 ,…,v rm },θ2); Among them, θ2 is the parameter set of the second generator, and the generated aging trend prediction reflects the overall aging process of the storage chip in the current state; S64. Predict T based on aging trend r,chip (t) Generate failure time estimate E of storage chip fail : Among them, T threshold is the preset aging threshold, is the rate of change of the current aging trend, and the failure time is estimated to be E fail It indicates the estimated time point when the storage chip reaches the failure threshold if the current aging trend is maintained.

8. A storage chip aging prediction device based on topological sorting, characterized in that: include: The data acquisition module is used to collect the operating parameter sets of each module in the storage chip in real time, including temperature data, voltage data, operating frequency data and load data, and transmit the data to the data processing module; The data processing module is used to receive and process the operating parameter set provided by the data acquisition module, perform data cleaning, normalization processing and feature extraction, generate the cleaned operating parameter set and feature data set, and transmit them to the prediction module; A dependency analysis module is used to construct a dependency graph between modules in the storage chip based on the generated operating parameter set, and to generate a module execution sequence by applying a topological sorting algorithm to determine the priority and dependency order between modules; A prediction module, integrating a two-layer generative adversarial network model, including a first generator and a second generator, is used to generate module aging paths and overall aging trend predictions of storage chips based on feature data sets and module execution sequences, and to predict and generate failure time estimates; The early warning module is used to trigger the early warning mechanism when the aging trend forecast reaches the preset aging threshold, reminding the user to perform preventive maintenance or data backup.

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