Wafer backside thinning method based on BSI process

Abstract

The present invention discloses a wafer backside thinning method based on a BSI process, belonging to the field of semiconductor manufacturing technology, and comprising the following steps: (1) providing a wafer to be thinned; (2) thinning the wafer to a target thickness by adopting a thinning process; (3) forming an oxide layer on the surface of the thinned wafer and performing a chemical mechanical flattening treatment; (4) laying a silicene layer on the flattened wafer thinned surface and then performing an annealing treatment. Based on the existing thinning process method, the present invention performs surface oxidation and flattening treatment on the back side of the wafer thinned to the target thickness, and then lays a silicene layer and performs annealing to improve the flatness of the back side of the wafer after completing the wafer backside thinning process.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a wafer backside thinning method based on a BSI process. Background Art

[0002] CMOS Image Sensor (CIS) is a sensor that can convert the color and brightness of light captured by the lens into electronic signals and transmit them to the processor. Therefore, the image sensor plays the role of the "eyes" of mobile devices such as smartphones or tablets. In recent years, with the rise of virtual reality (VR), augmented reality (AR), and autonomous driving, CIS technology has become a key technology for Industry 4.0. It is expected that CIS technology will not only serve as the "eyes" of the device, but will also have further development in terms of functionality.

[0003] Early CIS product pixels used a front-illuminated (FSI) structure, which placed an optical structure on a circuit based on a CMOS process. This technology is suitable for most CIS solutions with a pixel size of 1.12μm and above, and is widely used in mobile devices, CCTV, dashcams, digital SLR cameras, automotive sensors and other products. As for the FSI structure, this structure is more susceptible to diffraction due to the influence of the metal wiring layer in the lower circuit. Even if the FSI pixel size is reduced, the area covered by the metal remains unchanged. Therefore, the area through which light passes becomes smaller, and the diffraction phenomenon is enhanced, resulting in color mixing in the image. For this reason, a back-illuminated (BSI) process has been proposed to eliminate metal interference by flipping the wafer to utilize its back side; as for BSI technology, all circuit parts are first made on one side of the wafer, and then the wafer is flipped upside down to create an optical structure that can collect light on the back side, which can eliminate the interference caused by the metal lines in the FSI, and the space for light to pass is larger under the condition of the same size pixel, thereby improving quantum efficiency.

[0004] The process steps of the BSI structure are relatively complicated. One of the steps is to flip and bond the device wafer with the photodiode and then thin it on the back side. Conventional thinning processes include mechanical grinding, dry etching, wet etching and plasma etching, which can easily produce a damaged layer and residual stress on the back side of the wafer, resulting in reduced strength of the wafer, easy adhesion of fragments or impurities, and warping of the edge of the wafer due to the presence of residual stress, making the back side of the wafer rough after thinning, which in turn leads to problems such as uneven conductive layer and short circuit of the protective layer in the later process of packaging. Summary of the invention

[0005] In view of the above problems, the present invention provides a wafer back side thinning method based on the BSI process.

[0006] The purpose of the present invention is achieved by the following technical solutions:

[0007] A wafer backside thinning method based on a BSI process comprises the following steps:

[0008] (1) Providing a wafer to be thinned;

[0009] (2) thinning the wafer to a target thickness using a thinning process;

[0010] (3) forming an oxide layer on the thinned wafer surface and performing chemical mechanical planarization treatment;

[0011] (4) After laying a silicene layer on the flattened wafer surface, annealing is performed.

[0012] In some preferred embodiments, the wafer in step (1) is a product of bonding a first wafer having a photodiode circuit structure and metal wiring formed thereon and a second wafer serving as a support structure.

[0013] In some preferred embodiments, the thinning process is mechanical grinding, dry etching, wet etching or plasma etching; the thinning rate of the thinning process is 0.1-10µm / min.

[0014] In some preferred embodiments, the target thickness of step (2) is 80-150 µm.

[0015] In some preferred embodiments, the oxide layer in step (3) is formed by plasma oxidation or thermal oxygen oxidation.

[0016] In some preferred embodiments, the gas medium of the plasma oxidation and the thermal oxygen oxidation includes one or both of oxygen and ozone.

[0017] In some preferred embodiments, the thickness of the oxide layer in step (3) is 10-5000 angstroms.

[0018] In some preferred embodiments, the method for preparing the silicene layer comprises the following steps:

[0019] First, a graphene layer is grown on the surface of a metal substrate material by epitaxial growth, and then silicon atoms are deposited on the graphene surface. Finally, silicon atoms are inserted between the graphene and the metal substrate by annealing and diffused at the interface to form a continuous film. The silicene layer is then peeled off and laid on the flattened wafer thinning surface.

[0020] In some preferred embodiments, in the method for preparing the silicene layer, the annealing temperature is 200-400° C., and the annealing time is 1-4 hours.

[0021] In some preferred embodiments, the annealing temperature in step (4) is 100-400° C., and the annealing time is 1-3 h.

[0022] The beneficial effects of the present invention are:

[0023] In view of the problem of high wafer roughness caused by the BSI process wafer thinning method in the prior art, the present invention provides a wafer back side thinning method based on the BSI process. On the basis of the existing thinning process method, the back side of the wafer thinned to a target thickness is subjected to surface oxidation and flattening treatment, and then a silicene layer is laid and annealed to improve the flatness of the back side of the wafer that has completed the wafer back side thinning process. Specifically, the present invention uses an atomically flat metal single crystal surface as a substrate to epitaxially grow a graphene layer, and inserts silicon atoms thereunder to construct silicene, so as to obtain an ultra-thin silicene layer with high flatness. After annealing treatment, the graphene is ablated and vaporized, and the silicon atoms are combined with the oxide layer to form a flat and dense thinned surface. At the same time, the annealing treatment can also eliminate the residual stress generated by thinning. DETAILED DESCRIPTION

[0024] The present invention is further described in conjunction with the following examples.

[0025] Example 1

[0026] A wafer backside thinning method based on a BSI process comprises the following steps:

[0027] (1) Providing a wafer to be thinned;

[0028] (2) thinning the wafer to a target thickness using a thinning process;

[0029] (3) forming an oxide layer on the thinned wafer surface and performing chemical mechanical planarization treatment;

[0030] (4) After laying a silicene layer on the flattened wafer thinned surface, an annealing treatment is performed; the annealing temperature is 300° C. and the annealing time is 1.5 hours;

[0031] The wafer in step (1) is a product of bonding a first wafer having a photodiode circuit structure and metal wiring formed thereon and a second wafer serving as a support structure;

[0032] The thinning process is mechanical grinding, dry etching, wet etching or plasma etching; the thinning rate of the thinning process is 5µm / min;

[0033] The target thickness in step (2) is 100 µm;

[0034] The oxide layer in step (3) is formed by ozone plasma oxidation, and the thickness of the oxide layer is 100 angstroms;

[0035] The silicene layer is prepared by using a single crystal Ru (0001) surface as a substrate through a silicon intercalation process of epitaxially grown graphene, and the preparation method thereof comprises the following steps:

[0036] First, a graphene layer is grown on the surface of a single crystal Ru (0001) substrate material by epitaxial growth, and then silicon atoms are deposited on the graphene surface. Finally, silicon atoms are inserted between the graphene and the metal substrate by annealing, and diffused at the interface to form a continuous film, and the silicene layer is obtained by peeling, and then laid on the flattened wafer thinning surface; the annealing temperature is 300° C., and the annealing time is 1 hour;

[0037] The thickness of the silicene layer is 100 angstroms.

[0038] The maximum roughness of the wafer thinning surface described in this embodiment (five-point measurement method) is 6.8 nm.

[0039] Example 2

[0040] A wafer backside thinning method based on a BSI process comprises the following steps:

[0041] (1) Providing a wafer to be thinned;

[0042] (2) thinning the wafer to a target thickness using a thinning process;

[0043] (3) forming an oxide layer on the thinned wafer surface and performing chemical mechanical planarization treatment;

[0044] (4) After laying a silicene layer on the flattened wafer thinned surface, an annealing treatment is performed; the annealing temperature is 300° C. and the annealing time is 1.5 hours;

[0045] The wafer in step (1) is a product of bonding a first wafer having a photodiode circuit structure and metal wiring formed thereon and a second wafer serving as a support structure;

[0046] The thinning process is mechanical grinding, dry etching, wet etching or plasma etching; the thinning rate of the thinning process is 5µm / min;

[0047] The target thickness in step (2) is 100 µm;

[0048] The oxide layer in step (3) is formed by ozone plasma oxidation, and the thickness of the oxide layer is 100 angstroms;

[0049] The silicene layer is prepared by using a single crystal Ru (0001) surface as a substrate through a silicon intercalation process of epitaxially grown graphene, and the preparation method thereof comprises the following steps:

[0050] First, a graphene layer is grown on the surface of a single crystal Ru (0001) substrate material by epitaxial growth, and then silicon atoms are deposited on the graphene surface. Finally, silicon atoms are inserted between the graphene and the metal substrate by annealing, and diffused at the interface to form a continuous film, and the silicene layer is obtained by peeling, and then laid on the flattened wafer thinning surface; the annealing temperature is 300° C., and the annealing time is 1 hour;

[0051] The thickness of the silicene layer is 500 angstroms.

[0052] The maximum roughness of the wafer thinning surface described in this embodiment (five-point measurement method) is 7.6 nm.

[0053] Example 3

[0054] A wafer backside thinning method based on a BSI process comprises the following steps:

[0055] (1) Providing a wafer to be thinned;

[0056] (2) thinning the wafer to a target thickness using a thinning process;

[0057] (3) forming an oxide layer on the thinned wafer surface and performing chemical mechanical planarization treatment;

[0058] (4) After laying a silicene layer on the flattened wafer thinned surface, an annealing treatment is performed; the annealing temperature is 300° C. and the annealing time is 1.5 hours;

[0059] The wafer in step (1) is a product of bonding a first wafer having a photodiode circuit structure and metal wiring formed thereon and a second wafer serving as a support structure;

[0060] The thinning process is mechanical grinding, dry etching, wet etching or plasma etching; the thinning rate of the thinning process is 5µm / min;

[0061] The target thickness in step (2) is 100 µm;

[0062] The oxide layer in step (3) is formed by ozone plasma oxidation, and the thickness of the oxide layer is 100 angstroms;

[0063] The method for preparing the silicene layer comprises the following steps:

[0064] First, epitaxially grow the silicene layer on the surface of the substrate material Ag (111), then peel off the generated silicene layer, and then transfer and lay the peeled silicene layer on the flattened wafer thinning surface;

[0065] The thickness of the silicene layer is 100 angstroms.

[0066] The maximum roughness of the wafer thinning surface described in this embodiment (five-point measurement method) is 79.5 nm.

[0067] Example 4

[0068] A wafer backside thinning method based on a BSI process comprises the following steps:

[0069] (1) Providing a wafer to be thinned;

[0070] (2) thinning the wafer to a target thickness using a thinning process;

[0071] (3) forming an oxide layer on the thinned wafer surface and performing chemical mechanical planarization treatment;

[0072] (4) After laying a silicene layer on the flattened wafer thinning surface, an annealing treatment is performed; the annealing temperature is 100° C. and the annealing time is 3 hours;

[0073] The wafer in step (1) is a product of bonding a first wafer having a photodiode circuit structure and metal wiring formed thereon and a second wafer serving as a support structure;

[0074] The thinning process is mechanical grinding, dry etching, wet etching or plasma etching; the thinning rate of the thinning process is 5µm / min;

[0075] The target thickness in step (2) is 100 µm;

[0076] The oxide layer in step (3) is formed by ozone plasma oxidation, and the thickness of the oxide layer is 10 angstroms;

[0077] The silicene layer is prepared by using a single crystal Ru (0001) surface as a substrate through a silicon intercalation process of epitaxially grown graphene, and the preparation method thereof comprises the following steps:

[0078] First, a graphene layer is grown on the surface of a single crystal Ru (0001) substrate material by epitaxial growth, and then silicon atoms are deposited on the graphene surface. Finally, silicon atoms are inserted between the graphene and the metal substrate by annealing, and diffused at the interface to form a continuous film, and the silicene layer is obtained by peeling, and then laid on the flattened wafer thinning surface; the annealing temperature is 400°C, and the annealing time is 1h;

[0079] The thickness of the silicene layer is 100 angstroms.

[0080] The maximum roughness of the wafer thinning surface described in this embodiment (five-point measurement method) is 10.2 nm.

[0081] Example 5

[0082] A wafer backside thinning method based on a BSI process comprises the following steps:

[0083] (1) Providing a wafer to be thinned;

[0084] (2) thinning the wafer to a target thickness using a thinning process;

[0085] (3) forming an oxide layer on the thinned wafer surface and performing chemical mechanical planarization treatment;

[0086] (4) After laying a silicene layer on the flattened wafer thinned surface, an annealing treatment is performed; the annealing temperature is 400° C. and the annealing time is 1 hour;

[0087] The wafer in step (1) is a product of bonding a first wafer having a photodiode circuit structure and metal wiring formed thereon and a second wafer serving as a support structure;

[0088] The thinning process is mechanical grinding, dry etching, wet etching or plasma etching; the thinning rate of the thinning process is 5µm / min;

[0089] The target thickness in step (2) is 100 µm;

[0090] The oxide layer in step (3) is formed by ozone plasma oxidation, and the thickness of the oxide layer is 5000 angstroms;

[0091] The silicene layer is prepared by using a single crystal Ru (0001) surface as a substrate through a silicon intercalation process of epitaxially grown graphene, and the preparation method thereof comprises the following steps:

[0092] First, a graphene layer is grown on the surface of a single crystal Ru (0001) substrate material by epitaxial growth, and then silicon atoms are deposited on the graphene surface. Finally, silicon atoms are inserted between the graphene and the metal substrate by annealing, and diffused at the interface to form a continuous film, and the silicene layer is obtained by peeling, and then laid on the flattened wafer thinning surface; the annealing temperature is 200°C, and the annealing time is 4h;

[0093] The thickness of the silicene layer is 100 angstroms.

[0094] The maximum roughness of the wafer thinning surface described in this embodiment (five-point measurement method) is 12.4 nm.

[0095] Comparative Example

[0096] A wafer backside thinning method based on a BSI process comprises the following steps:

[0097] (1) Providing a wafer to be thinned;

[0098] (2) thinning the wafer to a target thickness using a thinning process;

[0099] (3) forming an oxide layer on the thinned wafer surface and performing chemical mechanical planarization treatment;

[0100] (4) annealing the flattened wafer thinned surface; the annealing temperature is 300° C. and the annealing time is 1.5 h;

[0101] The wafer in step (1) is a product of bonding a first wafer having a photodiode circuit structure and metal wiring formed thereon and a second wafer serving as a support structure;

[0102] The thinning process is mechanical grinding, dry etching, wet etching or plasma etching; the thinning rate of the thinning process is 5µm / min;

[0103] The target thickness in step (2) is 100 µm;

[0104] In step (3), the oxide layer is formed by ozone plasma oxidation, and the thickness of the oxide layer is 100 angstroms.

[0105] The maximum roughness of the wafer thinning surface described in this embodiment (five-point measurement method) is 116.5 nm.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention, rather than to limit the scope of protection of the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the essence and scope of the technical solution of the present invention.

Claims

1. A wafer backside thinning method based on BSI process, characterized in that: The following steps are involved: (1) Providing a wafer to be thinned; (2) thinning the wafer to a target thickness using a thinning process; (3) forming an oxide layer on the thinned wafer surface and performing chemical mechanical planarization treatment; (4) After laying a silicene layer on the flattened wafer thinning surface, an annealing treatment is performed.

2. The method for wafer backside thinning based on BSI process according to claim 1, characterized in that: The wafer in step (1) is the product of bonding a first wafer having a photodiode circuit structure and metal wiring formed thereon and a second wafer serving as a supporting structure.

3. The method for wafer backside thinning based on BSI process according to claim 1, characterized in that: The thinning process is mechanical grinding, dry etching, and wet etching; the thinning rate of the thinning process is 0.1-10 μm / min.

4. The method for wafer backside thinning based on BSI process according to claim 1, characterized in that: The target thickness of step (2) is 80-150 μm.

5. The method for wafer backside thinning based on BSI process according to claim 1, characterized in that: The oxide layer in step (3) is formed by plasma oxidation or thermal oxygen oxidation.

6. The method for wafer backside thinning based on BSI process according to claim 5, characterized in that: The gas medium of the plasma oxidation and the thermal oxygen oxidation includes one or both of oxygen and ozone.

7. The method for wafer backside thinning based on BSI process according to claim 1, characterized in that: The thickness of the oxide layer in step (3) is between 10 and 5000 angstroms.

8. The method for wafer backside thinning based on BSI process according to claim 1, characterized in that: The method for preparing the silicene layer comprises the following steps: First, a graphene layer is grown on the surface of a metal substrate material by epitaxial growth, and then silicon atoms are deposited on the graphene surface. Finally, silicon atoms are inserted between the graphene and the metal substrate by annealing and diffused at the interface to form a continuous film. The silicene layer is then peeled off and laid on the flattened wafer thinning surface.

9. The method for wafer backside thinning based on BSI process according to claim 8, characterized in that: In the method for preparing the silicene layer, the annealing temperature is 200-400° C. and the annealing time is 1-4 hours.

10. The method for wafer backside thinning based on BSI process according to claim 1, characterized in that: The annealing temperature in step (4) is 100-400° C. and the annealing time is 1-3 hours.