ESD protection circuit

Abstract

The present invention discloses an ESD protection circuit, belonging to the field of integrated circuits. In order to solve the problem of weak ESD protection capability of the I / O terminal against backflow, the ESD protection circuit of the present invention has the source of the first PMOS tube connected to VDD, the drain of the first NMOS tube connected to the drain of the first PMOS tube; the source of the first NMOS tube connected to VSS, the drain of the first NMOS tube leading to the I / O terminal; the I / O terminal is connected to the anode of the first diode, the I / O terminal is also connected to the cathode of the second diode, the anode of the second diode is connected to VSS; the first end of the first module is connected to VDD, the second end of the first module is connected to the cathode of the first diode; the second end of the first module is also connected to the first end of the second module, the second end of the second module is connected to VSS; the first module includes a third diode or a first resistor; the second module includes a second resistor, a first capacitor, an inverter and a second NMOS tube. The present invention avoids the leakage problem of the I / O terminal in the prior art when VDD is not powered on.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an ESD protection circuit. Background Art

[0002] Static electricity is widely present in nature. Electrostatic Discharge (ESD) protection is an important part of the electronics industry and semiconductor field. Every year, electronic products are damaged due to static electricity, accounting for about 30% of the total damage rate of electronic products. Therefore, a good ESD protection circuit is an important task in the field of electronic circuits.

[0003] Figure 1 This is an ESD protection circuit diagram in the prior art. Among them, the P-channel Metal Oxide Semiconductor (PMOS) tube P0 and the N-channel Metal Oxide Semiconductor (NMOS) tube N0 belong to the driving level, and the diode D1 and the diode D2 are ESD protection devices. When a positive electrostatic voltage appears at the input-output (I / O) port relative to the common ground voltage (Voltage Source-to-Source, VSS) terminal, the electrostatic current flows from D1 through the device working voltage (Voltage Drain-to-Drain, VDD) terminal, and then passes through the power clamp between the VDD terminal and the VSS terminal, and flows into the VSS terminal. The voltage at the I / O terminal is clamped to a lower voltage value, and the PMOS tube P0 and the NMOS tube N0 are protected and will not be broken down by static electricity.

[0004] When a negative electrostatic voltage appears at the I / O terminal relative to the VSS terminal, the electrostatic current flows through the diode D2 from the VSS terminal to the I / O terminal, and the PMOS tube P0 and the NMOS tube N0 are protected from being broken down by static electricity.

[0005] However, the prior art has the following defects: when there is voltage at the I / O terminal and no voltage at the VDD terminal, current will flow from the I / O terminal to the VDD terminal, causing the I / O terminal voltage to be too low and unable to meet the index requirements.

[0006] Figure 2 This is another ESD protection circuit diagram in the prior art, in which a grounded gate NMOS (GGNMOS) tube N1 is designed to cut off the leakage channel of the PMOS tube P0 and the NMOS tube N0.

[0007] When a positive electrostatic voltage appears at the I / O terminal, the GGNMOS tube N1 is turned on, and the electrostatic current flows from the I / O terminal through the GGNMOS tube N1 to the VSS terminal. Conversely, the current flows into the drain through the substrate of the GGNMOS tube N1.

[0008] The disadvantage of this solution is that when a positive electrostatic voltage appears at the I / O terminal, the voltage when the current passes through the drain to the source of the GGNMOS tube N1 is relatively high, between 5V and 8V, which may cause the PMOS tube P0 and the NMOS tube N0 to burn out. Summary of the invention

[0009] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

[0010] An ESD protection circuit, wherein the source of a first PMOS tube is connected to VDD, the drain of a first NMOS tube is connected to the drain of the first PMOS tube; the source of the first NMOS tube is connected to VSS, and the drain of the first NMOS tube leads to an I / O terminal; the I / O terminal is connected to the anode of a first diode, and the I / O terminal is also connected to the cathode of a second diode, and the anode of the second diode is connected to VSS; the first end of a first module is connected to VDD, and the second end of the first module is connected to the cathode of the first diode; the second end of the first module is also connected to the first end of the second module, and the second end of the second module is connected to VSS; in addition, the first module includes a third diode or a first resistor; the second module includes a second resistor, a first capacitor, an inverter and a second NMOS tube.

[0011] Further, when the first module includes a third diode: an anode of the third diode serves as a first end of the first module and is connected to VDD; and a cathode of the third diode serves as a second end of the first module and is connected to a cathode of the first diode.

[0012] Further, when the first module includes a first resistor: the first end of the first resistor serves as the first end of the first module and is connected to VDD; the second end of the first resistor serves as the second end of the first module and is connected to the cathode of the first diode.

[0013] Furthermore, the second module has the following circuit structure: the first end of the second resistor and the drain of the second NMOS tube are connected together and serve as the first end of the second module; the second end of the second resistor is connected to the first end of the first capacitor and the input end of the inverter, and the output end of the inverter is connected to the gate of the second NMOS tube; the second end of the first capacitor and the source of the second NMOS tube are connected together and serve as the second end of the second module.

[0014] Furthermore, when a positive electrostatic voltage appears at the I / O terminal, the electrostatic current flows into VSS through the first diode and the second module.

[0015] Furthermore, when a negative electrostatic voltage appears at the I / O terminal, an electrostatic current flows from VSS through the second diode and into the I / O terminal.

[0016] Furthermore, when VDD is not powered on and the I / O terminal is powered on, the second module is in a shutdown state.

[0017] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0018] (1) A new ESD protection circuit structure is proposed to solve the problem of weak ESD protection capability of the I / O terminal.

[0019] (2) Avoid the leakage problem of the I / O terminal in the prior art when VDD is not powered.

[0020] (3) Overcome the problem of weak ESD protection capability in the existing technology. Under the same ESD protection capability, the circuit speed is higher and the power consumption is lower.

[0021] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is an ESD protection circuit diagram in the prior art;

[0023] Figure 2 is another ESD protection circuit diagram in the prior art;

[0024] Figure 3 is a schematic diagram of an ESD protection circuit of the present invention;

[0025] Figure 4 is the ESD protection circuit diagram of the present invention;

[0026] Figure 5 This is a first working schematic diagram of the ESD protection circuit of the present invention;

[0027] Figure 6 This is a second working schematic diagram of the ESD protection circuit of the present invention.

[0028] The meanings of the English marks in the attached figure are: P0: first PMOS tube; N0: first NMOS tube; N1: GGNMOS tube; N2: second NMOS tube; D1: first diode; D2: second diode; D3: third diode; VDD: device operating voltage; VDD1: first voltage; VSS: common ground terminal voltage; IO: input and output; R1: first resistor; R2: second resistor; C1: first capacitor. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0031] Figure 3 Schematic diagram of the ESD protection circuit of the present invention. The source of the first PMOS tube P0 is connected to VDD, the drain of the first NMOS tube N0 is connected to the drain of the first PMOS tube P0, and the source of the first NMOS tube N0 is connected to VSS. In the present invention, the first PMOS tube P0 and the first NMOS tube N0 are used as driving-level circuits, which can be devices at any position that need to be protected by ESD. Therefore, the present invention does not limit the gate access conditions of the first PMOS tube P0 and the gate access conditions of the first NMOS tube N0.

[0032] In addition, an I / O terminal is led out from the drain of the first NMOS transistor N0, the I / O terminal is connected to the anode of the first diode D1, and the I / O terminal is also connected to the cathode of the second diode D2. The anode of the second diode D2 is connected to VSS.

[0033] Furthermore, the first end of the first module is connected to VDD, the second end of the first module is connected to the cathode of the first diode D1, the second end of the first module is also connected to the first end of the second module, and the second end of the second module is connected to VSS.

[0034] In the present invention, after VDD passes through the first module, a first voltage VDD1 is obtained. The second end of the first module outputs the first voltage VDD1.

[0035] Figure 4 This is the ESD protection circuit diagram of the present invention. Figure 3 Based on the ESD protection circuit shown, the present invention further defines the circuit implementation of the first module and the second module.

[0036] For example, in the first module, a third diode D3 is included. The anode of the third diode D3 is used as the first end of the first module and connected to VDD; the cathode of the third diode D3 is used as the second end of the first module and connected to the cathode of the first diode D1.

[0037] In this example, when working normally, the third diode D3 in the first module provides a bias from VDD to the first voltage VDD1, ensuring the reverse bias of the first diode D1 and the reverse bias of the second diode D2, without leakage, and the circuit works normally.

[0038] When VDD is not powered on and the I / O terminal is powered, the second module is in a shut-off state and no current flows through it. The third diode D3 in the first module is in a reverse biased state and no current flows through it.

[0039] When there is a positive electrostatic voltage at the I / O terminal relative to VSS, the electrostatic current flows into VSS through the first diode D1 and the second module. At this time, the third diode D3 in the first module is in an off state.

[0040] For example, in the first module, a first resistor R1 is included. The first end of the first resistor R1 is used as the first end of the first module and connected to VDD; the second end of the first resistor R1 is used as the second end of the first module and connected to the cathode of the first diode D1.

[0041] In this example, when working normally, the first resistor R1 in the first module provides a voltage bias from VDD to the first voltage VDD1, ensuring the reverse bias of the first diode D1, and no leakage occurs. The second diode D2 is also in a reverse bias state, and the circuit works normally.

[0042] When VDD is not powered on and the I / O terminal is powered, the second module is in a shutdown state and no current flows.

[0043] When there is a positive electrostatic voltage at the I / O terminal relative to VSS, the electrostatic current flows into VSS through the first diode D1 and the second module. At this time, since the first resistor R1 in the first module has a large resistance, only a small current flows.

[0044] Further, in the second module, the first end of the second module is connected to the first voltage VDD1. The second module includes a second resistor R2, a first capacitor C1, an inverter and a second NMOS transistor N2. The first end of the second resistor R2 and the drain of the second NMOS transistor N2 are connected together and serve as the first end of the second module.

[0045] The second end of the second resistor R2 is connected to the first end of the first capacitor C1 and the input end of the inverter. The output end of the inverter is connected to the gate of the second NMOS transistor N2.

[0046] The second end of the first capacitor C1 and the source of the second NMOS transistor N2 are connected together and serve as the second end of the second module.

[0047] When the circuit operates normally, the value of the first voltage VDD1 is equal to the value of VDD, the first diode D1 is reverse biased, and no leakage occurs.

[0048] Figure 5 This is a first working schematic diagram of the ESD protection circuit of the present invention. When a positive electrostatic voltage appears at the I / O terminal, the electrostatic current flows into VSS through the first diode D1 and the second module.

[0049] Figure 6 This is a second working schematic diagram of the ESD protection circuit of the present invention. When a negative electrostatic voltage appears at the I / O terminal, the electrostatic current flows from VSS through the second diode D2 and flows into the I / O terminal.

[0050] If the I / O terminal is at a high level and the VDD terminal is not powered on and thus VDD is at a low level, the first module blocks the current from flowing from the first terminal of the second module to the VDD terminal. The second module cuts off the path of the current flowing from the first terminal of the second module to VSS. Therefore, there is no forward leakage path on the first diode D1.

[0051] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0052] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An ESD protection circuit, characterized in that: The source of the first PMOS tube is connected to VDD, and the drain of the first NMOS tube is connected to the drain of the first PMOS tube; The source of the first NMOS tube is connected to VSS, and the drain of the first NMOS tube is connected to the I / O terminal; The I / O terminal is connected to the anode of the first diode, and the I / O terminal is also connected to the cathode of the second diode, and the anode of the second diode is connected to VSS; A first terminal of the first module is connected to VDD, and a second terminal of the first module is connected to the cathode of the first diode; The second end of the first module is also connected to the first end of the second module, and the second end of the second module is connected to VSS; in addition, The first module includes a third diode or a first resistor; The second module includes a second resistor, a first capacitor, an inverter and a second NMOS tube.

2. The ESD protection circuit according to claim 1, characterized in that: When the first module includes a third diode: The anode of the third diode serves as the first terminal of the first module and is connected to VDD; The cathode of the third diode serves as the second end of the first module and is connected to the cathode of the first diode.

3. The ESD protection circuit according to claim 1, characterized in that: When the first module includes a first resistor: The first end of the first resistor is used as the first end of the first module and is connected to VDD; The second end of the first resistor serves as the second end of the first module and is connected to the cathode of the first diode.

4. The ESD protection circuit according to claim 2 or 3, characterized in that: The second module has the following circuit structure: The first end of the second resistor and the drain of the second NMOS tube are connected together and serve as the first end of the second module; The second end of the second resistor is connected to the first end of the first capacitor and the input end of the inverter, and the output end of the inverter is connected to the gate of the second NMOS tube; The second end of the first capacitor and the source of the second NMOS tube are connected together and serve as the second end of the second module.

5. The ESD protection circuit according to claim 4, characterized in that: When a positive electrostatic voltage appears at the I / O terminal, the electrostatic current flows into VSS through the first diode and the second module.

6. The ESD protection circuit according to claim 5, characterized in that: When a negative electrostatic voltage appears at the I / O terminal, an electrostatic current flows from VSS through the second diode and into the I / O terminal.

7. The ESD protection circuit according to claim 6, characterized in that: When VDD is not powered on and the I / O terminal is powered on, the second module is in the off state.

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