Graph calculation-oriented priority perception processing method and hardware accelerator

Abstract

The invention relates to a graph calculation-oriented priority perception processing method and a hardware accelerator, and the method comprises the steps: receiving graph data to be processed, traversing each vertex in the graph data, carrying out the priority prediction of all adjacent edges of each vertex, and carrying out the reordering of all adjacent edges according to a priority prediction result; according to a reordering result of all the adjacent edges of each vertex, performing hierarchical storage on the adjacent edges; and simultaneously scheduling a plurality of vertexes to carry out parallel computing, sequentially and preferentially scheduling adjacent edges in each vertex from a high-priority storage region to carry out task processing, and if the processed vertex state is converged to a final result, skipping all the remaining non-traversed adjacent edges of the current vertex. Compared with the prior art, the method has the advantages that the redundancy calculation problem can be reduced to a great extent, the calculation efficiency is improved and the graph calculation processing speed is accelerated on the premise of keeping high parallelism, and meanwhile, the software and hardware collaborative design scheme has high throughput rate and optimizes the performance.

Description

Technical Field

[0001] The present invention relates to the field of graph processing technology, and in particular to a priority-aware processing method and hardware accelerator for graph computing. Background Art

[0002] Graph computing, or graph processing technology, plays a vital role in applications such as social network analysis, recommendation systems, network security, and traffic flow optimization. For example, in social network analysis, finding the most influential nodes or key social groups often relies on graph computing technology. In the process of large-scale graph computing, the sparsity and irregularity of graph data will lead to inefficiency of traditional computing methods, especially in terms of memory access and computing resource utilization. Therefore, it is very important to use customized data flow and hardware architecture to optimize graph computing.

[0003] Common graph computing applications in customized hardware accelerators usually use the GAS model to unify their execution modes. The GAS (Gather, Scatter, Apply) model is an abstract computing model that describes the three stages of graph data processing: the Gather stage collects and aggregates attribute values ​​from all incoming vertices, the Apply stage updates the attribute value of the current vertex with the aggregated value, and the Scatter stage propagates the updated value to all outgoing vertices. Through this unified GAS model, common graph algorithms such as PageRank and BFS can achieve efficient parallel computing in large-scale graph data processing, optimize memory access and computing resource utilization, and improve algorithm execution efficiency.

[0004] Field-Programmable Gate Array (FPGA) is a highly flexible and reconfigurable integrated circuit that allows users to program and configure it through hardware description languages ​​​​(such as VHDL or Verilog). FPGA consists of programmable logic blocks, input and output blocks, and reconfigurable interconnection networks, supporting a variety of circuit designs from simple logic gates to complex system-level functions. Its reconfigurable characteristics make FPGA play an important role in hardware acceleration, signal processing, embedded systems, artificial intelligence, and rapid prototyping. FPGA has been widely used in the research and design of customized graph computing accelerators.

[0005] There are already works for accelerating graph computing in the patents currently disclosed, such as the invention with publication number CN109003222A, which discloses an asynchronous high-energy-efficiency graph computing accelerator. According to its disclosed content, it includes a data preprocessing module, a data transmission module and a data processing module connected in sequence, wherein the data processing module includes a storage module and a computing module. According to the specific implementation steps disclosed, first, the data preprocessing module divides the graph into multiple Batch Row Vectors. Then, the PCIe DMA in the transmission module transmits one Batch Row Vector to the FPGA onboard DDR each time, and then the AXIDMA in the transmission module transmits it to the on-chip computing module. The calculation of on-chip data is divided into three stages: StreamEdges, Reduce, and Update. StreamEdges traverses the on-chip edge data, reads the state value of the source vertex, and updates the temporary state value of the target vertex. Reduce is responsible for collecting the state value components from different source vertices on the same target vertex, and determines the method of aggregating these components according to the specific algorithm, such as the aggregation operation for the PageRank algorithm is addition, and the aggregation operation for the BFS algorithm is to take the minimum value. Update receives the aggregate value from the Reduce stage and executes the update function to modify the attribute value of the vertex. The above invention accelerates the convergence speed of the graph algorithm by using asynchronous computing, and reduces the power consumption and energy consumption of the system based on the customized accelerator of the hardware platform.

[0006] However, the accelerated graph computing work represented by the above publication number CN109003222A, whether software or hardware, assumes that all edge data have the same contribution to the convergence of the graph algorithm, so these works all process the edge data uniformly and indiscriminately. In actual application scenarios, the edge data that actually contributes to the convergence of the graph algorithm often only accounts for a very small part of all edge data. At this time, the graph computing accelerator represented by the above publication number CN109003222A faces the unavoidable problem of redundant computing, which seriously wastes memory bandwidth and computing resources and reduces the update execution efficiency of the accelerator. Summary of the invention

[0007] The purpose of the present invention is to provide a priority-aware processing method and hardware accelerator for graph computing in order to overcome the defect of redundant computing in the accelerator of the above-mentioned prior art.

[0008] The purpose of the present invention can be achieved by the following technical solutions:

[0009] A priority-aware processing method for graph computing includes the following steps:

[0010] Receive the graph data to be processed, traverse each vertex in the graph data, make priority predictions for all adjacent edges of each vertex, and reorder all adjacent edges according to the priority prediction results;

[0011] According to the reordering results of all adjacent edges of each vertex, each adjacent edge is stored hierarchically;

[0012] Multiple vertices are scheduled for parallel calculation at the same time, and the adjacent edges of each vertex are scheduled from the high-priority storage area for task processing. If the processed vertex state converges to the final result, the processing task of the current vertex is terminated and all the adjacent edges of the current vertex that have not been traversed are skipped.

[0013] Furthermore, the reordering process includes: obtaining all adjacent edges and adjacent points of the vertex, and calculating the priority of each adjacent edge according to the weight value of the adjacent edge and the degree of the adjacent point;

[0014] Traverse all adjacent edges of the vertex, rearrange the adjacent edges in descending order according to their priorities, and obtain the reordered adjacency list.

[0015] Furthermore, the hierarchical storage process includes: selecting the first K adjacent edges from the reordering results of each vertex according to a preset boundary value K and storing them in a high priority edge area, and storing the remaining adjacent edges in a low priority edge area;

[0016] If the number of adjacent edges of a vertex is less than the boundary value K, placeholders are filled in the corresponding high-priority edge area.

[0017] Furthermore, in the process of processing tasks on the adjacent edges of a vertex, the high-priority edge area corresponding to the vertex is first accessed and all the adjacent edges therein are traversed to perform calculation tasks to update the vertex state. If the vertex state converges to the final result, the processing task of the current vertex is terminated and the remaining low-priority edge areas are skipped; if it does not converge to the final result, it waits for rescheduling to access the calculation of the adjacent edges in the low-priority edge area.

[0018] The present invention also provides a hardware accelerator for graph computing, including a processor, a scheduler, a thermal value manager, a memory efficiency-aware merger, an on-chip interconnect network, a high-speed internal memory, and an external memory;

[0019] The external memory is used to store graph structure information and edge data required by the processor;

[0020] The processor is used to process graph computing tasks in parallel with multiple basic processing units, each basic processing unit is allocated a corresponding storage space for storing vertex data in a high-speed internal memory, each basic processing unit reads vertex data from the corresponding storage space, performs priority prediction on all adjacent edges of the vertex, and executes the corresponding graph computing task according to the instructions of the scheduler; each basic processing unit also filters out high-degree vertices whose degrees exceed a screening threshold from the corresponding storage space and transmits them to the thermal value manager;

[0021] The high-speed internal memory is used to allocate storage space to each basic processing unit and store vertex values, intermediate calculation results and edge offset memory addresses;

[0022] The thermal value manager is used to read corresponding data from the high-speed internal memory according to the received high-degree vertices, so as to realize independent management and calculation of the high-degree vertices;

[0023] The scheduler is used to allocate a high priority edge region and a low priority edge region to each processing unit, perform hierarchical storage according to the priority of adjacent edges, and preferentially schedule vertex tasks from the high priority edge region;

[0024] The on-chip interconnect network is used for data interaction and communication between different processing units in the processor;

[0025] The memory efficiency-aware merger is used to read edge data from external memory and pass it to the processor.

[0026] Furthermore, the processing process of the scheduler is specifically as follows:

[0027] The scheduler allocates a high-priority edge region, a low-priority edge region, a high-priority buffer, and a low-priority buffer to each processing unit, reorders all adjacent edges according to the priority prediction result of each processing unit, and stores them hierarchically into the high-priority edge region and the low-priority edge region;

[0028] Receive the vertex ID transmitted by the processor, check whether the vertex ID is scheduled for the first time in the current iteration round, if so, assign a unique and fixed global workload ID to the vertex and store it in the corresponding high priority buffer; if not, store the vertex in the corresponding low priority buffer;

[0029] In the processing stage, the vertex tasks to be processed are read out from the high-priority buffer in a first-in-first-out manner, and the corresponding high-priority edges are read from the high-priority edge area according to the current vertex ID, and sent to the corresponding processing unit to execute the graph calculation task; if the vertex state obtained by the processing unit converges to the final result, the low-priority edge area is not read, and the processing of the current vertex is completed;

[0030] The vertices of the low-priority buffer are scheduled out in sequence, and the memory address offset of the low-priority edge in the corresponding low-priority edge area is read according to the vertex ID. During the processing, the memory address offsets of multiple low-priority edges are collected and the requests are packaged and sent to the merger, which uniformly accesses the low-priority edges stored in the external memory through the merger.

[0031] Furthermore, the processing process of the merger is specifically as follows:

[0032] Select the request with the smallest memory address, add a cache line size to the request address as the address threshold, traverse all received request addresses, and if the request address is less than the address threshold, merge the request with the request with the smallest memory address to access the external memory.

[0033] Furthermore, the high-priority edge region is a storage region composed of high-speed read-write hardware storage devices, and the low-priority edge region is a storage region composed of low-speed read-write hardware storage devices.

[0034] Furthermore, the processing process of the thermal value manager is specifically as follows:

[0035] According to the vertex ID of the high-degree vertex transmitted by the processor, the corresponding vertex attribute value is read from the high-speed internal memory and stored and backed up;

[0036] After each round of calculation starts, the data corresponding to the high-degree vertex is sent to the basic processing unit for vertex update tasks. After the high-degree vertex is updated, coarse-grained data synchronization is performed to back up the corresponding high-degree vertex data. Whenever a vertex update task is generated subsequently, the thermal value manager checks whether the data to be read by the vertex update task hits the stored data in the thermal value manager. If so, the high-degree vertex data is returned directly to the basic processing unit; otherwise, it is forwarded to the on-chip network interface for routing to access the corresponding data.

[0037] Furthermore, the processor divides the multiple basic processing units into a coarse-grained Tile processing group, and the multiple basic processing units in each Tile processing group share the backup data in the thermal value manager, while the data between different Tile processing groups are not shared.

[0038] Compared with the prior art, the present invention has the following advantages:

[0039] (1) The present invention utilizes a priority-aware edge processing mode to process edge tasks of multiple vertices in parallel, thus significantly improving the throughput of graph computing. Compared with the prior art solutions, the present invention introduces a vertex-granular edge serial execution mode to prioritize edge tasks that contribute significantly to the final result, thereby reducing unnecessary computing load. By prioritizing edge tasks, it ensures that computing resources are concentrated on the most critical edge tasks, avoiding unnecessary computing waste.

[0040] (2) The present invention adopts a memory-efficient hierarchical layout to store high-priority edges and low-priority edges separately. This layout design allows the system to preferentially obtain data of high-priority edges when accessing memory, thereby reducing redundant data access within the cache line and improving the efficiency of memory access.

[0041] (3) The present invention proposes a hot value manager to alleviate the congestion problem of the on-chip network. The manager manages the frequently accessed vertex data through distributed cache, reduces the data contention of high-priority vertices in the on-chip network, and thus improves the efficiency of parallel processing. Its design can ensure efficient allocation and access to data among multiple processing units, reducing pipeline stalls and delays caused by data contention.

[0042] (4) To further optimize memory access efficiency, the present invention introduces a memory-aware merger. The merger can dynamically merge memory requests of low-priority edges, thereby significantly reducing memory bandwidth consumption. By reducing frequent access to memory, the overall system performance and energy efficiency are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic diagram of a flow chart of a priority-aware processing method for graph computing provided in an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of an edge serial execution mode at a vertex granularity provided in an embodiment of the present invention;

[0045] Figure 3 A schematic diagram of a hierarchical memory subsystem provided in an embodiment of the present invention;

[0046] Figure 4 A schematic diagram of the structure of a hardware accelerator for graph computing provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0048] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0050] It should be understood that these terms may be interpreted or replaced differently by a person of ordinary skill in the technical field described in the present invention. For example, the "module" or "unit" mentioned in the present invention may be a component implemented by hardware or a functional module implemented by software or firmware; similarly, "connection" or "coupling" may be a physical connection or a logical connection or a functional connection. Unless otherwise specified, the use of these terms should be based on the overall understanding of the invention and should not be limited to a specific definition.

[0051] The following first introduces, explains and discusses the terms in the present invention.

[0052] IESM: Intra-Edge-Sequential Model (IESM) is an edge serial execution mode proposed by the present invention. The specific behavior is to schedule an edge of multiple vertices to perform execution calculation tasks of multiple vertices at the same time;

[0053] HVM: Hot-Value Manager (HVM) is a hot value manager designed by the present invention, which is used to store and centrally manage multiple frequently accessed vertex data separately, thereby reducing data contention and pipeline stagnation problems caused by data access conflicts between different processing units;

[0054] On-chip cache: On-chip cache refers to internal high-speed memory integrated in the processor or dedicated hardware accelerator. In this invention, it refers to the scratchpad memory (SPM) in the FPGA. SPM is a small high-speed memory used to store temporary data. It can be directly connected to the logic unit and provide high-bandwidth and low-latency data access capabilities. It is used to store instructions and data currently needed by the processor, reducing the latency of accessing external memory;

[0055] PE: The smallest basic processing unit (Processing Element) in the present invention is an independent module for performing basic calculations. In graph computing applications, it usually performs calculations generated during vertex update, such as addition, multiplication, and comparison operations. Each PE can independently process data computing tasks. In the present invention, a multi-PE parallel architecture is adopted, which can process multiple computing tasks at the same time, thereby accelerating the graph computing execution process;

[0056] Tile: It is used to divide multiple PEs into a coarse-grained PE group. The PEs in each tile share the same communication channel connected to the external memory and the memory area in the same external memory. This division is used to improve data reuse and locality;

[0057] NoC: Network-on-Chip is an interconnection architecture for communication between different modules. The design purpose of NoC is to improve the communication bottleneck between components in the System-on-Chip (SoC) by providing efficient, scalable and low-latency data transmission solutions. In the present invention, NoC is used to connect different PEs to achieve data interaction across PEs;

[0058] HyperX: HyperX is a high-performance network topology that is commonly used in large-scale parallel computing systems and data center networks. It is an improved multi-level network topology designed to provide high bandwidth, low latency, and high fault tolerance. The HyperX topology is designed to reduce the network diameter and increase bandwidth while maintaining a certain scalability. The NoC implementation in the present invention adopts the HyperX architecture.

[0059] Example 1

[0060] like Figure 1 As shown, this embodiment provides a priority-aware processing method for graph computing, comprising the following steps:

[0061] S1: Use vertex-level parallel granularity to schedule multiple vertices at the same time and schedule only one adjacent edge for each vertex to process tasks. When the vertex state converges to the final result, the current vertex calculation task is terminated immediately, and the remaining edges that have not been traversed are skipped, thereby reducing redundant and invalid calculations;

[0062] The specific process of scheduling is:

[0063] In the preprocessing stage, a graph data storage format is constructed to evenly distribute fixed and mutually orthogonal vertex data to each processing unit and store them in the local cache of the processing unit;

[0064] The processing unit schedules an active vertex from its own vertex data cache in a first-in-first-out order and reads an edge of the active vertex at the same time. Multiple processing units perform edge calculation tasks for different vertices at the same time;

[0065] The processing unit will access the values ​​of the required adjacent vertices through the on-chip network for remote data access;

[0066] When a vertex completes an edge calculation task and converges to the final result, the traversal behavior is terminated, the remaining edges are skipped, and the results are written back.

[0067] S2: Predict a priority for all edges of each vertex through the prediction function, and reorder all edges according to this priority to prioritize edges that are more likely to contribute to vertex updates, accelerate vertex convergence, and skip more edges;

[0068] The specific process of sorting is:

[0069] In the preprocessing stage, each vertex is traversed, and for each vertex, all its adjacent edges and connected adjacent points are traversed, and the priority of each edge is calculated according to the weight value of the edge and the degree of its connected adjacent points;

[0070] For each vertex, traverse all its edges and reorder the entire adjacency list in descending order of priority of each edge to form a new adjacency list.

[0071] S3: All edges of each vertex are stored hierarchically to reduce the edge data redundancy problem in cache lines caused by coarse-grained memory access patterns;

[0072] The specific methods of hierarchical storage are as follows:

[0073] When reordering the adjacency list, according to the preset boundary value K, the first K edges are selected for each vertex according to the priority value to form a high priority edge region, and the remaining edges form a low priority edge region;

[0074] For vertices whose number of adjacent edges is less than K, placeholders are filled in the corresponding high-priority areas so that the high-priority edge areas of all vertices form a regular memory layout in the memory space.

[0075] When processing tasks on the adjacent edges of a vertex, first visit the high-priority edge region corresponding to the vertex and traverse all the adjacent edges therein to perform calculation tasks to update the vertex state. If the vertex state converges to the final result, terminate the processing task of the current vertex and skip the remaining low-priority edge regions; if it does not converge to the final result, the vertex is sent to the active vertex set and waits for scheduling to access its low-priority edge region again.

[0076] The specific process of the above graph computing execution mode is introduced in detail below.

[0077] Step 1: Construct a graph data storage format, evenly distribute fixed and mutually orthogonal vertex data to each processing unit, and store them in the local cache of the processing unit. Mutually orthogonal means that the data of two vertices are independent and unrelated.

[0078] Specifically, for building the graph data storage format, the graph data is stored according to the algorithm requirements. Preferably, the csr or csc format is used to store data to reduce the reading and writing burden. For vertex allocation, for PE0-n, the vertex sequence number is operated with a remainder n, and the PE is allocated according to the remainder obtained. For example, if the remainder is 3, it is allocated to the PE with sequence number 3. Finally, the vertex data is stored in the local cache of the PE.

[0079] Step 2: The processing unit schedules an active vertex from the vertex data cache and reads an edge of the active vertex at the same time. Multiple processing units perform edge calculation tasks in parallel.

[0080] Specifically, PE reads active vertices v from the local cache in a first-in-first-out order, and reads required edges from the hierarchical storage according to the edge calculation status of the active points, that is, whether the edge to be read is a high priority and in which buffer. All PEs read edges in parallel and perform edge calculation tasks. Specifically, BFS needs to determine the value size between the adjacent point and the destination point.

[0081] Step 3: The processing unit performs remote data access to the values ​​of the required adjacent vertices through the on-chip network;

[0082] Specifically, the processing unit sends a read request for the adjacent vertex value through the HyperX interconnection network and receives data, and starts computing the task after receiving the data. Specifically, the interconnection network performs a modulo operation on the sequence number to determine the destination based on the adjacent points in the processing unit read request and the active points in the return data request. Preferably, the waiting time is reduced by sending the task in advance.

[0083] Step 4: Determine whether the vertex is converged, write back the converged vertices, and return the active point set for the non-converged vertices;

[0084] Specifically, when a vertex completes an edge calculation task, it is determined whether the vertex has converged. Specifically, for the BFS algorithm, if the synchronous execution mode is used, as long as it is updated, it means convergence. If the vertex has converged to the final result, the vertex traversal behavior is terminated, all the remaining unnecessary edges are skipped, and the latest result of the vertex is written back to the local cache of the processing unit that stores its vertex value. If the vertex has not converged to the final result, the edges that the vertex has completed are recorded and written back to the active point set.

[0085] Step 5: Traverse each vertex, traverse all its adjacent edges and connected adjacent points for each vertex, and calculate the priority of each edge based on the weight value of the edge and the degree of its connected adjacent points;

[0086] Specifically, for each edge e of point v, its priority value is calculated using formula (1).

[0087] Priority(e)=Deg(u)+λ×Wei(e) (1)

[0088] Where u is the adjacent vertex corresponding to point v on edge e, Deg(u) represents the degree of point u, that is, the sum of the number of outgoing edges and the number of incoming edges of point u, Wei(e) is the weight of edge e, which is 0 in an unweighted graph, and λ is a scaling factor that can be adjusted according to the graph or algorithm.

[0089] Specifically, for each vertex v's adjacency list n(v), traverse the adjacency list n(v), calculate the priority value of each edge e therein using formula (1) and store it.

[0090] Step 6: For each vertex, traverse all its edges and rearrange them in descending order according to the priority of each edge;

[0091] Specifically, for each vertex v's adjacency list n(v), traverse the adjacency list n(v), read the priority value calculated in step 5 for each edge e therein, and sort the edges in n(v) according to the priority value. It should be noted that only the edges inside n(v) are sorted in descending order, and the edges between different vertices are not sorted in descending order. After the sorting is completed, it is stored in a hierarchical storage structure.

[0092] Step 7: For each point in the adjacent edge table, select the first K edges with the highest priority and store them in the high priority storage area;

[0093] Specifically, Figure 3As shown in the figure, the adjacent edge table of each point has been reordered at this time, and the edge with a smaller sequence number has a higher priority. Therefore, it is only necessary to intercept the first K elements starting from sequence number 0 in the adjacent edge table of each point to meet the requirement. The K value is preset by the user and is usually a small integer value.

[0094] Specifically, the high priority storage area refers to a storage area composed of high-speed read and write hardware storage devices, which has a corresponding description in the hardware implementation steps.

[0095] Preferably, for any vertex u, if the number of edges in its adjacent edge table is less than the value K, in order to facilitate the indexing and burst read operations of high-priority edges, K elements are still stored in the high-priority cache. At this time, the first several elements of these K elements are all outgoing edge neighbors of point u, and the remaining elements are blank fillers.

[0096] Step 8: Add the remaining edges in the adjacent edge table of each point in step 7 to the low priority storage area;

[0097] Specifically, when the adjacent edge table of each point has been reordered, it is only necessary to intercept all elements from every K elements to the end of the table to meet the requirements.

[0098] Specifically, the low priority storage area refers to a storage area composed of low-speed read and write hardware storage devices, which has a corresponding description in the hardware implementation steps.

[0099] Specifically, if in step 7, all adjacent edges of a point have been added to the high priority storage area, then this step does not require any operation.

[0100] Example 2

[0101] like Figure 4 As shown, this embodiment provides a hardware accelerator for graph computing, including a processor, a scheduler, a thermal value manager, a memory efficiency-aware merger, an on-chip interconnect network, a high-speed internal memory, and an external memory;

[0102] The external memory is used to store the graph structure information and edge data required by the processor;

[0103] The processor is used to process graph computing tasks in parallel with multiple basic processing units. Each basic processing unit is allocated a corresponding storage space for storing vertex data in a high-speed internal memory. Each basic processing unit reads vertex data from the corresponding storage space, performs priority prediction on all adjacent edges of the vertex, and executes the corresponding graph computing task according to the instructions of the scheduler; each basic processing unit also selects high-degree vertices whose degrees exceed a screening threshold from the corresponding storage space and transmits them to the thermal value manager;

[0104] The high-speed internal memory is used to allocate storage space for each basic processing unit and store vertex values, intermediate calculation results and edge offset memory addresses;

[0105] The thermal value manager is used to read the corresponding data from the high-speed internal memory according to the received high-degree vertex, so as to realize the independent management and calculation of the high-degree vertex;

[0106] The scheduler is used to allocate a high priority edge region and a low priority edge region to each processing unit, hierarchically store the adjacent edges according to their priorities, and schedule vertex tasks preferentially from the high priority edge region;

[0107] The on-chip interconnect network is used for data interaction and communication between different processing units in the processor;

[0108] A memory efficiency-aware merger is used to read edge data from external memory and pass it to the processor.

[0109] The processing process of the scheduler is as follows:

[0110] The scheduler allocates a high-priority edge region, a low-priority edge region, a high-priority buffer, and a low-priority buffer to each processing unit, reorders all adjacent edges according to the priority prediction result of each processing unit, and stores them hierarchically into the high-priority edge region and the low-priority edge region;

[0111] Receive the vertex ID transmitted by the processor, check whether the vertex ID is scheduled for the first time in the current iteration round, if so, assign a unique and fixed global workload ID to the vertex and store it in the corresponding high priority buffer; if not, store the vertex in the corresponding low priority buffer;

[0112] In the processing stage, the vertex tasks to be processed are read out from the high-priority buffer in a first-in-first-out manner, and the corresponding high-priority edges are read from the high-priority edge area according to the current vertex ID, and sent to the corresponding processing unit to execute the graph calculation task; if the vertex state obtained by the processing unit converges to the final result, the low-priority edge area is not read, and the processing of the current vertex is completed;

[0113] The vertices of the low-priority buffer are scheduled out in sequence, and the memory address offset of the low-priority edge in the corresponding low-priority edge area is read according to the vertex ID. During the processing, the memory address offsets of multiple low-priority edges are collected and the requests are packaged and sent to the merger, which uniformly accesses the low-priority edges stored in the external memory through the merger.

[0114] The specific processing process of the combiner is as follows:

[0115] Select the request with the smallest memory address, add a cache line size to the request address as the address threshold, traverse all received request addresses, and if the request address is less than the address threshold, merge the request with the request with the smallest memory address to access the external memory.

[0116] The high priority side area is a storage area composed of high-speed read-write hardware storage devices, and the low priority side area is a storage area composed of low-speed read-write hardware storage devices.

[0117] The specific processing process of the thermal value manager is as follows:

[0118] According to the vertex ID of the high-degree vertex transmitted by the processor, the corresponding vertex attribute value is read from the high-speed internal memory and stored and backed up;

[0119] After each round of calculation starts, the data corresponding to the high-degree vertex is sent to the basic processing unit for vertex update tasks. After the high-degree vertex is updated, coarse-grained data synchronization is performed to back up the corresponding high-degree vertex data. Whenever a vertex update task is generated subsequently, the thermal value manager checks whether the data to be read by the vertex update task hits the stored data in the thermal value manager. If so, the high-degree vertex data is returned directly to the basic processing unit; otherwise, it is forwarded to the on-chip network interface for routing to access the corresponding data.

[0120] Optionally, the processor divides the multiple basic processing units into a coarse-grained Tile processing group, and the multiple basic processing units in each Tile processing group share the backup data in the thermal value manager, while the data between different Tile processing groups are not shared.

[0121] In order to facilitate understanding of the structure and workflow of the accelerator, the execution process is now described. Specifically, the complete process of the hardware accelerator executing the graph computing algorithm may include the following steps:

[0122] Step 1: Allocate continuous storage space of the same size to each PE in the high-speed internal memory. After acquiring the graph data, first send a read request to the external memory to read all vertex data in all graph data. Use the vertex index modulo the number of PEs to assign each vertex to a specific PE in turn. Assuming there are N vertices and M PEs in total, the number of vertices contained in each PE is N / M. Each PE stores the allocated vertex data in the fixed storage space of the current PE in the high-speed internal memory.

[0123] Step 2: Each PE reads vertex data from its own local cache and traverses each vertex in turn. For a vertex v, read the address offset (Address Offset) of the first edge in the adjacent edge table of the vertex from the internal high-speed memory according to the ID of v. Send a request to the external memory based on this offset address to read all the edges of vertex v into the current PE. Traverse each edge of v in turn, access the internal memory according to the edge data to read the weight of this edge and the IDs of all adjacent vertices of v. Read the degree of the adjacent vertex from the internal memory according to the adjacent vertex ID. The logical calculation unit in the PE calculates the priority value of the edge based on the edge weight and the degree of the adjacent vertex according to the priority prediction function. After calculating the priorities of all edges of v, reorder these edges in descending order of priority.

[0124] Step 3: Select the high-degree vertices and move the high-degree vertex data to the thermal value manager for centralized storage and management. Specifically, all processing units traverse each vertex in the local cache and read the degree of each vertex from the high-speed internal memory according to the vertex ID, according to the following formula:

[0125]

[0126] Among them, N v Represents the number of vertices in the graph, MaxDegree represents the maximum vertex degree, Degree(v i ) represents the vertex v i The degree of τ represents the first τ% of the high-degree vertices that you want to obtain, and τ η Indicates the calculated growth rate factor. Use Maxdegree×(1-τ η %) to obtain the screening threshold T of the high-degree vertex η The processing unit traverses all the degrees in the local cache for more than T η All vertex IDs are passed to the thermal value manager. When the thermal value manager receives the IDs of these vertices, it reads the corresponding vertex attribute values ​​from the high-speed internal memory and stores them in the memory space allocated by the thermal value manager in the high-speed internal memory. In the processor, every 16 processing units are divided into a tile. The thermal value manager copies the data backup of multiple high-degree vertices according to the number of tiles. The 16 PEs in each tile share the data backup of the high-degree vertices in the same thermal value manager, and different tiles do not share.

[0127] Step 4: After each iteration starts, the thermal value manager first sends the high-degree vertices to the processing unit for vertex update tasks. After the high-degree vertices are updated, coarse-grained data synchronization is performed to back up a copy of the high-degree vertex data for each Tile. In the subsequent calculation process, whenever a vertex update task is generated, the task is first sent to the thermal value manager. The manager will first check whether the data to be read by the task hits the high-degree vertex cache in the thermal value manager. If it hits, it will directly return the high-degree vertex data to the processing unit. If there is no hit, the request is forwarded to the on-chip network interface for routing to access the remote processing unit.

[0128] Step 5: When the algorithm starts to execute, the processor schedules each active vertex from the active vertex queue in turn and sends the ID of the active vertex to the scheduler. When the scheduler receives the active vertex ID, it checks whether the vertex is scheduled for the first time in the current iteration round. If so, a unique and fixed global workload ID (workloadID) is assigned to the vertex and sent to the high priority buffer. In the processing stage, the scheduler reads the vertex tasks to be processed from the high priority buffer in a first-in-first-out manner, reads the high priority edges corresponding to the vertex from the high priority edge area according to the ID of the current vertex, and sends them to the processing unit. After the processing unit receives these edge data, it starts to traverse all the high priority edges of the vertex in turn, and performs corresponding calculation tasks to update the value of the target vertex. If during the calculation process, the data of the target vertex (i.e., the adjacent vertex) of the active vertex is not in the processing unit to which the current active vertex belongs, the processing unit forwards the data and the target vertex ID to the on-chip network interface, and the on-chip network routes the data to the corresponding processing unit according to the ID of the target vertex to perform vertex update.

[0129] If the vertex received by the scheduler is not scheduled for the first time, the scheduler directly sends the vertex to the low-priority buffer. In the processing stage, the scheduler schedules the active points of the low-priority buffer in turn, and reads the memory address offset of its first low-priority edge from the high-speed internal storage according to the vertex ID. The scheduler collects the low-priority edge memory address offsets generated by the 16 processing units inside each tile, and packages the address and sends it to the merger to access the low-priority edges stored in the external memory.

[0130] Step 6: When the merger receives an access request to the external memory, the merger will merge and reorder the requests according to the granularity of the tile.

[0131] Specifically, the merger first selects the request with the smallest memory address among the 16 processing units of each tile. The minimum address plus a cache line size is used as a threshold, and all request addresses in the current tile are traversed. If there is a request address smaller than this threshold, the request is merged with the request with the smallest address. In this way, the merger merges all requests with addresses smaller than the threshold and only sends sequential access requests to the external memory.

[0132] After merging, in order to ensure that the low-priority edge data read from the external memory can be correctly sent back to the corresponding processing unit, the merger maps the read data.

[0133] Specifically, the merger checks each read edge to determine whether the current edge belongs to the tile being processed. If so, it assigns a one-bit status value and sets it to 1. If not, the status value is set to 0. In addition, each tile only needs 4 bits to meet the requirements because there are only 16 processing units inside each tile.

[0134] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A priority-aware processing method for graph computing, characterized in that: The following steps are involved: Receive the graph data to be processed, traverse each vertex in the graph data, make priority predictions for all adjacent edges of each vertex, and reorder all adjacent edges according to the priority prediction results; According to the reordering results of all adjacent edges of each vertex, each adjacent edge is stored hierarchically; Multiple vertices are scheduled for parallel calculation at the same time, and the adjacent edges of each vertex are scheduled from the high-priority storage area for task processing. If the processed vertex state converges to the final result, the processing task of the current vertex is terminated and all the adjacent edges of the current vertex that have not been traversed are skipped.

2. A priority-aware processing method for graph computing according to claim 1, characterized in that: The reordering process includes: obtaining all adjacent edges and adjacent points of the vertex, and calculating the priority of each adjacent edge according to the weight value of the adjacent edge and the degree of the adjacent point; Traverse all adjacent edges of the vertex, rearrange the adjacent edges in descending order according to their priorities, and obtain the reordered adjacency list.

3. A priority-aware processing method for graph computing according to claim 1, characterized in that: The hierarchical storage process includes: selecting the first K adjacent edges from the reordering results of each vertex according to a preset boundary value K and storing them in a high priority edge area, and storing the remaining adjacent edges in a low priority edge area; If the number of adjacent edges of a vertex is less than the boundary value K, placeholders are filled in the corresponding high-priority edge area.

4. A priority-aware processing method for graph computing according to claim 3, characterized in that: When processing tasks on the adjacent edges of a vertex, first visit the high-priority edge region corresponding to the vertex and traverse all the adjacent edges therein to perform calculation tasks to update the vertex state. If the vertex state converges to the final result, terminate the processing task of the current vertex and skip the remaining low-priority edge regions; If it has not converged to the final result, it waits for rescheduling to access the calculation of adjacent edges in the low-priority edge area.

5. A hardware accelerator for graph computing, characterized in that: Includes processor, scheduler, thermal manager, memory efficiency aware merger, on-chip interconnect network, high-speed internal memory, external memory; The external memory is used to store graph structure information and edge data required by the processor; The processor is used to process graph computing tasks in parallel with multiple basic processing units, each basic processing unit is allocated a corresponding storage space for storing vertex data in a high-speed internal memory, each basic processing unit reads vertex data from the corresponding storage space, performs priority prediction on all adjacent edges of the vertex, and executes the corresponding graph computing task according to the instructions of the scheduler; each basic processing unit also filters out high-degree vertices whose degrees exceed a screening threshold from the corresponding storage space and transmits them to the thermal value manager; The high-speed internal memory is used to allocate storage space to each basic processing unit and store vertex values, intermediate calculation results and edge offset memory addresses; The thermal value manager is used to read corresponding data from the high-speed internal memory according to the received high-degree vertices, so as to realize independent management and calculation of the high-degree vertices; The scheduler is used to allocate a high priority edge region and a low priority edge region to each processing unit, perform hierarchical storage according to the priority of adjacent edges, and preferentially schedule vertex tasks from the high priority edge region; The on-chip interconnect network is used for data interaction and communication between different processing units in the processor; The memory efficiency-aware merger is used to read edge data from external memory and pass it to the processor.

6. A hardware accelerator for graph computing according to claim 5, characterized in that: The processing process of the scheduler is specifically as follows: The scheduler allocates a high-priority edge region, a low-priority edge region, a high-priority buffer, and a low-priority buffer to each processing unit, reorders all adjacent edges according to the priority prediction result of each processing unit, and stores them hierarchically into the high-priority edge region and the low-priority edge region; Receive the vertex ID transmitted by the processor, check whether the vertex ID is scheduled for the first time in the current iteration round, if so, assign a unique and fixed global workload ID to the vertex and store it in the corresponding high priority buffer; if not, store the vertex in the corresponding low priority buffer; In the processing stage, the vertex tasks to be processed are read out from the high-priority buffer in a first-in-first-out manner, and the corresponding high-priority edges are read from the high-priority edge area according to the current vertex ID, and sent to the corresponding processing unit to execute the graph calculation task; If the vertex state obtained by the processing unit converges to the final result, the low-priority edge region is not read and the processing of the current vertex is completed; The vertices of the low-priority buffer are scheduled out in sequence, and the memory address offset of the low-priority edge in the corresponding low-priority edge area is read according to the vertex ID. During the processing, the memory address offsets of multiple low-priority edges are collected and the requests are packaged and sent to the merger, which uniformly accesses the low-priority edges stored in the external memory through the merger.

7. A hardware accelerator for graph computing according to claim 6, characterized in that: The processing process of the merger is specifically as follows: Select the request with the smallest memory address, add a cache line size to the request address as the address threshold, traverse all received request addresses, and if the request address is less than the address threshold, merge the request with the request with the smallest memory address to access the external memory.

8. A hardware accelerator for graph computing according to claim 6, characterized in that: The high priority side area is a storage area composed of high-speed read-write hardware storage devices, and the low priority side area is a storage area composed of low-speed read-write hardware storage devices.

9. The hardware accelerator for graph computing according to claim 5, characterized in that: The processing process of the thermal value manager is specifically as follows: According to the vertex ID of the high-degree vertex transmitted by the processor, the corresponding vertex attribute value is read from the high-speed internal memory and stored and backed up; After each round of calculation starts, the data corresponding to the high-degree vertex is sent to the basic processing unit for vertex update tasks. When the high-degree vertex is updated, coarse-grained data synchronization is performed to back up the corresponding high-degree vertex data. Whenever a vertex update task is generated, the thermal value manager checks whether the data to be read by the vertex update task hits the stored data in the thermal value manager. If so, the high-degree vertex data is returned directly to the basic processing unit; otherwise, it is forwarded to the on-chip network interface for routing to access the corresponding data.

10. A hardware accelerator for graph computing according to claim 9, characterized in that: The processor divides multiple basic processing units into a coarse-grained Tile processing group. Multiple basic processing units in each Tile processing group share the backup data in the thermal value manager, and data between different Tile processing groups is not shared.

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