Semiconductor test structure, wafer and metal short circuit test method

Abstract

The embodiment of the present application provides a semiconductor test structure, a wafer and a metal short circuit test method, wherein the semiconductor test structure comprises: a comb structure unit, two U-shaped structure unit groups, a first test pad, a second test pad, a third test pad and a fourth test pad, and two NMOS tube groups; the comb structure unit comprises a trunk metal line and two comb groups respectively arranged on both sides of the trunk metal line; the first test pad is connected to one end of the trunk metal line; the two U-shaped structure unit groups are respectively located on both sides of the trunk metal line and do not contact the comb structure unit, and each of the NMOS tube groups comprises an NMOS tube corresponding to a U-shaped structure unit in one of the U-shaped structure unit groups. The method can monitor whether there are process defects that cause metal short circuits in the relevant manufacturing process, and can more accurately locate the specific failure point position, which is conducive to analyzing and improving related problems of the process and improving the yield rate of semiconductor products.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor test structure, a wafer, and a metal short circuit test method. Background Art

[0002] With the rapid development of semiconductor technology, the integration density of integrated circuits is increasing day by day. The preparation of smaller size and higher performance devices has always been the goal and direction of the development of the semiconductor industry. In the semiconductor manufacturing process, it is easy for some tiny residual defects to cause metal connections and cause short circuits. For example, the metal aluminum wire is not etched cleanly due to copper precipitation, causing the metal aluminum wire to short-circuit. For example, the aluminum barrier layer is not etched cleanly due to partial etching of the metal aluminum wire, causing the metal aluminum wire to short-circuit. In the above situation, it is often only possible to find out whether the metal is short-circuited through electrical testing. However, since the residual defects are small and located at the bottom of the metal, it is difficult to accurately locate the specific failure point.

[0003] In the related art, a test structure is used for metal short circuit detection, which can only detect whether a metal short circuit occurs in the test structure. The specific failure point location cannot be determined through failure analysis, which increases the difficulty of analyzing and judging process problems, is not conducive to process improvement, and needs to be improved. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor test structure, wafer, and metal short circuit test method, which solves the problem that the metal short circuit detection using the test structure in the related art can only detect the metal short circuit in the test structure, but cannot determine the specific failure point through the failure analysis, which increases the difficulty of analyzing and judging process problems, and cannot accurately locate the specific process problems, which is not conducive to process improvement. It is possible to monitor whether there are process defects that cause metal short circuits in the relevant manufacturing process, and can more accurately locate the specific failure point, which is conducive to analyzing and improving related problems of the process and improving the yield of semiconductor products.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor test structure, including:

[0006] A comb-tooth structure unit, two U-shaped structure unit groups, a first test pad, a second test pad, a third test pad, and a fourth test pad, wherein the comb-tooth structure unit, the two U-shaped structure unit groups, the first test pad, the second test pad, the third test pad, and the fourth test pad are arranged on a metal layer of a wafer;

[0007] Two NMOS tube groups, wherein the NMOS tube groups are arranged on a device layer of a wafer;

[0008] The comb tooth structure unit includes a main metal wire and two comb tooth groups respectively arranged on both sides of the main metal wire, each of the comb tooth groups includes a plurality of toothed metal wires arranged in parallel and spaced apart, and the plurality of toothed metal wires include a first toothed metal wire and a second toothed metal wire which are staggeredly distributed;

[0009] The first test pad is connected to one end of the trunk metal line;

[0010] The two U-shaped structural unit groups are respectively located on both sides of the main metal wire and are not in contact with the comb-tooth structural unit. Each of the U-shaped structural unit groups includes a U-shaped structural unit corresponding to a first toothed metal wire in one of the comb-tooth groups. The opening of the U-shaped structural unit faces the main metal wire. The first toothed metal wire passes through the opening and is embedded in the corresponding U-shaped structural unit. The U-shaped structural unit includes a bottom metal wire and two side metal wires.

[0011] Each of the NMOS tube groups includes an NMOS tube corresponding to a U-shaped structure unit in one of the U-shaped structure unit groups, and a drain terminal of the NMOS tube is connected to a bottom metal wire of the corresponding U-shaped structure unit through a corresponding through hole;

[0012] The second test pad is connected to a source terminal of an NMOS tube in the NMOS tube group through a corresponding through hole;

[0013] The third test pad is connected to the source terminal of another NMOS tube in the NMOS tube group through a corresponding through hole;

[0014] The fourth test pad is connected to the gate terminal of each NMOS tube through a corresponding through hole.

[0015] Optionally, the first spacing between two adjacent toothed metal wires in each comb tooth group is the same, and the first spacing is .

[0016] Optionally, the second spacing between adjacent U-shaped structural units in each of the U-shaped structural unit groups is the same, and the second spacing is .

[0017] Optionally, the side metal wires of each of the U-shaped structural units have the same third spacing as the adjacent toothed metal wires, and the third spacing is .

[0018] Optionally, the first length of the bottom metal wire of the U-shaped structural unit is , the second length of the side metal wire of the U-shaped structural unit is , the first toothed metal wire has the same length as the side metal wire of the corresponding U-shaped structural unit.

[0019] Optionally, the first vertical distance between the suspended end of the side metal wire of each U-shaped structural unit and the main metal wire is The suspended end of the first toothed metal wire embedded in the groove of each U-shaped structural unit is spaced from the corresponding bottom metal wire by a second vertical distance of .

[0020] Optionally, the first test pad, the second test pad, the third test pad, and the fourth test pad are in the shape of rectangles of the same size, and the length of the rectangles is , the width of the rectangle is .

[0021] In a second aspect, an embodiment of the present application further provides a wafer, comprising: a test area, wherein the test area is provided with the semiconductor test structure described in any embodiment of the present application.

[0022] In a third aspect, an embodiment of the present application further provides a metal short circuit testing method applied to a wafer described in any embodiment of the present application, comprising:

[0023] Applying a first voltage to the first test pad, and applying a second voltage to the fourth test pad, wherein the second voltage is greater than or equal to a threshold voltage of an NMOS tube in the NMOS tube group;

[0024] When the NMOS tubes in the NMOS tube group are in the on state, detecting whether the second test pad and the third test pad have current respectively;

[0025] When it is detected that the second test pad or the third test pad has a current, it is determined that a metal short circuit exists in the semiconductor test structure.

[0026] Optionally, after determining that a metal short circuit exists in the semiconductor test structure, the method further includes:

[0027] Grounding the first test pad, scanning the semiconductor test structure with an electron beam, and observing the brightness of the U-shaped structural units in the U-shaped structural unit group through a scanning electron microscope;

[0028] When there is a target U-shaped structure unit having a brightness higher than that of other U-shaped structure units in the U-shaped structure unit group, the position of the target U-shaped structure unit is determined as the metal short circuit position of the semiconductor test structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a test structure provided for exemplary related art;

[0030] Figure 2 A schematic diagram of a semiconductor test structure provided in an embodiment of the present application;

[0031] Figure 3 A schematic diagram of a semiconductor test structure provided in an embodiment of the present application;

[0032] Figure 4 An electrical schematic diagram of a semiconductor test structure provided in an embodiment of the present application;

[0033] Figure 5 A schematic diagram of the results of a metal short circuit test using a semiconductor test structure provided in an embodiment of the present application;

[0034] Figure 6 A flowchart of a metal short circuit testing method for a wafer provided in an embodiment of the present application;

[0035] Figure 7 A flow chart of another wafer metal short circuit testing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the embodiments of the present application, rather than to limit the embodiments of the present application. It should also be noted that, for ease of description, only parts related to the embodiments of the present application are shown in the accompanying drawings, rather than all structures.

[0037] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0038] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. Spatial relationship terms such as "under ...", "under ...", "below ...", "under ...", "above ...", "above", etc., can be used here to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the accompanying drawings is turned over, the element or feature described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under ..." and "under ..." can include both upper and lower orientations. Furthermore, the devices may be included in alternative orientations (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

[0039] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] With the continuous advancement of semiconductor technology, the integration of integrated circuits continues to rise, and the size of semiconductor devices is decreasing. For this reason, any slight process error in the manufacturing process will have a very serious impact on the yield, device performance, and device reliability. In the actual manufacturing process, some slight residual defects often cause short circuit problems in metal connections. For example, the metal aluminum wire is not etched cleanly due to copper precipitation, which causes the metal aluminum wire to short-circuit; for another example, the partial etching of the metal aluminum wire causes the aluminum barrier layer to be not etched cleanly, which can also cause the metal aluminum wire to short-circuit. In the above situation, electrical testing can usually only be used to determine whether the metal is short-circuited. However, since the residual defects are small and located at the bottom of the metal, it is difficult to accurately locate the specific failure point.

[0041] Figure 1 A schematic diagram of a test structure provided for exemplary related technologies, such as Figure 1As shown, the test structure includes a first metal wire structure 101, a second metal wire structure 102, a third metal wire structure 103, a first pad 104, a second pad 105 and a third pad 106. The first metal wire structure 101, the second metal wire structure 102 and the third metal wire structure 103 are not in contact with each other, and one end of the first metal wire structure 101 and the second metal wire structure 102 are respectively connected to the first pad 104, and the two ends of the third metal wire structure 103 are respectively connected to the second pad 105 and the third pad 106. In the process of using the test structure to perform a metal electrical test, a preset voltage is first applied to the second pad 105. Under normal circumstances, a current can be detected at the third pad 106, while the first pad 104 cannot detect a current. Therefore, in the case that there is a metal wire break in the third metal wire structure 103, the current cannot be detected at the third pad 106. In the case that there is a metal short circuit between the first metal wire structure 101 and the third metal wire structure 103, the current will be detected at the first pad 104. In the case where a metal short exists between the second metal line structure 102 and the third metal line structure 103 , a current will be detected at the first pad 104 .

[0042] For the detection of metal short circuit, after the above test structure determines that there is an abnormal short circuit between metal wires, it can be sent for inspection and failure analysis to determine the specific cause of failure and locate the specific failure point. Since the first metal wire structure 101, the second metal wire structure 102 and the third metal wire structure 103 of the test structure are all integrated structures, according to the principle of passive voltage contrast, the third metal wire structure 103 is grounded. Under electron beam irradiation, if there is a metal short circuit between the first metal wire structure 101 and the third metal wire structure 103, the first metal wire structure 101 and the third metal wire structure 103 will be brighter and the second metal wire structure 102 will be darker when observed through a scanning electron microscope; if there is a metal short circuit between the second metal wire structure 102 and the third metal wire structure 103, the second metal wire structure 102 and the third metal wire structure 103 will be brighter and the first metal wire structure 101 will be darker when observed through a scanning electron microscope. However, it is generally observed that the first metal wire structure 101 and the third metal wire structure 103 are brighter, or the second metal wire structure 102 and the third metal wire structure 103 are brighter, and it is impossible to actually locate the specific failure point, especially the metal bottom short circuit caused by a tiny defect, so it is impossible to analyze the specific cause of the metal bottom short circuit. Based on this, the embodiment of the present application provides a semiconductor test structure, a wafer, and a metal short circuit test method, which solves the problem that the test structure is used for metal short circuit detection in the related art, and can only detect that the metal short circuit occurs in the test structure, and cannot determine the specific failure point through the inspection failure analysis, which increases the difficulty of analyzing and judging process problems, and cannot accurately locate specific process problems, which is not conducive to process improvement.

[0043] Figure 2 A schematic diagram of a semiconductor test structure provided in an embodiment of the present application, wherein the semiconductor test structure can be arranged in a preset test area on a wafer, such as Figure 2 As shown, the semiconductor test structure includes a comb-tooth structure unit 201, two U-shaped structure unit groups 202, a first test pad 203, a second test pad 204, a third test pad 205 and a fourth test pad 206, wherein the comb-tooth structure unit 201, the two U-shaped structure unit groups 202, the first test pad 203, the second test pad 204, the third test pad 205 and the fourth test pad 206 are arranged on the metal layer of the wafer, and the relevant structure is Figure 2 The solid lines are used in the figure;

[0044] Two NMOS tube groups 207, wherein the NMOS tube group 207 is arranged on the device layer of the wafer, and the related structure is Figure 2 Indicated by dashed lines;

[0045] Figure 3 A schematic diagram of a semiconductor test structure provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, in Figure 2 On the basis of the present invention, the comb structure unit 201 includes a main metal wire 2011 and two comb groups respectively arranged on both sides of the main metal wire, each comb group includes a plurality of toothed metal wires arranged in parallel and spaced apart, and the plurality of toothed metal wires include a first toothed metal wire 2012 and a second toothed metal wire 2013 that are staggered. Optionally, the metal wire width of the comb structure unit can be .

[0046] In one embodiment, the first spacing between two adjacent toothed metal wires in each comb tooth group is the same, and the first spacing is .

[0047] The first test pad 203 is connected to one end of the main metal line 2011;

[0048] The two U-shaped structural unit groups 202 are respectively located on both sides of the main metal wire 2011 and do not contact the comb-tooth structural unit 201. Each U-shaped structural unit group 202 includes a U-shaped structural unit 2021 corresponding to the first tooth-shaped metal wire 2012 in a comb-tooth group. The opening of the U-shaped structural unit 2021 faces the main metal wire 2011. The first tooth-shaped metal wire 2012 passes through the opening and is embedded in the corresponding U-shaped structural unit 2021. The U-shaped structural unit 2021 includes a bottom metal wire 20211 and two side metal wires 20212. Optionally, the metal wire width of the U-shaped structural unit can be .

[0049] In one embodiment, the second spacing between adjacent U-shaped structural units in each U-shaped structural unit group is the same, and the second spacing is .

[0050] In one embodiment, the first length of the bottom metal wire of the U-shaped structural unit is , the second length of the side metal wire of the U-shaped structural unit is The first toothed metal wire has the same length as the side metal wire of the corresponding U-shaped structural unit.

[0051] In one embodiment, the side metal wires of each U-shaped structural unit have the same third spacing as the adjacent toothed metal wires, and the third spacing is .

[0052] In one embodiment, the first vertical distance between the suspended end of the side metal wire of each U-shaped structural unit and the main metal wire is The suspended end of the first toothed metal wire embedded in the groove of each U-shaped structural unit and the second vertical spacing of the corresponding bottom metal wire are .

[0053] Each NMOS transistor group 207 includes an NMOS transistor 2071 corresponding to a U-shaped structure unit 2021 in a U-shaped structure unit group 202. The drain end 20711 of the NMOS transistor 2071 is connected to the bottom metal line 20211 of the corresponding U-shaped structure unit 2021 through a corresponding through hole ( Figure 2 The through hole is connected as shown in the figure, wherein the size and position of the through hole can be adaptively set according to different process technologies, and this application does not limit this.

[0054] The second test pad 204 is connected to the source terminal 20712 of the NMOS tube 2071 in the NMOS tube group 207 through a corresponding through hole ( Figure 2 (not shown) connection;

[0055] The third test pad 205 is connected to the source terminal 20712 of the NMOS tube 2071 in another NMOS tube group 207 through a corresponding through hole ( Figure 2 (not shown) connection;

[0056] The fourth test pad 206 is connected to the gate terminal 20713 of each NMOS tube 2071 through a corresponding through hole ( Figure 2 ) connection.

[0057] In one embodiment, the first test pad, the second test pad, the third test pad, and the fourth test pad are in the shape of rectangles of the same size, and the length of the rectangles is , the width of the rectangle is .

[0058] in, Figure 4 An electrical schematic diagram of a semiconductor test structure provided in an embodiment of the present application, such as Figure 4 As shown, in Figure 2 On the basis of, each NMOS tube group includes an NMOS tube 2071 corresponding to a U-shaped structure unit 2021 in a U-shaped structure unit group, the drain terminal of the NMOS tube 2071 is connected to the bottom metal wire of the corresponding U-shaped structure unit 2021, the second test pad 204 is connected to the source terminal of the NMOS tube 2071 in an NMOS tube group 207, the third test pad 205 is connected to the source terminal of the NMOS tube 2071 in another NMOS tube group 207, and the fourth test pad 206 is connected to the gate terminal of each NMOS tube 2071.

[0059] As mentioned above, the semiconductor test structure can not only be used to monitor whether a metal short circuit occurs, but also can be used for failure analysis to accurately locate the failure point. On the one hand, the gate terminals of all NMOS tubes in the two NMOS tube groups can be connected to the fourth test pad. By applying a voltage to the fourth test pad, which is greater than or equal to the threshold voltage of the NMOS tube, all NMOS tubes can be turned on at the same time, and each independent U-shaped structural unit is correspondingly provided with an NMOS tube, which is equivalent to the NMOS tubes in one NMOS tube group being connected to the second test pad, and the NMOS tubes in the other NMOS tube group being connected to the third test pad. Therefore, by applying a voltage to the first test pad and monitoring whether there is current in the second test pad and the third test pad, it can be determined whether the semiconductor test structure has a metal short circuit. On the other hand, if the semiconductor test structure has a metal short circuit, the failure point of the semiconductor test structure can be further determined by failure analysis. Among them, the first test pad is grounded and connected to one end of the main metal wire. Since the incident electrons irradiate the structural surface at different potentials, more secondary electrons overflow from the low potential part, so the high potential area is darker and the low potential area is brighter. Therefore, through a scanning electron microscope, it can be observed that the comb-tooth structure unit is brighter. If there is a U-shaped structure unit connected to the comb-tooth structure unit due to a metal short circuit, the U-shaped structure unit will also light up due to the low potential, while other U-shaped structure units are relatively dark because they are suspended and not connected to the comb-tooth structure unit. Figure 5 A schematic diagram of the results of a metal short circuit test using a semiconductor test structure provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, since the U-shaped structural unit in the dotted area 301 is short-circuited with the main metal line, the U-shaped structural unit will be brighter, while other U-shaped structural units will be darker.

[0060] Thus, the failure point of the semiconductor test structure can be accurately determined. Thus, it is possible to monitor whether there are process defects that cause metal short circuits in the relevant manufacturing process, and to more accurately locate the specific failure point, which is conducive to analyzing and improving related problems of the process and improving the yield rate of semiconductor products.

[0061] The present application also provides a wafer, the wafer comprising a test area, the test area being provided with a semiconductor test structure of any of the above schemes. The technical effects that can be achieved by the semiconductor test structure in the above embodiments can also be achieved by the wafer, which will not be described in detail here.

[0062] Figure 6 A flowchart of a metal short circuit test method for a wafer provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the metal short circuit test method includes the following steps:

[0063] S101 , applying a first voltage to a first test pad, and applying a second voltage to a fourth test pad, wherein the second voltage is greater than or equal to a threshold voltage of an NMOS transistor in an NMOS transistor group.

[0064] S102 , when the NMOS tubes in the NMOS tube group are in the on state, respectively detecting whether there is current on the second test pad and the third test pad.

[0065] S103 : When it is detected that the second test pad or the third test pad has a current, determine that a metal short circuit exists in the semiconductor test structure.

[0066] As mentioned above, by applying a second voltage to the fourth test pad, the second voltage is greater than or equal to the threshold voltage of the NMOS tube in the NMOS tube group. Since the gate terminals of all NMOS tubes are connected to the fourth test pad, all NMOS tubes will be turned on, so that each independent U-shaped structure unit is connected to its corresponding second test pad or third test pad. In the case of applying a first voltage to the first test pad, if there is a short circuit between the main metal wires of the U-shaped structure unit and the comb structure unit, it can be detected that there is current in the second test pad or the third test pad, thereby determining that there is a metal short circuit in the semiconductor test structure. If it is monitored that there is no current in the second test pad or the third test pad, there is no metal short circuit in the semiconductor test structure, thereby effectively monitoring whether there are process defects that cause metal short circuits in the relevant manufacturing process.

[0067] Figure 7 A flowchart of another wafer metal short circuit test method provided in an embodiment of the present application, such as Figure 7 As shown, the metal short circuit test method includes the following steps:

[0068] S201 , applying a first voltage to a first test pad, and applying a second voltage to a fourth test pad, wherein the second voltage is greater than or equal to a threshold voltage of an NMOS transistor in the NMOS transistor group.

[0069] S202 , when the NMOS tubes in the NMOS tube group are in the on state, respectively detect whether there is current on the second test pad and the third test pad.

[0070] S203: When it is detected that the second test pad or the third test pad has a current, determine that a metal short circuit exists in the semiconductor test structure.

[0071] S204 , grounding the first test pad, scanning the semiconductor test structure with an electron beam, and observing the brightness of the U-shaped structural units in the U-shaped structural unit group through a scanning electron microscope.

[0072] S205 . When there is a target U-shaped structure unit with a brightness higher than that of other U-shaped structure units in the U-shaped structure unit group, determine the position of the target U-shaped structure unit as the metal short circuit position of the semiconductor test structure.

[0073] As mentioned above, an electron beam is used to scan the semiconductor test structure. Since the incident electrons irradiate the surface of the structure at different potentials, more secondary electrons overflow from the low potential part, so the high potential area is darker and the low potential area is brighter. Therefore, the brightness of the U-shaped structure unit in the U-shaped structure unit group can be confirmed by scanning electron microscope observation, thereby judging the specific failure point in the semiconductor test structure, that is, the specific location where the metal short circuit occurs. If there is a U-shaped structure unit connected to the comb-tooth structure unit due to a metal short circuit, then the U-shaped structure unit will also light up due to the low potential, while other U-shaped structure units are relatively dark because they are suspended and not connected to the comb-tooth structure unit. Therefore, the specific location where the metal short circuit occurs can be located, which is conducive to more accurate positioning of the specific failure point in the semiconductor test structure, and is conducive to analyzing and improving related problems of the process, and improving the yield of semiconductor products.

[0074] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0075] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A semiconductor test structure, characterized in that: include: A comb-tooth structure unit, two U-shaped structure unit groups, a first test pad, a second test pad, a third test pad, and a fourth test pad, wherein the comb-tooth structure unit, the two U-shaped structure unit groups, the first test pad, the second test pad, the third test pad, and the fourth test pad are arranged on a metal layer of a wafer; Two NMOS tube groups, wherein the NMOS tube groups are arranged on a device layer of a wafer; The comb tooth structure unit includes a main metal wire and two comb tooth groups respectively arranged on both sides of the main metal wire, each of the comb tooth groups includes a plurality of toothed metal wires arranged in parallel and spaced apart, and the plurality of toothed metal wires include a first toothed metal wire and a second toothed metal wire which are staggeredly distributed; The first test pad is connected to one end of the trunk metal line; The two U-shaped structural unit groups are respectively located on both sides of the main metal wire and are not in contact with the comb-tooth structural unit. Each of the U-shaped structural unit groups includes a U-shaped structural unit corresponding to a first toothed metal wire in one of the comb-tooth groups. The opening of the U-shaped structural unit faces the main metal wire. The first toothed metal wire passes through the opening and is embedded in the corresponding U-shaped structural unit. The U-shaped structural unit includes a bottom metal wire and two side metal wires. Each of the NMOS tube groups includes an NMOS tube corresponding to a U-shaped structure unit in one of the U-shaped structure unit groups, and a drain terminal of the NMOS tube is connected to a bottom metal wire of the corresponding U-shaped structure unit through a corresponding through hole; The second test pad is connected to a source terminal of an NMOS tube in the NMOS tube group through a corresponding through hole; The third test pad is connected to the source terminal of another NMOS tube in the NMOS tube group through a corresponding through hole; The fourth test pad is connected to the gate terminal of each NMOS tube through a corresponding through hole.

2. The semiconductor test structure according to claim 1, characterized in that: The first spacing between two adjacent toothed metal wires in each comb tooth group is the same, and the first spacing is .

3. The semiconductor test structure according to claim 1, characterized in that: The second spacing between adjacent U-shaped structural units in each of the U-shaped structural unit groups is the same, and the second spacing is .

4. The semiconductor test structure according to claim 1, characterized in that: The side metal wires of each U-shaped structural unit have the same third spacing as the adjacent toothed metal wires, and the third spacing is .

5. The semiconductor test structure according to claim 1, characterized in that: The first length of the bottom metal wire of the U-shaped structural unit is , the second length of the side metal wire of the U-shaped structural unit is , the first toothed metal wire has the same length as the side metal wire of the corresponding U-shaped structural unit.

6. The semiconductor test structure according to claim 1, characterized in that: The first vertical distance between the suspended end of the side metal wire of each U-shaped structural unit and the main metal wire is The suspended end of the first toothed metal wire embedded in the groove of each U-shaped structural unit is spaced from the corresponding bottom metal wire by a second vertical distance of .

7. The semiconductor test structure according to claim 1, characterized in that: The first test pad, the second test pad, the third test pad and the fourth test pad are in the shape of rectangles of the same size, and the length of the rectangle is , the width of the rectangle is .

8. A wafer, characterized in that: include: A test area, wherein the test area is provided with a semiconductor test structure as described in any one of claims 1 to 7.

9. A metal short circuit testing method for a wafer as claimed in claim 8, characterized in that: include: Applying a first voltage to the first test pad, and applying a second voltage to the fourth test pad, wherein the second voltage is greater than or equal to a threshold voltage of an NMOS tube in the NMOS tube group; When the NMOS tubes in the NMOS tube group are in the on state, detecting whether the second test pad and the third test pad have current respectively; When it is detected that the second test pad or the third test pad has a current, it is determined that a metal short circuit exists in the semiconductor test structure.

10. The metal short circuit testing method according to claim 9, characterized in that: After determining that a metal short circuit exists in the semiconductor test structure, the method further includes: Grounding the first test pad, scanning the semiconductor test structure with an electron beam, and observing the brightness of the U-shaped structural units in the U-shaped structural unit group through a scanning electron microscope; When there is a target U-shaped structure unit having a brightness higher than that of other U-shaped structure units in the U-shaped structure unit group, the position of the target U-shaped structure unit is determined as the metal short circuit position of the semiconductor test structure.

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