Monolithic integrated GaN cascode structure based on thin film transistor technology

Abstract

The invention discloses a monolithic integrated GaN cascode structure based on a thin film transistor technology and a preparation method, and relates to the technical field of semiconductor devices. The GaN cascode structure comprises a thin film transistor (TFT) and a gallium nitride transistor (GaN HEMT) which are integrated in a monolithic heterogeneous mode, a drain electrode of the TFT is electrically connected with a source electrode of the GaN HEMT, and the source electrode of the TFT is electrically connected with a grid electrode of the GaN HEMT. The TFT and GaN HEMT monolithic heterogeneous integration is adopted, the TFT serves as a normally-closed device in a Cascode structure, the technological process of the TFT can be compatible with a back-end manufacturing process, and the TFT and the GaN HEMT can be normally integrated at low temperature (lt; production is completed in equipment in the back-end process of the GaN-enhanced Cascode structure, the integration level is high, interconnection parasitic parameters are greatly reduced, the switching frequency of the GaN-enhanced Cascode structure can be remarkably improved, and the static power consumption of the switch can be reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and specifically relates to a monolithic integrated GaN cascode structure and a preparation method based on thin film transistor technology. Background Art

[0002] GaN has the advantages of wide bandgap, high operating frequency, and strong process compatibility, and is widely used in high electron mobility transistors. However, in practical industrial applications, it is not easy to prepare enhanced devices for GaN high mobility transistors, so it is necessary to connect enhanced transistors in series for control, namely the GaN Cascode (common source and common gate) structure, so as to achieve low power consumption and safety of transistors in production and use.

[0003] The traditional GaN Cascode structure connects a low-voltage normally-off Si MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) in series with a high-voltage normally-on GaN HEMT (High electron mobility transistor) to provide a normally-off and high-voltage safety and stability feature. This common-source and common-gate structure is achieved by stacking and packaging silicon-based and gallium nitride-based chips. It not only has a low level of integration and a large area, but also the parasitic parameters between different device structures will greatly affect the performance of the device, and cannot meet the current mainstream system integration and miniaturization trends.

[0004] With the emergence of monolithic heterogeneous integration of GaN Cascode structures, the system integration level has been greatly improved. However, in most of the current integrated circuit manufacturing, conventional crystalline silicon transistors need to exist in the front-end process, that is, under high temperature conditions >450°, which will cause the traditional monolithic integrated GaN Cascode structure to be incompatible with the back-end process, resulting in relatively slow production speed and higher production costs. In addition, traditional Si materials can no longer fully meet its miniaturization, high frequency, high power and other indicators, while gallium nitride has the characteristics of high bandgap width, high saturation current, high breakdown voltage, etc., which can better meet market requirements, and the performance shortcomings of Si materials themselves will limit the overall performance of Cascode, resulting in the inability to give full play to the performance advantages of gallium nitride materials. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a monolithic integrated GaN cascode structure and a preparation method based on thin film transistor technology. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a monolithically integrated GaN cascode structure based on thin film transistor technology, comprising a monolithically heterogeneously integrated thin film transistor and a GaN HEMT, wherein the drain of the thin film transistor is electrically connected to the source of the GaN HEMT, and the source of the thin film transistor is electrically connected to the gate of the GaN HEMT.

[0007] In one embodiment of the present invention, the GaN HEMT comprises: a monolithic heterogeneous integrated epitaxial wafer structure and a source, a drain and a gate arranged at intervals on the upper surface of the monolithic heterogeneous integrated epitaxial wafer structure, wherein:

[0008] The monolithic heterogeneous integrated epitaxial sheet structure includes a substrate layer, a buffer layer, a GaN channel layer, and an AlGaN barrier layer arranged from bottom to top;

[0009] The gate of the GaN HEMT is located between its source and drain.

[0010] In one embodiment of the present invention, an etched isolation mesa extending from the AlGaN barrier layer to the GaN channel layer is etched at the position of the AlGaN barrier layer on one side of the monolithic heterogeneous integrated epitaxial wafer structure that is not covered by the source, drain and gate of the GaN HEMT;

[0011] The thin film transistor is disposed on the upper surface of the etched isolation table to achieve monolithic heterogeneous integration with the GaN HEMT.

[0012] In one embodiment of the invention, the monolithic heterogeneous integrated epitaxial sheet structure is etched with an isolation groove extending from the AlGaN barrier layer to the GaN channel layer;

[0013] The source, drain and gate of the GaN HEMT are provided on the upper surface of the AlGaN barrier layer on one side of the isolation groove;

[0014] The thin film transistor is disposed on the upper surface of the AlGaN barrier layer on the other side of the isolation groove to achieve monolithic heterogeneity integration with the GaN HEMT.

[0015] In one embodiment of the present invention, an ion implanted planar isolation region extending from the AlGaN barrier layer to the GaN channel layer is provided at the position of the AlGaN barrier layer on one side of the monolithic heterogeneous integrated epitaxial wafer structure not covered by the source, drain and gate of the GaN HEMT;

[0016] The thin film transistor is disposed on the upper surface of the ion implantation plane isolation region to achieve monolithic heterogeneity integration with the GaNHEMT.

[0017] In one embodiment of the present invention, the thin film transistor is a bottom gate structure transistor with a single thin film channel, a top gate structure transistor with a single thin film channel, or a ring gate structure transistor with a multi-film channel stack.

[0018] In one embodiment of the present invention, the material of the thin film channel layer of the thin film transistor is indium tin oxide, indium oxide, indium zinc oxide, gallium indium zinc oxide quaternary compound, zinc tin oxide or polycrystalline silicon.

[0019] In one embodiment of the present invention, the thickness of the thin film channel layer is 0.1 nm to 500 nm.

[0020] The present invention provides a method for preparing a monolithically integrated GaN cascode structure based on thin film transistor technology, which is applicable to the monolithically integrated GaN cascode structure based on thin film transistor technology described in any of the above embodiments, and the preparation method comprises:

[0021] Step 1: stacking an epitaxial buffer layer, a GaN channel layer and an AlGaN barrier layer in sequence on a substrate layer to obtain a monolithic heterogeneous integrated epitaxial wafer structure, wherein a two-dimensional electron gas is formed at a contact interface between the GaN channel layer and the AlGaN barrier layer;

[0022] Step 2: Etch or ion implantation of the monolithic heterogeneous integrated epitaxial sheet structure, cut off the transmission of the two-dimensional electron gas, and form an AlGaN / GaN island and an isolated area;

[0023] Step 3: Prepare the source, drain and gate on the AlGaN barrier layer of the AlGaN / GaN island to form GaNHEMT;

[0024] Step 4: Prepare thin film transistors on the upper surface of the isolation region;

[0025] Step 5: forming a metal interconnection between the drain of the thin film transistor and the source of the GaN HEMT, and forming a metal interconnection between the source of the thin film transistor and the gate of the GaN HEMT, to obtain the monolithic integrated GaN cascode structure based on thin film transistor technology.

[0026] In one embodiment of the present invention, in step 4, when preparing the thin film transistor, a magnetron sputtering process is used to prepare the thin film channel layer, and annealed in an environment containing hydrogen or nitrogen.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] The monolithic integrated GaN Cascode structure based on thin film transistor technology of the present invention adopts monolithic heterogeneous integration of thin film transistors and GaN HEMTs. The thin film transistor is used as a normally-off device in the Cascode structure. In production, its process can be compatible with the back-end process technology, and does not require semiconductor equipment processing in the front-end process. The production can be completed in the equipment in the back-end process at low temperature (<450°), which greatly simplifies the complexity of the heterogeneous integration process, improves the output density, and reduces the production cost. In terms of performance, the thin film transistor achieves a significant increase in switching frequency and a significant reduction in the static power consumption of the switch. The deposition process for preparing the thin film transistor can easily realize the stacking of multiple thin film channels, and prepare a multi-nanosheet structure with a ring gate and multiple channels, which is conducive to preparing an enhanced device with a smaller feature size and stronger gate control capability, thereby bringing more possibilities for the performance improvement and preparation scheme of the Cascode.

[0029] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following specifically cites a preferred embodiment and describes it in detail with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural diagram of a monolithic integrated GaN Cascode structure based on thin film transistor technology provided by an embodiment of the present invention;

[0031] Figure 2 It is a structural diagram of another monolithic integrated GaN Cascode structure based on thin film transistor technology provided by embodiments of the present invention;

[0032] Figure 3 It is another structural diagram of a monolithic integrated GaN Cascode structure based on thin film transistor technology provided by an embodiment of the present invention;

[0033] Figure 4 It is a flowchart of a preparation method for a monolithic integrated GaN Cascode structure based on thin film transistor technology provided by an embodiment of the present invention;

[0034] Figure 5 It is a schematic diagram of the preparation process of a monolithic integrated GaN Cascode structure based on thin film transistor technology provided by an embodiment of the present invention;

[0035] Figure 6 It is a schematic diagram of the preparation process of another monolithic integrated GaN Cascode structure based on thin film transistor technology provided by embodiments of the present invention;

[0036] Figure 7 It is another schematic diagram of the preparation process of a monolithic integrated GaN Cascode structure based on thin film transistor technology provided by the embodiment of the present invention.

[0037] Icon: 1-substrate layer; 2-buffer layer; 3-GaN channel layer; 4-AlGaN barrier layer; 5-first source; 6-first gate; 7-first drain; 8-second gate; 9-insulating layer; 10-second source; 11-second drain; 12-thin film channel layer; 13-first metal interconnection line; 14-second metal interconnection line; 15-gate dielectric layer; 16-isolation dielectric layer; 17-sacrificial layer; 18-dummy gate. DETAILED DESCRIPTION

[0038] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following is a detailed description of a monolithic integrated GaN Cascode structure and a preparation method based on thin film transistor technology proposed by the present invention in combination with the accompanying drawings and specific embodiments.

[0039] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0040] In a first aspect, an embodiment of the present invention provides a monolithically integrated GaNCascode structure based on thin film transistor technology, including a monolithically heterogeneously integrated thin film transistor and a GaN HEMT (gallium nitride transistor), wherein the drain of the thin film transistor is electrically connected to the source of the GaN HEMT, and the source of the thin film transistor is electrically connected to the gate of the GaN HEMT.

[0041] Thin film transistors (TFTs) are normally-off transistors that feature simple manufacturing processes, low production costs, and full compatibility with back-end processes. Thin film transistors are structures composed of multiple thin film layers, using sophisticated advanced processes, and the devices have extremely high precision and stability. In the off state, thin film transistors can effectively prevent the passage of current and achieve lower off current, giving thin film transistors significant advantages in applications that require precise control of current. When display is not needed, thin film transistors can remain normally off, a feature that lays the foundation for their use in low-power applications.

[0042] In a possible embodiment, the GaN HEMT includes a monolithic heterogeneous integrated epitaxial wafer structure and a source, a drain and a gate arranged at intervals on the upper surface of the monolithic heterogeneous integrated epitaxial wafer structure, wherein the monolithic heterogeneous integrated epitaxial wafer structure includes a substrate layer, a buffer layer, a GaN channel layer and an AlGaN barrier layer stacked from bottom to top; the gate of the GaN HEMT is located between its source and drain.

[0043] Optionally, the material of the substrate layer may be a material having a crystal orientation of <111> High-resistance silicon, crystal orientation <100> The thickness of the substrate layer of high resistance silicon, semi-insulating sapphire or semi-insulating AlN can be 50-1500 μm.

[0044] Optionally, the thickness of the buffer layer is 1.5 μm, the thickness of the GaN channel layer is 200 nm, and the thickness of the AlGaN barrier layer is 5 nm.

[0045] In a possible embodiment, an etched isolation mesa extending from the AlGaN barrier layer to the GaN channel layer is etched at the position of the AlGaN barrier layer on one side of the monolithic heterogeneous integrated epitaxial wafer structure that is not covered by the source, drain and gate of the GaN HEMT; and a thin film transistor is arranged on the upper surface of the etched isolation mesa to achieve monolithic heterogeneous integration with the GaN HEMT.

[0046] In a possible embodiment, an isolation trench extending from the AlGaN barrier layer to the GaN channel layer is etched in the monolithic heterogeneous integrated epitaxial wafer structure; the source, drain and gate of the GaN HEMT are arranged on the upper surface of the AlGaN barrier layer on one side of the isolation trench; and the thin film transistor is arranged on the upper surface of the AlGaN barrier layer on the other side of the isolation trench to achieve monolithic heterogeneous integration with the GaN HEMT.

[0047] In a possible embodiment, an ion-implanted planar isolation region extending from the AlGaN barrier layer to the GaN channel layer is provided at the position of the AlGaN barrier layer on one side of the monolithic heterogeneous integrated epitaxial wafer structure not covered by the source, drain and gate of the GaN HEMT; and a thin film transistor is provided on the upper surface of the ion-implanted planar isolation region to achieve monolithic heterogeneous integration with the GaN HEMT.

[0048] Optionally, the material of the source and drain of GaN HEMT is a titanium / aluminum / nickel / gold laminated metal, with a thickness corresponding to 20 / 120 / 50 / 40 nm, and the material of the gate of GaN HEMT is a nickel / gold laminated metal, with a thickness corresponding to 50 / 150 nm.

[0049] Optionally, the thin film transistor may be a bottom gate structure transistor with a single thin film channel, a top gate structure transistor with a single thin film channel, or a ring gate structure transistor with a multi-film channel stack.

[0050] It can be understood that for multi-thin film channel stacking ring gate structure transistors, the ring gate structure improves gate control capabilities, and the multi-channel stacking form achieves high current density, greatly improving driving capabilities.

[0051] Optionally, the material of the thin film channel layer of the thin film transistor is indium tin oxide (ITO), indium oxide (InO), indium zinc oxide (IZO), gallium indium zinc oxide quaternary compound (α-IGZO), zinc tin oxide (ZTO) or polysilicon. The thickness of the thin film channel layer can be 0.1nm to 500nm.

[0052] The polysilicon may be a polysilicon film produced by a solid phase crystallization method. Indium tin oxide (ITO) and indium gallium zinc oxide (IGZO) films have high conductivity and transparency, and low resistivity, which helps to reduce energy loss in thin film transistors, improve device efficiency, and speed up switching, thereby making the device have faster response performance.

[0053] The monolithic integrated GaN Cascode structure based on thin film transistor technology of this embodiment, the thin film transistor is a normally closed device in the Cascode structure. In production, its process is compatible with the back-end process technology, does not require semiconductor equipment processing in the front-end process, and can be completed in the equipment in the back-end process at low temperature (<450°), which greatly simplifies the complexity of the heterogeneous integration process, improves the output density, and reduces the production cost. In terms of performance, the thin film transistor achieves a significant increase in switching frequency and a significant reduction in the static power consumption of the switch, and the deposition process for preparing the thin film transistor can easily realize the stacking of multiple thin film channels and prepare a multi-nanosheet structure with a ring gate and multiple channels, which is conducive to the preparation of an enhanced device with a smaller feature size and stronger gate control capability, thereby bringing more possibilities for the performance improvement and preparation scheme of the Cascode.

[0054] Further, the monolithic integrated GaNCascode structure based on thin film transistor technology of the present invention will be specifically described by specific embodiments.

[0055] Example 1

[0056] See also Figure 1 , Figure 1 It is a structural diagram of a monolithic integrated GaNCascode structure based on thin film transistor technology provided by an embodiment of the present invention. If Figure 1As shown, in this embodiment, the monolithic integrated GaN cascode structure based on thin film transistor technology includes a substrate layer 1, a buffer layer 2, a GaN channel layer 3 and an AlGaN barrier layer 4 stacked from bottom to top. Among them, the substrate layer 1, the buffer layer 2, the GaN channel layer 3 and the AlGaN barrier layer 4 constitute a monolithic heterogeneous integrated epitaxial wafer structure, and a two-dimensional electron gas is formed at the contact interface between the GaN channel layer 3 and the AlGaN barrier layer 4.

[0057] An etched isolation mesa extending from the AlGaN barrier layer 4 to the GaN channel layer 3 is etched on the AlGaN barrier layer 4 to cut off the transmission of the two-dimensional electron gas, and an AlGaN / GaN island is formed on one side of the etched isolation mesa. A first source 5, a first gate 6, and a first drain 7 are arranged on the upper surface of the AlGaN barrier layer 4 of the AlGaN / GaN island to form a GaNHEMT, wherein the first gate 6 is located between the first source 5 and the first drain 7. A thin film transistor is arranged on the upper surface of the etched isolation mesa.

[0058] In this embodiment, the thin film transistor is a bottom-gate structure transistor with a single thin film channel, comprising: a second gate electrode 8, an insulating layer 9, a second source electrode 10, a second drain electrode 11 and a thin film channel layer 12. The second gate electrode 8 is arranged on the upper surface of the etched isolation mesa, the insulating layer 9 is located on the upper surface of the second gate electrode 8 and the upper surface of a portion of the etched isolation mesa, the second source electrode 10 and the second drain electrode 11 are arranged on the upper surface of the insulating layer 9 with intervals, the thin film channel layer 12 is arranged on the upper surface of the insulating layer 9 and is located between the second source electrode 10 and the second drain electrode 11, and the thin film channel layer 12 is in contact with the second source electrode 10 and the second drain electrode 11, respectively.

[0059] In this embodiment, the second source 10 and the first gate 6 are electrically connected by a first metal interconnection line 13 , and the second drain 11 and the first source 5 are electrically connected by a second metal interconnection line 14 .

[0060] It is understandable that the thin film transistor in the monolithically integrated GaN cascode structure based on thin film transistor technology of this embodiment may also be a top-gate structure transistor with a single thin film channel or a ring-gate structure transistor with multiple thin film channels stacked.

[0061] Example 2

[0062] See also Figure 2 , Figure 2 It is a structural diagram of another monolithic integrated GaN Cascode structure based on thin film transistor technology provided by embodiments of the present invention. If Figure 2As shown, in this embodiment, the monolithic integrated GaN cascode structure based on thin film transistor technology includes a substrate layer 1, a buffer layer 2, a GaN channel layer 3 and an AlGaN barrier layer 4 stacked from bottom to top. Among them, the substrate layer 1, the buffer layer 2, the GaN channel layer 3 and the AlGaN barrier layer 4 constitute a monolithic heterogeneous integrated epitaxial wafer structure, and a two-dimensional electron gas is formed at the contact interface between the GaN channel layer 3 and the AlGaN barrier layer 4.

[0063] An isolation trench extending from the AlGaN barrier layer 4 to the GaN channel layer 3 is etched on the AlGaN barrier layer 4 to cut off the transmission of the two-dimensional electron gas, and two AlGaN / GaN islands are formed on both sides of the isolation trench. A first source 5, a first gate 6, and a first drain 7 are arranged on the upper surface of the AlGaN barrier layer 4 of an AlGaN / GaN island to form a GaN HEMT, wherein the first gate 6 is located between the first source 5 and the first drain 7. A thin film transistor is arranged on the upper surface of the AlGaN barrier layer 4 of another AlGaN / GaN island.

[0064] In this embodiment, the thin film transistor is a top-gate structure transistor with a single thin film channel, comprising: a second gate electrode 8, an insulating layer 9, a second source electrode 10, a second drain electrode 11 and a thin film channel layer 12. The thin film channel layer 12 is arranged on the upper surface of the AlGaN barrier layer 4 of another AlGaN / GaN island, the second source electrode 10 and the second drain electrode 11 are arranged at intervals on the upper surface of the thin film channel layer 12, the insulating layer 9 is arranged on the position of the thin film channel layer 12 that is not covered by the second source electrode 10 and the second drain electrode 11, a part of the upper surface of the second source electrode 10 and a part of the upper surface of the second drain electrode 11, and the second gate electrode 8 is arranged on the upper surface of the insulating layer 9.

[0065] In this embodiment, the second source 10 and the first gate 6 are electrically connected by a first metal interconnection line 13 , and the second drain 11 and the first source 5 are electrically connected by a second metal interconnection line 14 .

[0066] It is understandable that the thin film transistor in the monolithically integrated GaN cascode structure based on thin film transistor technology of this embodiment may also be a bottom-gate structure transistor with a single thin film channel or a ring-gate structure transistor with multiple thin film channels stacked.

[0067] For a bottom-gate structure transistor with a single thin film channel and a top-gate structure transistor with a single thin film channel. Optionally, the material of the second gate 8 can be a platinum / titanium laminated metal with a thickness of 100 / 10 nm. The material of the second gate 8 can also be a titanium / gold laminated metal, a titanium / gold / titanium laminated metal or a titanium / silicon laminated metal, wherein gold metal, platinum metal, etc. protect titanium metal to reduce contact resistance, and titanium metal can not only reduce channel contact resistance, but also increase adhesion.

[0068] Optionally, the material of the insulating layer 9 may be silicon oxide, silicon nitride or other dielectric constant ε r The insulating layer 9 may be made of a binary oxide with a high dielectric constant of >3.9, such as aluminum oxide, hafnium oxide, gallium oxide, magnesium oxide, zirconium oxide, lanthanum oxide, tantalum oxide, etc. The insulating layer 9 may also be made of a composite dielectric material, such as a composite dielectric formed by cyclic stacking of aluminum oxide and silicon oxide. The thickness of the insulating layer 9 may be 1 nm to 50 nm.

[0069] Optionally, the material of the second source 10 and the second drain 11 is a chromium / gold laminated metal, with a thickness corresponding to 5 / 25 nm.

[0070] Example 3

[0071] See also Figure 3 , Figure 3 It is another structural diagram of a monolithic integrated GaN Cascode structure based on thin film transistor technology provided by an embodiment of the present invention. If Figure 3 As shown, in this embodiment, the monolithic integrated GaN cascode structure based on thin film transistor technology includes a substrate layer 1, a buffer layer 2, a GaN channel layer 3 and an AlGaN barrier layer 4 stacked from bottom to top. Among them, the substrate layer 1, the buffer layer 2, the GaN channel layer 3 and the AlGaN barrier layer 4 constitute a monolithic heterogeneous integrated epitaxial wafer structure, and a two-dimensional electron gas is formed at the contact interface between the GaN channel layer 3 and the AlGaN barrier layer 4.

[0072] An ion implantation planar isolation region extending from the AlGaN barrier layer 4 to the GaN channel layer 3 is formed on the AlGaN barrier layer 4 by ion implantation to cut off the transmission of the two-dimensional electron gas, and an AlGaN / GaN island is formed on one side of the ion implantation planar isolation region. A first source 5, a first gate 6 and a first drain 7 are arranged on the upper surface of the AlGaN barrier layer 4 of the AlGaN / GaN island to form a GaN HEMT, wherein the first gate 6 is located between the first source 5 and the first drain 7. A thin film transistor is arranged on the upper surface of the ion implantation planar isolation region.

[0073] In this embodiment, the thin film transistor is a ring gate structure transistor with multiple thin film channel stacks, including: a second gate 8, a second source 10, a second drain 11, a nanosheet stack array, a gate dielectric layer 15 and an isolation dielectric layer 16. Among them, the second source 10, the second drain 11 and the nanosheet stack array are arranged on the upper surface of the ion implantation plane isolation region, and the second source 10 and the second drain 11 are located on both sides of the nanosheet stack array and are in contact with the nanosheet stack array. The nanosheet stack array includes a plurality of thin film channel layers 12 arranged in a stacked array from bottom to top, the second gate 8 is arranged around the thin film channel layer 12 in the nanosheet stack array, the gate dielectric layer 15 is located between the thin film channel layer 12 and the second gate 8, and the isolation dielectric layer 16 surrounds the thin film channel layer 12 not surrounded by the second gate 8.

[0074] In this embodiment, the second source 10 and the first gate 6 are electrically connected by a first metal interconnection line 13 , and the second drain 11 and the first source 5 are electrically connected by a second metal interconnection line 14 .

[0075] It is understandable that the thin film transistor in the monolithically integrated GaN cascode structure based on thin film transistor technology of this embodiment may also be a bottom-gate structure transistor with a single thin film channel or a top-gate structure transistor with a single thin film channel.

[0076] For a ring-gate structure transistor with a multi-thin film channel stack, the material of the gate dielectric layer 15 is a high-K dielectric material, which can be aluminum oxide, hafnium oxide or zirconium oxide. The material of the isolation dielectric layer 16 can be silicon nitride, and the metal of the second gate 8, the second source 10 and the second drain 11 can include Au, Ti, Pt, Cr and any combination of stacked metals.

[0077] In a second aspect, an embodiment of the present invention provides a method for preparing a monolithically integrated GaN Cascode structure based on thin film transistor technology, which is applicable to the monolithically integrated GaN Cascode structure based on thin film transistor technology provided in the first aspect. Figure 4 , Figure 4 It is a flowchart of a preparation method for a monolithic integrated GaN Cascode structure based on thin film transistor technology provided by an embodiment of the present invention. If Figure 4 As shown, the preparation method of this embodiment includes:

[0078] Step 1: stacking an epitaxial buffer layer, a GaN channel layer and an AlGaN barrier layer in sequence on the substrate layer to obtain a monolithic heterogeneous integrated epitaxial wafer structure, and forming a two-dimensional electron gas at the contact interface between the GaN channel layer and the AlGaN barrier layer;

[0079] Step 2: Etch or ion implantation of the monolithic heterogeneous integrated epitaxial sheet structure to cut off the transmission of two-dimensional electron gas, forming AlGaN / GaN islands and isolation areas;

[0080] In this embodiment, the isolation region can be an etched isolation mesa formed by etching and extending from the AlGaN barrier layer to the GaN channel layer, or it can be one of the two AlGaN / GaN islands formed on both sides of the isolation groove after etching to form an isolation groove extending from the AlGaN barrier layer to the GaN channel layer, or it can be an ion implanted planar isolation region formed by ion implantation and extending from the AlGaN barrier layer to the GaN channel layer.

[0081] Step 3: Prepare the source, drain and gate on the AlGaN barrier layer of the AlGaN / GaN island to form GaN HEMT;

[0082] Step 4: Prepare thin film transistors on the upper surface of the isolation area;

[0083] Optionally, the thin film transistor may be a bottom gate structure transistor of a single thin film channel, a top gate structure transistor of a single thin film channel, or a ring gate structure transistor of a multi-thin film channel stack. Optionally, the material of the thin film channel layer of the thin film transistor is indium tin oxide (ITO), indium oxide (InO), indium zinc oxide (IZO), gallium indium zinc oxide quaternary compound (α-IGZO), zinc tin oxide (ZTO) or polysilicon. The thickness of the thin film channel layer may be 0.1 nm to 500 nm.

[0084] Optionally, when preparing thin film transistors, the thin film channel layer can be prepared by magnetron sputtering process and annealed in an environment containing hydrogen or nitrogen.

[0085] Exemplary, when the thin film channel layer is prepared by magnetron sputtering process, an annealing treatment at 290° and 10 minutes may be performed under a nitrogen-containing environment.

[0086] Step 5: Form a metal interconnection between the drain of the thin film transistor and the source of the GaN HEMT, and form a metal interconnection between the source of the thin film transistor and the gate of the GaN HEMT to obtain a monolithic integrated GaN Cascode structure based on thin film transistor technology.

[0087] In this embodiment, the thin film transistor is directly deposited on the GaN epitaxial structure of the GaN HEMT, instead of using a soft flexible material as a substrate as is commonly used in the current TFT, thereby achieving monolithic heterogeneous integration of the thin film transistor and the GaN HEMT. The thin film transistor can be produced in equipment in the back-end process at a low temperature (<450°), is compatible with the back-end process technology, and does not require semiconductor equipment processing in the front-end process, which greatly simplifies the complexity of the heterogeneous integration process, improves the yield density, and reduces the production cost.

[0088] Further, the preparation method of the monolithic integrated GaNCascode structure based on thin film transistor technology of the present invention will be specifically described by specific examples.

[0089] Example 1

[0090] See also Figure 5 , Figure 5 It is a schematic diagram of the preparation process of a monolithic integrated GaNCascode structure based on thin film transistor technology provided by an embodiment of the present invention. If Figure 5 As shown, the preparation process of the monolithic integrated GaN Cascode structure based on thin film transistor technology in this embodiment includes the following steps:

[0091] S1: Using metal organic chemical vapor deposition equipment in crystal direction <111> A buffer layer 2 with an epitaxial thickness of 1.5 μm, a GaN channel layer 3 with a thickness of 200 nm and an AlGaN barrier layer 4 with a thickness of 5 nm are sequentially stacked on a high-resistance silicon substrate layer 1 to form a monolithic heterogeneous integrated epitaxial wafer structure; wherein a two-dimensional electron gas is formed at the contact interface between the GaN channel layer 3 and the AlGaN barrier layer 4.

[0092] S2: The AlGaN barrier layer 4 and part of the GaN channel layer 3 are etched by a plasma dry etching process to form an etched isolation table extending from the AlGaN barrier layer 4 to the GaN channel layer 3 to cut off the transmission of the two-dimensional electron gas and form an AlGaN / GaN island on one side of the etched isolation table.

[0093] S3: Prepare titanium / aluminum / nickel / gold stacked metal in the active area on the upper surface of the AlGaN barrier layer 4 of the AlGaN / GaN island by electron beam evaporation or magnetron sputtering, with thicknesses of 20 / 120 / 50 / 40 nm respectively, to form source metal and drain metal, and then use a rapid annealing furnace to anneal for 30 seconds in a nitrogen environment at 800°C to form a first source 5 and a first drain 7 of ohmic contact.

[0094] S4: On the gate pattern formed by photolithography on the upper surface of the AlGaN barrier layer 4 of the AlGaN / GaN island, nickel metal with a thickness of 50 nm and gold metal with a thickness of 150 nm are sequentially deposited by electron beam evaporation or magnetron sputtering to form a first gate 6, thereby obtaining a GaN HEMT.

[0095] S5: using an electron beam evaporation process or a magnetron sputtering process, platinum metal with a thickness of 100 nm and titanium metal with a thickness of 10 nm are sequentially deposited on the photolithographic gate pattern on the upper surface of the etched isolation mesa to form a second gate 8.

[0096] S6: Using plasma enhanced chemical vapor deposition (PECVD) technology, the temperature reaches 300° C. in a nitrogen atmosphere, and a 30 nm thick silicon oxide is deposited on the upper surface of the second gate 8 and the upper surface of the partially etched isolation mesa as the insulating layer 9 of the thin film transistor.

[0097] It is understandable that the insulating layer 9 may also be prepared by processes such as metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), inductively coupled plasma enhanced chemical vapor deposition (ICPCVD) or atomic layer deposition (ALD).

[0098] S7: Using a magnetron sputtering process, a 50 nm thick indium tin oxide thin film is prepared on the upper surface of the insulating layer 9 as the thin film channel layer 12, and then an annealing treatment is performed at 290° for 10 min in a hydrogen or nitrogen environment.

[0099] S8: using an electron beam evaporation process or a magnetron sputtering process, a chromium metal with a thickness of 5 nm and a gold metal with a thickness of 25 nm are sequentially deposited at a position on the insulating layer 9 that is not covered by the thin film channel layer 12 to form a second source electrode 10 and a second drain electrode 11, thereby obtaining a top-gate structure transistor with a single thin film channel;

[0100] S9: Prepare a first metal interconnection line 13 between the second source 10 and the first gate 6 to achieve electrical connection, and prepare a second metal interconnection line 14 between the second drain 11 and the first source 5 to achieve electrical connection, to obtain a monolithic integrated GaN cascode structure based on thin film transistor technology.

[0101] Example 2

[0102] See also Figure 6 , Figure 6 FIG. 1 is a schematic diagram of another process for preparing a monolithically integrated GaN cascode structure based on thin film transistor technology provided by an embodiment of the present invention. Figure 6 As shown, the preparation process of the monolithically integrated GaN cascode structure based on thin film transistor technology in this embodiment includes the following steps:

[0103] S1: Metal organic chemical vapor deposition equipment is used in the crystal direction <111> A buffer layer 2 with an epitaxial thickness of 1.5 μm, a GaN channel layer 3 with a thickness of 200 nm and an AlGaN barrier layer 4 with a thickness of 5 nm are sequentially stacked on a high-resistance silicon substrate layer 1 to form a monolithic heterogeneous integrated epitaxial wafer structure; wherein a two-dimensional electron gas is formed at the contact interface between the GaN channel layer 3 and the AlGaN barrier layer 4.

[0104] S2: etching the AlGaN barrier layer 4 and part of the GaN channel layer 3 using a plasma dry etching process to form an isolation trench extending from the AlGaN barrier layer 4 to the GaN channel layer 3 to cut off the transmission of the two-dimensional electron gas and form two AlGaN / GaN islands on both sides of the isolation trench.

[0105] S3: Prepare titanium / aluminum / nickel / gold stacked metal in the active area on the upper surface of the AlGaN barrier layer 4 of the first AlGaN / GaN island by electron beam evaporation or magnetron sputtering, with thicknesses of 20 / 120 / 50 / 40 nm respectively, to form source metal and drain metal, and then use a rapid annealing furnace to anneal for 30 seconds in a nitrogen environment at 800°C to form a first source 5 and a first drain 7 of ohmic contact.

[0106] S4: On the gate pattern formed by photolithography on the upper surface of the AlGaN barrier layer 4 of the first AlGaN / GaN island, nickel metal with a thickness of 50 nm and gold metal with a thickness of 150 nm are sequentially deposited by electron beam evaporation or magnetron sputtering to form a first gate 6, thereby obtaining a GaN HEMT.

[0107] S5: Using a magnetron sputtering process, a 50 nm thick indium tin oxide film is prepared as a thin film channel layer 12 on the upper surface of the AlGaN barrier layer 4 of the second AlGaN / GaN island, and then an annealing treatment is performed at 290° for 10 min in a hydrogen or nitrogen environment.

[0108] S6: using an electron beam evaporation process or a magnetron sputtering process, chromium metal with a thickness of 5 nm and gold metal with a thickness of 25 nm are sequentially deposited on the active area on the upper surface of the thin film channel layer 12 to form a second source electrode 10 and a second drain electrode 11 .

[0109] S7: Using plasma enhanced chemical vapor deposition (PECVD) technology, the temperature reaches 300°C in a nitrogen atmosphere, and silicon oxide with a thickness of 30nm is deposited as the insulating layer 9 of the thin film transistor on the position on the thin film channel layer 12 not covered by the second source 10 and the second drain 11, on part of the upper surface of the second source 10 and on part of the upper surface of the second drain 11.

[0110] It is understandable that the insulating layer 9 may also be prepared by processes such as metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), inductively coupled plasma enhanced chemical vapor deposition (ICPCVD) or atomic layer deposition (ALD).

[0111] S8: Platinum metal with a thickness of 100 nm and titanium metal with a thickness of 10 nm are sequentially deposited on the photolithographic gate pattern on the upper surface of the insulating layer 9 by electron beam evaporation process or magnetron sputtering process to form a second gate 8.

[0112] S9: Prepare a first metal interconnection line 13 between the second source 10 and the first gate 6 to achieve electrical connection, and prepare a second metal interconnection line 14 between the second drain 11 and the first source 5 to achieve electrical connection, to obtain a monolithic integrated GaN cascode structure based on thin film transistor technology.

[0113] Example 3

[0114] See also Figure 7 , Figure 7 FIG. 1 is another schematic diagram of a manufacturing process of a monolithically integrated GaN cascode structure based on thin film transistor technology provided by an embodiment of the present invention. Figure 7 As shown, the preparation process of the monolithically integrated GaN cascode structure based on thin film transistor technology in this embodiment includes the following steps:

[0115] S1: Metal organic chemical vapor deposition equipment is used in the crystal direction <111> A buffer layer 2 with an epitaxial thickness of 1.5 μm, a GaN channel layer 3 with a thickness of 200 nm and an AlGaN barrier layer 4 with a thickness of 5 nm are sequentially stacked on a high-resistance silicon substrate layer 1 to form a monolithic heterogeneous integrated epitaxial wafer structure; wherein a two-dimensional electron gas is formed at the contact interface between the GaN channel layer 3 and the AlGaN barrier layer 4.

[0116] S2: forming an ion implantation planar isolation region extending from the AlGaN barrier layer 4 to the GaN channel layer 3 on the AlGaN barrier layer 4 by ion implantation to cut off the transmission of the two-dimensional electron gas, and forming an AlGaN / GaN island on one side of the ion implantation planar isolation region.

[0117] S3: Prepare titanium / aluminum / nickel / gold stacked metal in the active area on the upper surface of the AlGaN barrier layer 4 of the AlGaN / GaN island by electron beam evaporation or magnetron sputtering, with thicknesses of 20 / 120 / 50 / 40 nm respectively, to form source metal and drain metal, and then use a rapid annealing furnace to anneal for 30 seconds in a nitrogen environment at 800°C to form a first source 5 and a first drain 7 of ohmic contact.

[0118] S4: On the gate pattern formed by photolithography on the upper surface of the AlGaN barrier layer 4 of the AlGaN / GaN island, nickel metal with a thickness of 50 nm and gold metal with a thickness of 150 nm are sequentially deposited by electron beam evaporation or magnetron sputtering to form a first gate 6, thereby obtaining a GaN HEMT.

[0119] S5: Using LPCVD process and magnetron sputtering process, a sacrificial layer 17 and a thin film channel layer 12 are alternately deposited on the upper surface of the ion implantation planar isolation region to form a fin structure, and polysilicon is deposited on the top and both sides of the fin structure using PECVD process to form a dummy gate 18 across the fin structure.

[0120] S6: using BOE or HF wet etching to etch the sacrificial layer 17 in the fin structure not covered by the dummy gate 18, so that the thin film channel layer 12 therein is exposed, and using ALD process to deposit isolation dielectric on both sides of the dummy gate 18, so as to form a surrounding isolation dielectric layer 16 around the thin film channel layer 12 in the fin structure not covered by the dummy gate 18;

[0121] S7: using an electron beam evaporation process to deposit metal on both sides of the fin structure to form a second source 10 and a second drain 11 .

[0122] S8: using a combination of dry etching and wet etching, the dummy gate 18 and the sacrificial layer 17 in the fin structure covered by the dummy gate 18 are etched to release the thin film channel layer 12 therein.

[0123] S9: Using the ALD process, high-K dielectric is deposited in the released channel area to form a gate dielectric layer 15 surrounding the thin film channel layer 12. Using the electron beam evaporation process, gate metal is deposited on the released channel area so that the gate metal surrounds the high-K dielectric layer and fills the suspended area of ​​the channel to form a second gate 8.

[0124] S10: preparing a first metal interconnection line 13 between the second source 10 and the first gate 6 to achieve electrical connection, and preparing a second metal interconnection line 14 between the second drain 11 and the first source 5 to achieve electrical connection, to obtain a monolithic integrated GaN cascode structure based on thin film transistor technology.

[0125] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0126] In the description of this specification, the description with reference to the terms "one implementation", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0127] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A monolithically integrated GaN cascode structure based on thin film transistor technology, characterized in that: The invention comprises a monolithic heterogeneously integrated thin film transistor and a GaN HEMT, wherein the drain of the thin film transistor is electrically connected to the source of the GaN HEMT, and the source of the thin film transistor is electrically connected to the gate of the GaN HEMT.

2. The monolithically integrated GaN cascode structure based on thin film transistor technology according to claim 1, characterized in that: The GaN HEMT comprises: a monolithic heterogeneous integrated epitaxial wafer structure and a source electrode, a drain electrode and a gate electrode which are spaced apart and arranged on the upper surface of the monolithic heterogeneous integrated epitaxial wafer structure, wherein: The monolithic heterogeneous integrated epitaxial wafer structure comprises a substrate layer, a buffer layer, a GaN channel layer and an AlGaN barrier layer stacked from bottom to top; The gate of the GaN HEMT is located between its source and drain.

3. The monolithically integrated GaN cascode structure based on thin film transistor technology according to claim 2, characterized in that: An etched isolation mesa extending from the AlGaN barrier layer to the GaN channel layer is etched at a position of the AlGaN barrier layer on one side of the monolithic heterogeneous integrated epitaxial wafer structure that is not covered by the source, drain and gate of the GaN HEMT; The thin film transistor is arranged on the upper surface of the etched isolation mesa to achieve monolithic heterogeneous integration with the GaN HEMT.

4. The monolithically integrated GaN cascode structure based on thin film transistor technology according to claim 2, characterized in that: An isolation groove extending from the AlGaN barrier layer to the GaN channel layer is etched in the monolithic heterogeneous integrated epitaxial wafer structure; The source, drain and gate of the GaN HEMT are arranged on the upper surface of the AlGaN barrier layer on one side of the isolation trench; The thin film transistor is arranged on the upper surface of the AlGaN barrier layer on the other side of the isolation trench to achieve monolithic heterogeneous integration with the GaN HEMT.

5. The monolithically integrated GaN cascode structure based on thin film transistor technology according to claim 2, characterized in that: An ion implanted planar isolation region extending from the AlGaN barrier layer to the GaN channel layer is provided at the position of the AlGaN barrier layer on one side of the monolithic heterogeneous integrated epitaxial wafer structure not covered by the source, drain and gate of the GaN HEMT; The thin film transistor is arranged on the upper surface of the ion implantation planar isolation region to achieve monolithic heterogeneous integration with the GaN HEMT.

6. The monolithically integrated GaN cascode structure based on thin film transistor technology according to claim 1, characterized in that: The thin film transistor is a bottom gate structure transistor with a single thin film channel, a top gate structure transistor with a single thin film channel, or a ring gate structure transistor with multiple thin film channels stacked.

7. The monolithically integrated GaN cascode structure based on thin film transistor technology according to claim 1, characterized in that: The material of the thin film channel layer of the thin film transistor is indium tin oxide, indium oxide, indium zinc oxide, gallium indium zinc oxide quaternary compound, zinc tin oxide or polycrystalline silicon.

8. The monolithically integrated GaN cascode structure based on thin film transistor technology according to claim 7, characterized in that: The thickness of the thin film channel layer is 0.1nm-500nm.

9. A method for preparing a monolithically integrated GaN cascode structure based on thin film transistor technology, characterized in that: The monolithic integrated GaN cascode structure based on thin film transistor technology according to any one of claims 1 to 8, wherein the preparation method comprises: Step 1: stacking an epitaxial buffer layer, a GaN channel layer and an AlGaN barrier layer in sequence on a substrate layer to obtain a monolithic heterogeneous integrated epitaxial wafer structure, wherein a two-dimensional electron gas is formed at a contact interface between the GaN channel layer and the AlGaN barrier layer; Step 2: etching or ion implanting the monolithic heterogeneous integrated epitaxial wafer structure to cut off the transmission of the two-dimensional electron gas and form AlGaN / GaN islands and isolation regions; Step 3: preparing a source electrode, a drain electrode and a gate electrode on the AlGaN barrier layer of the AlGaN / GaN island to form a GaN HEMT; Step 4: preparing a thin film transistor on the upper surface of the isolation region; Step 5: forming a metal interconnection between the drain of the thin film transistor and the source of the GaN HEMT, and forming a metal interconnection between the source of the thin film transistor and the gate of the GaN HEMT, to obtain the monolithic integrated GaN cascode structure based on thin film transistor technology.

10. The method for preparing a monolithically integrated GaN cascode structure based on thin film transistor technology according to claim 9, characterized in that: In the step 4, when preparing the thin film transistor, a thin film channel layer is prepared by a magnetron sputtering process, and annealing is performed in an environment containing hydrogen or nitrogen.

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