Zero temperature coefficient under-voltage protection circuit suitable for band-gap reference

Abstract

The invention discloses a zero-temperature coefficient under-voltage protection circuit suitable for band-gap reference, which comprises five enhanced PMOS (P-channel Metal Oxide Semiconductor) tubes, two enhanced NMOS (N-channel Metal Oxide Semiconductor) tubes, three NPN (Negative-Positive-Negative) type transistors and five resistors, and MP1, MP2 and MP3 are of common-gate structures; the Q1 and the Q2 are of a common base structure; the collector electrode of the Q3 is connected with the drain electrode of the MP3, and the base electrode of the Q3 is connected with reference voltage through the R3; the grid electrode of the MP4 is connected with the drain electrode of the MP3, and the drain electrode of the MP4 is connected with the drain electrode of the NM1; the grid electrode of the MN1 is connected with a VBIAS signal; and the drain electrode of the MP5 is connected with the drain electrode of the MN2 and is connected to a VUVLO signal. According to the invention, the band-gap reference circuit is optimized by using the enhanced PMOS tube with the common-gate structure, the buffer structure is improved, the use of a comparator and a depletion type MOS tube is avoided, the under-voltage protection irrelevant to temperature can be provided, the power consumption and the noise are reduced, and the endurance is improved.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a zero temperature coefficient undervoltage protection circuit suitable for a bandgap reference. Background Art

[0002] With the continuous development of intelligent electronic devices, power management chips play an important role in various applications. Usually, when the power management chip detects that the input voltage is insufficient, in order to prevent the input voltage from being too low and causing the chip to work in an abnormal state and affect the subsequent system application, the chip will be shut down to prevent damage. This function is called undervoltage protection.

[0003] Nowadays, the rapid development of portable smart devices has also put forward higher requirements for power management chips. Due to portability, the chip must adapt to various types of outdoor temperatures, that is, the chip must be able to work normally regardless of high or low temperatures. At the same time, the power consumption of the chip also directly determines the battery life of the system. Therefore, a more streamlined circuit structure can not only save layout area and reduce costs, but also reduce system power consumption, thereby improving overall battery life.

[0004] At present, for undervoltage protection circuits, in order to solve the temperature influence and power consumption problems, one method is, for example, the patent application publication number CN111834982A, which uses a circuit combining enhancement and depletion MOS tubes to compare current and temperature, thereby performing compensation or protection; another method is, for example, the patent application publication number CN211183396U, which uses a common bandgap reference circuit combined with a hysteresis comparator to control the hysteresis of the comparison circuit to prevent the circuit from oscillating. However, the two methods currently adopted contain at least the following two problems: 1) When using depletion-type MOS tubes in an undervoltage state, the depletion-type MOS tubes will always generate power consumption, resulting in additional consumption of the circuit; 2) The comparator is very sensitive to noise signals, especially when the hysteresis of the circuit is small, the noise has a great impact on the final output signal; when the hysteresis of the circuit is large or the required accuracy is high, a hysteresis comparator with higher power consumption and cost is required. Summary of the invention

[0005] In view of the above two problems, the purpose of the present invention is to propose a zero temperature coefficient under-voltage protection circuit suitable for a bandgap reference, which uses multiple enhanced PMOS tubes with a common gate structure to provide a stable bandgap reference voltage. At the same time, the buffer circuit structure at the output end is optimized, avoiding the use of comparators and depletion-type MOS tubes, effectively ensuring that the circuit has excellent power consumption and reduces noise. Especially in the under-voltage state, the circuit power consumption is effectively reduced, the noise is less, and the battery life is greatly improved.

[0006] This is achieved through the following technical solutions: A zero temperature coefficient undervoltage protection circuit suitable for bandgap reference is used to protect the circuit without using a comparator and a depletion type MOS tube. The circuit includes 5 enhanced PMOS tubes, 2 enhanced NMOS tubes, 3 NPN transistors and 5 resistors. The 5 enhanced PMOS tubes are MP1, MP2, MP3, MP4 and MP5, the 2 enhanced NMOS tubes are MN1 and MN2, the 3 NPN transistors are Q1, Q2 and Q3, and the 5 resistors are R1, R2, R3, R4 and R5. The source of MP1 is connected to the reference power supply, and MP1, MP2 and MP3 are connected to the reference power supply. Common gate structure; the source of MP2 is connected to the reference power supply, the drain is connected to the base and collector of Q2 through resistor R2, and the emitter of Q2 is grounded; Q1 and Q2 are common base structures, the collector of Q1 is connected to the gate of MP1, and the emitter of Q1 is grounded after passing through R1; the emitter of Q3 is grounded after passing through R5, the collector of Q3 is connected to the drain of MP3, and the base of Q3 is connected to the reference voltage through R3 and grounded through resistor R4; the source of MP3 is connected to the reference power supply; the source of MP4 is connected to the reference power supply, the gate of MP4 is connected to the drain of MP3, and the drain of MP4 is connected to the drain of NM1; the gate of MN1 is connected to V BIAS Signal, V BIAS The signal is used to provide bias voltage to MN1. The source of MN1 is grounded. The source of MP5 is connected to the reference power supply. The gate of MP5 is connected to the drain of MP4. The drain of MP5 is connected to the drain of MN2 and connected to V UVLO Signal, V UVLO The signal is used to control the threshold voltage of the undervoltage circuit; the source of MN2 is grounded, and the gate of MN2 is connected to the gate of MP5.

[0007] Using a common gate structure for multiple enhanced PMOS tubes can simplify the circuit and provide a stable reference voltage. At the same time, the buffer circuit structure at the output end is optimized, avoiding the use of comparators and depletion-type MOS tubes, effectively ensuring excellent power consumption and reducing noise. Especially in the under-voltage state, the current flowing through the NPN transistor is extremely small, the circuit power consumption is effectively reduced, and the battery life is greatly improved.

[0008] Preferably, the current flowing through R2 is I1, , is a negative temperature coefficient, is the positive temperature coefficient, is the bias voltage between Q2 and Q1, U t is the positive temperature characteristic coefficient, is the ratio of the current amplification factors of Q1 and Q2, , K is the Boltzmann constant, T is the temperature, q is the electronic load; the collector current of Q3 is I2, and I2=I1 is controlled; , U BEQ3 is the forward bias voltage between the base and emitter of Q3. The ratio of R5 and R1 is adjusted to obtain a zero temperature coefficient of U UVLO By controlling I2=I1, the flip point of the undervoltage circuit can be obtained, and the temperature coefficient, R5 and R1 can be adjusted at the same time, so that the undervoltage circuit can obtain a voltage with a zero temperature coefficient.

[0009] Preferably, the ratio of the emitter area of ​​Q1 and Q2 is 8:1, and the gate and drain of MP1 are short-circuited. When the base currents of Q1 and Q2 are the same, the emitter area ratio of 8 times can provide a larger current amplification factor and better matching of the output end. The gate and drain of MP1 are short-circuited to ensure that the currents of MP1, MP2 and MP3 are equal.

[0010] Preferably, R3 and R4 can be a single voltage-stabilizing resistor or a voltage-stabilizing series resistor composed of multiple resistors connected in series. R3 and R4 can both divide the voltage and limit the current, thereby effectively controlling the current flowing through Q3. The use of multiple resistors in series can reduce the impact of the failure when some resistors fail.

[0011] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention adopts an enhanced PMOS tube with a common gate structure in the undervoltage protection circuit to optimize the bandgap reference circuit, improve the buffer circuit structure at the output end, avoid the use of a comparator and a depletion-type MOS tube, and effectively ensure that the circuit has excellent power consumption and reduces noise. Especially in the undervoltage state, the circuit power consumption is effectively reduced, the noise is less, and the battery life is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The schematic diagram is a structural diagram of a zero temperature coefficient undervoltage protection circuit suitable for a bandgap reference. DETAILED DESCRIPTION

[0013] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention. Example

[0014] like Figure 1As shown, it is a structural schematic diagram of a zero temperature coefficient undervoltage protection circuit suitable for a bandgap reference. The circuit includes 5 enhanced PMOS tubes, 2 enhanced NMOS tubes, 3 NPN transistors and 5 resistors. The simplified structure not only saves the chip layout area and reduces the cost, but also reduces the power consumption of the chip. Especially when the input VIN voltage is less than the threshold corresponding to the undervoltage protection point, the current I2 flowing through the third NPN transistor Q3 is very small and the enhanced transistor will not generate additional power consumption when undervoltage, thereby greatly reducing the circuit power consumption and improving the endurance of the entire circuit system.

[0015] The five enhancement-mode PMOS tubes are MP1, MP2, MP3, MP4 and MP5, the two enhancement-mode NMOS tubes are MN1 and MN2, the three NPN transistors are Q1, Q2 and Q3, and the five resistors are R1, R2, R3, R4 and R5.

[0016] Specifically, the source of MP1 is connected to the reference power supply, and MP1, MP2 and MP3 are of a common gate structure. The source of MP2 is connected to the reference power supply, and the drain is respectively connected to the base and collector of Q2 through resistor R2, and the emitter of Q2 is grounded. Q1 and Q2 are of a common base structure, the collector of Q1 is connected to the gate of MP1, and the emitter of Q1 is grounded after passing through R1. The emitter of Q3 is grounded after passing through R5, the collector of Q3 is connected to the drain of MP3, and the base of Q3 is respectively connected to the reference voltage through R3 and to ground through resistor R4. The source of MP3 is connected to the reference power supply, the source of MP4 is connected to the reference power supply, the gate of MP4 is connected to the drain of MP3, and the drain of MP4 is connected to the drain of NM1. The gate of MN1 is connected to V BIAS Signal, V BIAS The signal is used to provide bias voltage to MN1. The source of MN1 is grounded. The source of MP5 is connected to the reference power supply, the gate of MP5 is connected to the drain of MP4, and the drain of MP5 is connected to the drain of MN2 and connected to V UVLO Signal, V UVLO The signal is used to control the threshold voltage of the undervoltage circuit. The source of MN2 is grounded, and the gate of MN2 is connected to the gate of MP5.

[0017] Using a common gate structure for multiple enhanced PMOS tubes can simplify the circuit and provide a stable reference voltage. If the gate voltage of the enhanced PMOS tube is insufficient in the undervoltage circuit, a conductive channel cannot be formed, and no consumption will be generated, which can greatly improve the battery life. In contrast, if a depletion-type PMOS tube is used, the channel always exists, which will inevitably lead to additional power consumption. At the same time, the buffer circuit structure at the output end is optimized to avoid the use of comparators and depletion-type MOS tubes, effectively ensuring excellent power consumption and reducing noise. Especially in the undervoltage state, the current flowing through the NPN transistor is extremely small, the circuit power consumption is effectively reduced, and the battery life is greatly improved.

[0018] In this embodiment, the current flowing through R2 is I1. , is the negative temperature coefficient and is also the voltage between the base and the corresponding emitter, It's U BE The change in temperature coefficient is also positive. Characterizes the change in bias voltage between Q2 and Q1, U t The value of U shows a positive temperature characteristic. t Also called positive temperature characteristic coefficient, is the ratio of the current amplification factors of Q1 and Q2, , K is the Boltzmann constant, T is the temperature, q is the electronic load; the collector current of Q3 is I2, and by controlling I2=I1, the flip point of the undervoltage circuit can be obtained. The flip point refers to the critical point at which the circuit is triggered to enter protection. , U BEQ3 is the forward bias voltage between the base and emitter of Q3, thereby, the flip point can be controlled and By adjusting the value of R5 and R1, a zero temperature coefficient U UVLO Signal.

[0019] At the same time, due to the control and By adjusting the value of R5 and R1, a zero temperature coefficient U UVLO Signal, when choosing resistor devices, there is no need to use zero temperature coefficient resistors, and conventional non-zero temperature coefficient resistors can be used directly, which can effectively save the cost of resistors.

[0020] V UVLO The signal is used to control the threshold voltage of the undervoltage circuit. When the power supply voltage is lower than the threshold voltage, V UVLOThe signal will put the circuit into protection state, preventing the device from working under unsafe voltage, avoiding potential damage or unstable operation. In the undervoltage protection circuit, the generation of this signal is controlled by MP5 and MN2 to ensure that the circuit is cut off or protected when the voltage is lower than the threshold voltage. BIAS It is used to provide a bias voltage signal to the circuit to ensure the stability of the operating point of MN1 so that it operates in the correct working state.

[0021] In this embodiment, the ratio of the emitter area of ​​Q1 and Q2 is 8:1, and the gate and drain of MP1 are short-circuited. Since Q1 and Q2 are common base structures, the base currents of the two are the same, so the ratio of the emitter area will greatly affect the current amplification factor. The ratio of 8 times can make the matching of the output end better. It is a kind of amplification factor with a wide range of applications in the bandgap reference circuit; after the gate and drain of MP1 are short-circuited, since MP1, MP2 and MP3 are common gate nodes, the currents of MP1, MP2 and MP3 are equal.

[0022] In this embodiment, R3 and R4 can be a single voltage-stabilizing resistor or a voltage-stabilizing series resistor composed of multiple resistors connected in series. R3 and R4 can both help Q3 to perform voltage division and current limiting protection, play a buffering protection role, and effectively control the current flowing through Q3. By using multiple resistors in series, even if a failure such as burning of a single resistor used in series occurs, the other resistors in series can still work, but the circuit may not work in the best state, but at least avoid the worst situation where a single resistor is directly used and the entire circuit cannot operate after a single resistor fails.

[0023] To sum up, in the undervoltage protection circuit of the present invention, an enhanced PMOS tube with a common gate structure is used to optimize the bandgap reference circuit, improve the buffer circuit structure at the output end, avoid the use of a comparator and a depletion-type MOS tube, and effectively ensure that the circuit has excellent power consumption and reduces noise. Especially in the undervoltage state, the circuit power consumption is effectively reduced, the noise is less, and the battery life is greatly improved, which is significantly progressive.

[0024] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A zero temperature coefficient undervoltage protection circuit suitable for bandgap reference, used to protect the circuit without using a comparator and a depletion MOS tube, It is characterized in that It includes 5 enhanced PMOS tubes, 2 enhanced NMOS tubes, 3 NPN transistors and 5 resistors. The 5 enhanced PMOS tubes are MP1, MP2, MP3, MP4 and MP5, the 2 enhanced NMOS tubes are MN1 and MN2, the 3 NPN transistors are Q1, Q2 and Q3, and the 5 resistors are R1, R2, R3, R4 and R5. Among them, the source of MP1 is connected to the reference power supply, and MP1, MP2 and MP3 are in a common gate structure; the source of MP2 is connected to the reference power supply, and the drain is connected to the base and collector of Q2 respectively through resistor R2, and the emitter of Q2 is grounded; Q1 and Q2 are in a common base structure, the collector of Q1 is connected to the gate of MP1, and the emitter of Q1 is grounded after passing through R1; the emitter of Q3 is grounded after passing through R5, the collector of Q3 is connected to the drain of MP3, and the base of Q3 is connected to the reference voltage through R3 and grounded through resistor R4; the source of MP3 is connected to the reference power supply; the source of MP4 is connected to the reference power supply, the gate of MP4 is connected to the drain of MP3, and the drain of MP4 is connected to the drain of NM1; the gate of MN1 is connected to V BIAS Signal, V BIAS The signal is used to provide bias voltage to MN1. The source of MN1 is grounded. The source of MP5 is connected to the reference power supply. The gate of MP5 is connected to the drain of MP4. The drain of MP5 is connected to the drain of MN2 and connected to V UVLO Signal, V UVLO The signal is used to control the threshold voltage of the undervoltage circuit; the source of MN2 is grounded, and the gate of MN2 is connected to the gate of MP5.

2. A zero temperature coefficient undervoltage protection circuit suitable for a bandgap reference according to claim 1, It is characterized in that The current flowing through R2 is I1, , is a negative temperature coefficient, is the positive temperature coefficient, is the bias voltage between Q2 and Q1, U t is the positive temperature characteristic coefficient, is the ratio of the current amplification factors of Q1 and Q2, , K is the Boltzmann constant, T is the temperature, q is the electronic load; the collector current of Q3 is I2, and I2=I1 is controlled; , U BEQ3 is the forward bias voltage between the base and emitter of Q3. The ratio of R5 and R1 is adjusted to obtain a zero temperature coefficient of U UVLO Signal.

3. A zero temperature coefficient undervoltage protection circuit suitable for a bandgap reference according to claim 1, It is characterized in that The emitter area ratio of Q1 and Q2 is 8:1, and the gate and drain of MP1 are short-circuited.

4. A zero temperature coefficient undervoltage protection circuit suitable for a bandgap reference according to claim 1, It is characterized in that R3 and R4 are both voltage-stabilizing series resistors composed of multiple resistors connected in series.

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