Chip performance test and comparison method and device, electronic equipment and storage medium

Abstract

The invention discloses a chip performance test and comparison method and device, electronic equipment and a storage medium. The method comprises: obtaining a first performance index of each frequency point in a target chip, the first performance index being obtained by testing the target chip; obtaining frequency point distribution and a scene proportion in a real scene corresponding to the target chip; and weighting the first performance index by using the frequency point distribution and the scene proportion to obtain a comprehensive performance index of the target chip. Through the mode, the accuracy of the chip performance index can be improved.

Description

Technical Field

[0001] The present application relates to the field of chip performance testing technology, and in particular to chip performance testing and comparison methods, devices, electronic devices and storage media. Background Art

[0002] As technology develops, chip manufacturers continue to improve their chip development capabilities and continue to iterate their chips. Some new chips can increase computing power and adjust the number of cores or frequencies, which may increase or improve power consumption.

[0003] Therefore, it is crucial to have a complete and comprehensive evaluation of the chip when it is updated. Only with accurate evaluation can we better understand the impact of chip upgrades on terminal devices and formulate a scheduling strategy that is more suitable for the chip platform. Summary of the invention

[0004] The present application provides a chip performance testing and comparison method, device, electronic device and storage medium, which can improve the accuracy of chip performance indicators.

[0005] In a first aspect, the present application provides a chip performance testing method, the method comprising: obtaining a first performance indicator for each frequency point in a target chip, wherein the first performance indicator is obtained by testing the target chip; obtaining the frequency point distribution and scene proportion in a real scene corresponding to the target chip; and weighting the first performance indicator using the frequency point distribution and scene proportion to obtain a comprehensive performance indicator of the target chip.

[0006] In a second aspect, the present application provides a chip performance comparison method, the method comprising: obtaining a first comprehensive performance indicator of a first type of chip, and obtaining a second comprehensive performance indicator of a second type of chip; the first comprehensive performance indicator and the second comprehensive performance indicator are obtained according to the method provided in the first aspect; comparing the first comprehensive performance indicator and the second comprehensive performance indicator to obtain a comparison result between the first type of chip and the second type of chip.

[0007] In a third aspect, the present application provides a chip performance testing device, which includes: a first acquisition module, which acquires a first performance indicator for each frequency point in the target chip, wherein the first performance indicator is obtained by testing the target chip; a second acquisition module, which acquires the frequency distribution and scene proportion in a real scene corresponding to the target chip; a processing module, which uses the frequency distribution and scene proportion to weightedly process the first performance indicator to obtain a comprehensive performance indicator of the target chip.

[0008] In a fourth aspect, the present application provides an electronic device, comprising a processor and a memory coupled to the processor; wherein the memory is used to store a computer program, and the processor is used to execute the computer program to implement the method provided in the first aspect and / or the second aspect.

[0009] In a fifth aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the method provided in the first aspect and / or the second aspect.

[0010] The beneficial effects of the present application are as follows: different from the prior art, the chip performance testing and comparison method, device, electronic device and storage medium provided by the present application obtain a first performance indicator for each frequency point in the target chip, wherein the first performance indicator is obtained by testing the target chip; obtain the frequency point distribution and scene proportion in the real scene corresponding to the target chip; use the frequency point distribution and scene proportion to weight the first performance indicator to obtain a comprehensive performance indicator of the target chip, which can improve the accuracy of the chip performance indicator. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0012] Figure 1 It is a flowchart of an embodiment of a chip performance testing method provided by the present application;

[0013] Figure 2 It is a flowchart of another embodiment of the chip performance testing method provided by the present application;

[0014] Figure 3 It is a flowchart of an embodiment of step 21 provided in this application;

[0015] Figure 4 It is a flowchart of another embodiment of the chip performance testing method provided by the present application;

[0016] Figure 5 is a flow chart of another embodiment of the chip performance comparison method provided by the present application;

[0017] Figure 6 It is a structural schematic diagram of an embodiment of a chip performance testing device provided by the present application;

[0018] Figure 7 It is a structural schematic diagram of an embodiment of an electronic device provided by the present application;

[0019] Figure 8 is a structural schematic diagram of another embodiment of the electronic device provided by the present application;

[0020] Fig. 9 It is a structural schematic diagram of an embodiment of a computer-readable storage medium provided by the present application. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0022] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0023] As technology develops, chip manufacturers continue to improve their chip development capabilities and continue to iterate their chips. Some new chips can increase computing power and adjust the number of cores or frequencies, which may increase or improve power consumption.

[0024] Therefore, it is crucial to have a complete and comprehensive evaluation of the chip when it is updated. Only with accurate evaluation can we better understand the impact of chip upgrades on terminal devices and formulate a scheduling strategy that is more suitable for the chip platform.

[0025] In order to evaluate the power consumption and performance of chips, the industry has a relatively common method in laboratory testing. There are three main methods for chip evaluation in the laboratory.

[0026] The first is to test the power consumption and performance of the whole machine under different chip platforms. The specific approach is: formulate some scenario test cases commonly used by users, try running the test cases on different chips, and measure the difference in power consumption and performance of the whole machine of different chips. If the power consumption of the chip is lower and the performance indicators are good under the same scenario, it means that the performance of the chip is better.

[0027] The second method is to test and count the CPU power consumption of different chips. The specific method is: test the test samples of different chip platforms in the laboratory, measure the CPU power or current of each core frequency point, and obtain the total CPU power consumption of the scene by weighted summation according to the frequency distribution in the scene. By comparing the power consumption differences of different chip platforms and looking at the fluctuation range, it can be judged how much the new chip platform will increase or decrease the power consumption in the same scene.

[0028] The third method is to measure the CPU power and computing performance at each frequency point of the chip. By drawing the CPU energy efficiency curve of the frequency point, you can know the power difference of the CPU under the same computing power. At the same time, after drawing the CPU energy efficiency curves of multiple chips, you can comprehensively evaluate whether there is a difference in the energy efficiency of the chip frequency points, which frequency points have better energy efficiency, and provide suggestions for subsequent frequency adjustment.

[0029] There are few studies on evaluating chip performance from big data, and there are mainly two approaches. One is to count whether there are differences in the power consumption and performance of the whole machine on different chip platforms. The statistical indicators will include the power consumption, current, frame loss, etc. of the whole machine. The second is to calculate the CPU power consumption of the terminal device of the big data user, and then check the frequency distribution, and judge the differences brought by different platforms by comparing the difference in CPU power consumption and frequency distribution. The experimental side method is to test the power consumption and performance of the whole machine under different chip platforms, which has many shortcomings. Limited by the test cost and manpower, the test scenario use cases are relatively single, which cannot fully cover the rich usage scenarios of users, and after adding test scenarios, there are too many comparison dimensions, which makes it difficult to comprehensively evaluate. Secondly, the measurement of the power consumption and performance of the whole machine is strongly bound to the platform and is affected by other devices. It is impossible to clarify whether the gap is caused by different CPU chip platforms or other device selection differences.

[0030] The second experimental method is to test and compare the CPU power consumption of different chip platforms. The advantage of this method over method one is that it is closer to the CPU and eliminates interference from other devices. However, the main problems are: the test scenarios in general laboratories are limited, and the calculated frequency distribution can only represent the results of one scenario. It is a bit biased to evaluate the power consumption of the chip platform. Moreover, it only measures power consumption and fails to pull the performance at the same time.

[0031] The third experimental method is to measure the CPU power and computing performance at each frequency point of the chip platform. The advantage is that it can measure the CPU power consumption and performance at the same time, but this method is not associated with the actual user scenario, and how the frequency points are scheduled cannot be monitored. For example, if a new frequency modulation measure is implemented, what changes have been brought to the frequency point distribution, whether the overall energy efficiency is optimized, and how much the optimization is, this method cannot measure. This method can only explain the chip quality from an experimental perspective, but the scheduling in real scenarios is very rich, and the comprehensive energy efficiency of a chip platform cannot be measured and monitored.

[0032] The first big data method is to count the power consumption and performance of the whole machine when users use different chips. This method is similar to the first method on the experimental side. The power consumption of the whole machine is too greatly affected by the selection of other devices. The final difference cannot be explained whether it is caused by the difference in chip platform or other devices. At the same time, users of different chip platforms have different preferences and behaviors. Direct comparison will actually incorporate the influence of user behavior preferences, so it cannot be compared objectively.

[0033] The second big data method is to calculate the CPU power consumption of users using different chips, and then check the frequency distribution. The disadvantage of this method is that the usage scenarios of the same application may be different for users of different chip platforms. For example, when using the same WeChat application, some users are chatting on WeChat, while others are making video calls. The computing power required for specific usage scenarios is different, and the final comparison may be different user behaviors; and this method only measures the CPU power consumption separately, without correlating performance to see how it performs. At the same time, the frequency points of different chips are different, so it is difficult to compare them together.

[0034] In general, the scenarios measured in the laboratory are customized and limited, while in reality, users use chips in a wide variety of scenarios. The comparison results in the laboratory cannot meet the needs of evaluating the pros and cons of a chip from the perspective of a large number of real users. Therefore, it is urgent to measure the performance of chips from the perspective of big data. However, there is currently no method for big data to simultaneously evaluate the CPU power consumption and computing power performance of different chips. There is only a direct comparison of the power consumption, performance, or CPU frequency distribution of the entire machine, but these methods all have the various shortcomings mentioned above.

[0035] Based on this, the present application proposes any of the following implementation methods to solve at least one of the above technical problems. Please refer to any of the following embodiments for details.

[0036] See also Figure 1 , Figure 1 1 is a flow chart of an embodiment of a chip performance testing method provided by the present application. The method comprises:

[0037] Step 11: Obtain a first performance indicator for each frequency point in the target chip, wherein the first performance indicator is obtained by testing the target chip.

[0038] In some embodiments, corresponding test cases may be set up separately for the chip in the laboratory, and the chip may be tested using the test cases to obtain corresponding performance indicators.

[0039] In some embodiments, the chip can be set in the terminal device, and the terminal device can be tested as a whole to obtain corresponding performance indicators. The chip can be a CPU (Central Processing Unit) or a GPU (graphics processing unit).

[0040] It can be understood that a chip includes multiple processing cores, such as a small core, a large core, an ultra-large core, etc. Each processing core corresponds to multiple frequency points, and the number of frequency points of different types of chips varies.

[0041] Therefore, the first performance index of each frequency point in the target chip can be obtained through testing.

[0042] In other embodiments, the first performance indicator of each frequency point corresponding to each processing core in the target chip may be obtained through testing.

[0043] Step 12: Obtain the frequency distribution and scene proportion in the actual scene corresponding to the target chip.

[0044] In step 11, the first performance index of each frequency point is obtained by testing. However, because the test is usually a standardized test, the test cases can only correspond to a limited number of test scenarios, so the first performance index cannot reflect the actual performance of the target chip's frequency point. Therefore, from the big data level, the frequency point distribution and scenario proportion in the real scenario corresponding to the target chip are obtained.

[0045] The actual scenario corresponding to the target chip is that the target chip is set in a terminal device, and the terminal device is used by the user according to his own usage requirements. That is, the frequency distribution and scenario proportion are obtained through the actual use of multiple terminal devices.

[0046] Among them, frequency distribution refers to the usage time ratio of each frequency point in multiple target chips. Scenario ratio refers to the usage time ratio of target scenario.

[0047] Step 13: The first performance indicator is weighted by using the frequency distribution and the scene proportion to obtain a comprehensive performance indicator of the target chip.

[0048] By weighting the first performance indicator using the frequency distribution, we can obtain a second performance indicator that measures the energy efficiency of the scene using big data.

[0049] By weighting the second performance indicator using the scenario proportion, the comprehensive performance indicator of the target chip can be obtained.

[0050] In this embodiment, by obtaining the first performance indicator of each frequency point in the target chip, wherein the first performance indicator is obtained by testing the target chip; obtaining the frequency point distribution and scene proportion corresponding to the target chip in the actual scene; and using the frequency point distribution and scene proportion to weight the first performance indicator to obtain the comprehensive performance indicator of the target chip, the accuracy of the chip performance indicator can be improved.

[0051] See also Figure 2 , Figure 2 1 is a flow chart of another embodiment of the chip performance testing method provided by the present application. The method comprises:

[0052] Step 21: Obtain the frequency power and frequency computing power corresponding to each processing core in the target chip.

[0053] In some embodiments, a corresponding test case can be set up in the laboratory for each frequency point of each processing core of the chip, and the chip can be tested using the test case to obtain the corresponding frequency point power and frequency point computing power.

[0054] In some embodiments, the chip can be set in a terminal device, and the terminal device can be tested as a whole to obtain the frequency power and frequency computing power corresponding to each processing core.

[0055] In some embodiments, see Figure 3 , step 21 may be the following process:

[0056] Step 211: Determine the processing cores of the target chip and the frequency points corresponding to each processing core.

[0057] The processing cores of the target chip and the frequency points corresponding to each processing core are obtained from the architecture information of the target chip.

[0058] Step 212: Obtain the frequency power and frequency computing power corresponding to each processing core respectively.

[0059] Corresponding test cases are set up in the laboratory for each frequency point of each processing core of the chip, and the chip is tested using the test cases to obtain the corresponding frequency point power and frequency point computing power.

[0060] Step 22: Use the frequency power and frequency computing power to obtain the first performance indicator corresponding to each frequency in each processing core.

[0061] In some embodiments, the ratio between the frequency point power and the frequency point computing power corresponding to each processing core can be used as the first performance indicator.

[0062] Among them, the first performance indicator is the frequency power ratio to the frequency computing power.

[0063] Among them, the first performance indicator can be the ratio of the frequency point computing power to the frequency point power.

[0064] Step 23: Obtain the frequency distribution and scene proportion in the actual scene corresponding to the target chip.

[0065] Step 24: The first performance indicator is weighted by using the frequency distribution and the scene proportion to obtain a comprehensive performance indicator of the target chip.

[0066] Step 23 and step 24 have the same or similar technical solutions as any of the above embodiments, and thus will not be described in detail.

[0067] In this embodiment, the frequency power and frequency computing power corresponding to each processing core in the target chip are obtained to obtain the first performance indicator of each frequency point; and the first performance indicator is weighted by using the frequency distribution and scenario proportion in the real scenario to obtain the comprehensive performance indicator of the target chip, which can improve the accuracy of the chip performance indicator.

[0068] See also Figure 4 , Figure 4 1 is a flow chart of another embodiment of the chip performance testing method provided by the present application. The method comprises:

[0069] Step 41: Obtain a first performance indicator for each frequency point in the target chip, wherein the first performance indicator is obtained by testing the target chip.

[0070] Step 42: Obtain the usage time of each frequency point of each core in real scenarios corresponding to multiple target chips.

[0071] Since the chip is set in the terminal device for use in the real scenario, it is possible to carry out tracking in the terminal device. By tracking, the usage time of each frequency point of each core in the real scenario corresponding to each target chip can be obtained.

[0072] Step 43: Using the usage time of each frequency point of each core, obtain the frequency point distribution corresponding to each frequency point of each core in the target scenario.

[0073] After obtaining the usage time of each frequency point of each core, the frequency point distribution corresponding to each frequency point of each core under each target can be separated. That is, the frequency point distribution can represent the usage time of each core in the target scenario.

[0074] Step 44: Obtain the scene ratio of the target scene.

[0075] When the terminal device is used in a real scenario, each target scene in the terminal device will have a corresponding usage time, so the scene proportion of each target scene can be obtained.

[0076] Step 45: weight the first performance indicator using the frequency distribution and the scene proportion to obtain a comprehensive performance indicator of the target chip.

[0077] The first performance index is weighted by using the frequency distribution to obtain a second performance index;

[0078] The second performance index is weighted by the proportion of scenarios to obtain a comprehensive performance index.

[0079] In this embodiment, by obtaining the first performance indicator of each frequency point in the target chip, the frequency point distribution and scene proportion corresponding to the target chip in the actual scene are obtained; the first performance indicator is weighted by using the frequency point distribution and scene proportion to obtain the comprehensive performance indicator of the target chip, which can improve the accuracy of the chip performance indicator.

[0080] See also Figure 5 , Figure 5 1 is a flow chart of an embodiment of a chip performance comparison method provided by the present application. The method comprises:

[0081] Step 51: Obtain a first comprehensive performance indicator of a first type of chip, and obtain a second comprehensive performance indicator of a second type of chip.

[0082] The first comprehensive performance indicator and the second comprehensive performance indicator are obtained according to any of the above embodiments.

[0083] Step 52: Compare the first comprehensive performance index with the second comprehensive performance index to obtain a comparison result between the first type of chip and the second type of chip.

[0084] In this embodiment, many types of chips can be compared simultaneously, so that different chips can be compared in the same dimension.

[0085] In an application scenario, first confirm the chip that needs to be evaluated for performance. Specifically, select the chip to be evaluated according to the purpose of the analysis, and select a typical model that uses the chip. One or more models of the same chip can be selected, and the data of the typical model represents the corresponding chip. Because it is also necessary to collect data corresponding to the model containing the chip based on users in real scenarios, therefore, select models that already have a certain number of users on the market, so as to facilitate the acquisition from the big data level.

[0086] It is understandable that when the chip is replaced, chip manufacturers usually make some modifications or improvements to the CPU architecture of the chip. Usually the CPU will include multiple processing cores, such as small cores, large cores, super large cores, etc. Each core will have multiple frequency points, and the number of frequency points of different types of chips is uncertain. Of course, as the chip continues to iterate and upgrade, the number and architecture of each core and frequency point may be adjusted. Usually, chip manufacturers will announce the architecture of the chip, including the number of cores and the number and frequency of frequency points.

[0087] In order to understand the power consumption and performance of the chip, the laboratory can usually obtain the power consumption and performance of each core at each frequency point through standardized testing, such as the power and computing power of each frequency point of the chip. This application is not limited to the above-mentioned indicators, but also applies to other or future development indicators for measuring frequency energy efficiency.

[0088] Based on the frequency power consumption and performance indicators measured in the laboratory, a comprehensive indicator for measuring energy efficiency can be calculated. Taking the power and computing power of each frequency point of the chip (CPU) as an example, the comprehensive indicator A for measuring energy efficiency (such as the first performance indicator mentioned above) can be calculated, and the calculation formula is as follows:

[0089]

[0090] The power of each CPU frequency is p, and the computing power of each CPU frequency is s. i represents the core of the CPU, such as small core, large core, and super large core. j represents the specific frequency of the CPU core.

[0091] Comprehensive indicator A measures the power consumption required to achieve the same computing power. The lower the indicator, the less power consumption is required to achieve the same computing power, which means the energy efficiency is better.

[0092] Similarly, by swapping the numerator and denominator, another comprehensive index can be obtained. The meaning it represents will be the opposite, that is, how much computing power can be achieved when the same power consumption is consumed. This application does not specifically limit the calculation method of the comprehensive index, and it is applicable to all. The following will take comprehensive index A as an example to explain in detail.

[0093] Big data side

[0094] The power consumption of the chip is one of the main power consumptions when the terminal device (such as a mobile phone) is running. In order to improve the power consumption experience of users using mobile phones, you can usually set a tracking point to obtain the CPU frequency usage time. Assuming that the CPU frequency usage time in different chip usage scenarios has been obtained, the CPU frequency time ratio can be calculated. The calculation formula is as follows:

[0095]

[0096] Among them, t ijk It is the sum of the usage time of the jth frequency point of core i corresponding to all terminal devices in scenario k. The denominator can be the sum of the usage time of all frequency points of all cores, or the sum of the usage time of all frequency points under each core, or the sum of the usage time of specific frequency points selected according to the purpose of the analysis. ijk Represents the proportion of the usage time of the jth frequency point of core i in scene k to the selected frequency points.

[0097] Therefore, the comprehensive index A for measuring energy efficiency can be weighted and summed according to the proportion of the CPU frequency time to obtain the comprehensive index B (such as the second performance index mentioned above) for measuring energy efficiency of big data scenarios. The calculation method is as follows:

[0098] b k =∑r ijk * ij .

[0099] Among them, r ijk represents the duration ratio of frequency point j in core i of scene k, a ij Indicates the energy efficiency at this frequency point.

[0100] The average energy efficiency of the scene can be calculated through the above method. In order to evaluate the energy efficiency performance of a chip, this application proposes a comprehensive evaluation method. By multiplying the energy efficiency of the scene by the corresponding weight, the weighted sum is obtained to obtain a comprehensive index C (such as the above-mentioned comprehensive performance index). The choice of weights is very rich. For example, the proportion of the usage time of the terminal device in each scene is used as the weight. The advantage of this method is that the usage behavior of terminal devices with different chips may be different. For example, some users prefer to use terminal devices to watch short videos, and some users prefer to use terminal devices to play games. Giving different chips the same weight during calculation is equivalent to smoothing out the scene differences between chips, so that the performance of the chips can be compared together.

[0101] The comprehensive index C can be calculated by the following formula:

[0102] c=∑u k * k .

[0103] Among them, b k represents the average energy efficiency of scenario k, u k Indicates the weight of scene k, such as the screen-on duration ratio of this scene.

[0104] In summary, corresponding test data tables can be designed for different scenarios to store corresponding data when the test is completed.

[0105] On the laboratory side, Table 1 and Table 2 can be designed. The details are as follows:

[0106] Table 1: Design test data table.

[0107] This table mainly stores the power and computing power information at different frequency points under different chip platforms.

[0108] Table name: dim_test_cpu_platform_dmips.

[0109] Data source: The power and computing power obtained by testing different chips at different frequencies in the laboratory.

[0110] The table structure of Table 1 is as follows:

[0111] Field Name Field meaning Field Type platform Chip Platform String core_type CPU core (small core, large core, super large core) String core_freq Frequency Floating point numbers freq_power Frequency power Floating point numbers dmips Frequency Point Computing Power Floating point numbers

[0112] Table 2: Data sheet for designing laboratory energy efficiency.

[0113] This table mainly stores energy efficiency information of different chips and different frequencies. It mainly calculates the ratio of frequency power and computing power based on the above table. This indicator is used to measure the power consumption required under the same computing power.

[0114] Table name: dim_test_cpu_platform_efficiency.

[0115] Data source: Design test data table.

[0116] The table structure of Table 2 is as follows:

[0117]

[0118]

[0119] Big data side

[0120] Table 3: Frequency distribution data table of design scenarios.

[0121] This table mainly stores the frequency distribution information of different chips and different scenarios.

[0122] Table name: dws_cpu_app_freq_du.

[0123] Data source: Fact table of data related to CPU frequency and duration according to different usage scenarios.

[0124] The table structure of Table 3 is as follows:

[0125] Field Name Field meaning Field Type platform Chip Platform String app_name Scenario String core_type CPU core (small core, large core, super large core) String core_freq Frequency Floating point numbers freq_du Frequency duration Floating point numbers freq_du_ratio Frequency point duration ratio Floating point numbers

[0126] Table 4: Design user scenario duration distribution table.

[0127] This table mainly stores the user usage scenario duration information of terminal devices corresponding to different chips.

[0128] Table name: dws_battery_app_du.

[0129] Data source: Fact table of data related to screen-on time according to usage scenarios.

[0130] The table structure of Table 4 is as follows:

[0131]

[0132]

[0133] Integration of laboratory side and big data side

[0134] Table 5: Energy efficiency data table for designing big data scenarios.

[0135] This table mainly stores the average energy efficiency information of different models (terminal equipment) corresponding to different chips in different scenarios. According to the frequency energy efficiency in Table 2 and the frequency distribution data in Table 3, the comprehensive energy efficiency of the scenario is calculated by weighted summation.

[0136] Table name: dws_cpu_app_efficiency.

[0137] Data sources: Laboratory energy efficiency data table 2, scene frequency distribution data table 3.

[0138] The table structure of Table 5 is as follows:

[0139] Field Name Field meaning Field Type platform Chip Platform String app_name Scenario String efficiency The comprehensive energy efficiency of this scenario is B Floating point numbers

[0140] Table 6: Data table of energy efficiency of the whole big data machine of the design platform.

[0141] This table mainly stores the average energy efficiency information of different chips. According to the average energy efficiency of the scenarios in Table 5 and the distribution data of the scenario duration in Table 4, the comprehensive energy efficiency of the chip is calculated by weighted summation.

[0142] Table name: dws_cpu_total_efficiency.

[0143] Data source: Energy efficiency data table 5 in big data scenarios, user scenario duration distribution table 4.

[0144] The table structure of Table 6 is as follows:

[0145] Field Name Field meaning Field Type platform Chip Platform String efficiency The platform's comprehensive energy efficiency C Floating point numbers

[0146] See also Figure 6 , Figure 6 1 is a schematic diagram of the structure of an embodiment of a chip performance test device provided by the present application. The chip performance test device 60 comprises: a first acquisition module 61 , a second acquisition module 62 and a processing module 63 .

[0147] The first acquisition module 61 acquires a first performance indicator of each frequency point in the target chip, wherein the first performance indicator is obtained by testing the target chip;

[0148] The second acquisition module 62 acquires the frequency distribution and scene proportion in the real scene corresponding to the target chip;

[0149] The processing module 63 performs weighted processing on the first performance indicator using the frequency distribution and the scene proportion to obtain a comprehensive performance indicator of the target chip.

[0150] It can be understood that the first acquisition module 61 , the second acquisition module 62 and the processing module 63 cooperate to implement the method of any of the above embodiments.

[0151] See also Figure 7 , Figure 7 1 is a schematic diagram of the structure of an embodiment of an electronic device provided by the present application. The electronic device 110 includes a processor 111 and a memory 112 coupled to the processor 111; wherein the memory 112 is used to store a computer program, and the processor 111 is used to execute the computer program to implement the following method:

[0152] Obtain a first performance indicator for each frequency point in the target chip, wherein the first performance indicator is obtained by testing the target chip; obtain the frequency point distribution and scene proportion in a real scene corresponding to the target chip; and perform weighted processing on the first performance indicator using the frequency point distribution and scene proportion to obtain a comprehensive performance indicator of the target chip;

[0153] Or, obtain a first comprehensive performance index of the first type of chip, and obtain a second comprehensive performance index of the second type of chip; compare the first comprehensive performance index and the second comprehensive performance index to obtain a comparison result between the first type of chip and the second type of chip.

[0154] It can be understood that the processor 111 is used to execute a computer program to implement the method of any of the above embodiments.

[0155] See also Figure 8 , Figure 8 1 is a schematic diagram of the structure of another embodiment of the electronic device provided by the present application. The electronic device 110 may be, for example, a mobile electronic device, and the electronic device 110 may include: a memory 112, a processor (Central Processing Unit, CPU) 111, a circuit board (not shown in the figure), a power circuit and a microphone 123. The circuit board is placed inside the space surrounded by the shell; the processor 111 and the memory 112 are arranged on the circuit board; the power circuit is used to supply power to various circuits or devices of the electronic device; the memory 112 is used to store executable program codes; the processor 111 runs a computer program corresponding to the executable program code by reading the executable program code stored in the memory 112, so as to implement the method of any of the above embodiments.

[0156] The electronic device may also include: a peripheral interface 114, an RF (Radio Frequency) circuit 116, an audio circuit 117, a speaker 122, a power management chip 119, an input / output (I / O) subsystem 120, other input / control devices 121, a display 124 and an external port 115. These components communicate through one or more communication buses or signal lines 118.

[0157] The memory 112 can be accessed by the processor 111, the peripheral interface 114, etc. The memory 112 can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, or other volatile solid-state storage devices. The peripheral interface 114 can connect the input and output peripherals of the device to the processor 111 and the memory 112.

[0158] The I / O subsystem 120 can connect the input and output peripherals on the device, such as a display 124 and other input / control devices 121, to the peripheral interface 114. The I / O subsystem 120 may include a display controller 1201 and one or more input controllers 1202 for controlling other input / control devices 121. Among them, the one or more input controllers 1202 receive electrical signals from other input / control devices 121 or send electrical signals to other input / control devices 121, and other input / control devices 121 may include physical buttons (press buttons, rocker buttons, etc.), dials, slide switches, joysticks, and click wheels. It is worth noting that the input controller 1202 can be connected to any of the following: a keyboard, an infrared port, a USB interface, and a pointing device such as a mouse.

[0159] The display 124 is an input interface and an output interface between the user electronic device and the user, and displays visual output to the user. The visual output may include graphics, text, icons, videos, etc.

[0160] The display controller 1201 in the I / O subsystem 120 receives an electrical signal from the display 124 or sends an electrical signal to the display 124. The display 124 detects contact on the touch screen, and the display controller 1201 converts the detected contact into interaction with a user interface object displayed on the display 124, that is, realizes human-computer interaction. The user interface object displayed on the display 124 may be an icon for running a game, an icon for connecting to a corresponding network, etc.

[0161] The RF circuit 116 is mainly used to establish communication between the mobile phone and the wireless network (i.e., the network side) to realize data reception and transmission between the mobile phone and the wireless network. For example, sending and receiving short messages, emails, etc. Specifically, the RF circuit 116 receives and sends RF signals, which are also called electromagnetic signals. The RF circuit 116 converts electrical signals into electromagnetic signals or converts electromagnetic signals into electrical signals, and communicates with the communication network and other devices through the electromagnetic signals. The RF circuit 116 may include known circuits for performing these functions, including but not limited to antenna systems, RF transceivers, one or more amplifiers, tuners, one or more oscillators, digital signal processors, CODEC (COder-DECoder, codec) chipsets, Subscriber Identity Module (SIM), etc.

[0162] The audio circuit 117 is mainly used to receive audio data from the peripheral interface 114, convert the audio data into an electrical signal, and send the electrical signal to the speaker 122. The speaker 122 is used to restore the voice signal received by the mobile phone from the wireless network through the RF circuit 116 to sound and play the sound to the user. The power management chip 119 is used to provide power supply and power management for the processor 111, the I / O subsystem 120 and the hardware connected to the peripheral interface 114.

[0163] The above-mentioned electronic device may be a mobile terminal, such as a smart phone, a tablet or other mobile device, or a terminal device, such as a personal computer.

[0164] See also Fig. 9 , Fig. 9 1 is a schematic diagram of a computer readable storage medium according to an embodiment of the present application. The computer readable storage medium 150 stores a computer program 151. When the computer program 151 is executed by a processor, the following method is implemented:

[0165] Obtain a first performance indicator for each frequency point in the target chip, wherein the first performance indicator is obtained by testing the target chip; obtain the frequency point distribution and scene proportion in a real scene corresponding to the target chip; and perform weighted processing on the first performance indicator using the frequency point distribution and scene proportion to obtain a comprehensive performance indicator of the target chip;

[0166] Or, obtain a first comprehensive performance index of the first type of chip, and obtain a second comprehensive performance index of the second type of chip; compare the first comprehensive performance index and the second comprehensive performance index to obtain a comparison result between the first type of chip and the second type of chip.

[0167] It can be understood that when the computer program 151 is executed by a processor, it can also implement the method of any of the above embodiments.

[0168] In summary, the chip performance testing and comparison method, device, electronic device and storage medium provided in the present application obtain the first performance indicator of each frequency point in the target chip, wherein the first performance indicator is obtained by testing the target chip; obtain the frequency distribution and scene proportion corresponding to the target chip in the real scene; use the frequency distribution and scene proportion to weight the first performance indicator to obtain the comprehensive performance indicator of the target chip, which can improve the accuracy of the chip performance indicator.

[0169] Furthermore, this application mainly proposes a cross-chip platform comparative analysis method based on chip (CPU) frequency big data distribution. This solution calculates the comprehensive energy efficiency of the scene by aligning the CPU frequency distribution data of each scene under laboratory energy efficiency test and big data; at the same time, a cross-chip platform metric calculation method is proposed to compare and analyze chips by aligning the energy efficiency of multiple scenes. Specifically, first, the frequency power and computing power of different chips are obtained through laboratory tests to obtain the frequency energy efficiency; then, the chip frequency distribution of the associated scene is weighted to obtain the average chip energy efficiency of the scene; finally, the scene weight (such as the proportion of screen-on time, etc.) is considered to comprehensively calculate the comprehensive energy efficiency of the chip, thereby realizing cross-chip comparison. The advantages and innovations mainly include the following aspects:

[0170] In order to compare different chips, we innovatively combined big data CPU frequency distribution and laboratory energy efficiency data to form a solution to analyze CPU energy efficiency from the perspective of real users. This method has advantages over the original laboratory's independent review of frequency energy efficiency and big data's independent review of frequency distribution and power consumption. This method is helpful to measure the average energy efficiency of existing CPU scheduling from the perspective of real users, provide suggestions on how to optimize energy efficiency, and quantify the impact of CPU frequency scheduling when adjusting the plan.

[0171] The first step of the innovation of this solution is to weight the sum of the energy efficiency index of the laboratory and the CPU frequency point proportion of the scene to obtain the average energy efficiency of the CPU in the scene, which has advantages. After calculating the average energy efficiency, even if the CPU frequency points of different chips are inconsistent, the average energy efficiency can still comprehensively reflect the energy efficiency of the chip, making the comparison between chips intuitive. Therefore, the method of this application is more intuitive and feasible than comparing the frequency point duration distribution of multiple chips, multiple cores and multiple frequency points at the same time. This indicator can measure the power consumption gap required between different chips when achieving the same computing power, and can eliminate some analysis problems caused by different user habits of terminal devices in the same scene. For example, whether the user uses WeChat for video calls or typing chats, it is mainly reflected in the different computing power provided, but the impact on the average energy efficiency is small. Further, the average energy efficiency of the CPU in the scene is multiplied by the corresponding scene weight, such as the proportion of screen-on time, to obtain the overall average CPU energy efficiency of the platform, which has the advantage of being able to smooth out the problem of different user application preferences of terminal devices with different chips, making the overall performance of the terminal device comparable.

[0172] Furthermore, the present application can be combined with a variety of scenarios for comprehensive analysis. The coverage of the scenarios here far exceeds the test cases in the laboratory, and they are the performance of real users, which has practical significance and makes it feasible to intuitively compare the differences between chips.

[0173] The method of this application describes the energy efficiency of the CPU module from the perspective of big data, clarifies the impact of other devices, and can measure CPU power consumption and computing power at the same time. This method can also be extended to other analysis scenarios such as measuring the computing power provided by the CPU per unit time, which is conducive to the disassembly and analysis of CPU power consumption. Furthermore, this application is not only applicable to the analysis of CPU energy efficiency, but can also be used as a reference for the comprehensive computing power and power consumption of the CPU; subsequent quantitative methods for CPU scheduling optimization can be given through relevant analysis, and some suggestions can also be given for CPU scheduling. At the same time, the entire process can also be automated to achieve automated comparison of CPU chip platforms in the big data dimension.

[0174] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device implementation described above is only illustrative, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0175] If the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program codes.

[0176] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A chip performance testing method, characterized in that: The method comprises: Obtaining a first performance indicator for each frequency point in a target chip, wherein the first performance indicator is obtained by testing the target chip; Obtain the frequency distribution and scene proportion in the real scene corresponding to the target chip; The first performance indicator is weighted by using the frequency distribution and the scenario proportion to obtain a comprehensive performance indicator of the target chip.

2. The method according to claim 1, characterized in that The obtaining of the first performance indicator of the target chip includes: Obtaining the frequency point power and frequency point computing power corresponding to each processing core in the target chip; The first performance indicator corresponding to each frequency point in each processing core is obtained by using the frequency point power and the frequency point computing power.

3. The method according to claim 2, characterized in that The obtaining of the frequency point power and frequency point computing power corresponding to each processing core in the target chip includes: Determine the processing cores of the target chip and the frequency points corresponding to each processing core; Get the frequency power and frequency computing power corresponding to each processing core respectively.

4. The method according to claim 3, characterized in that The determining of the processing core of the target chip and the frequency points corresponding to each processing core includes: The processing cores of the target chip and the frequency points corresponding to each processing core are acquired from the architecture information of the target chip.

5. The method according to claim 1, characterized in that The weighted processing of the first performance indicator by using the frequency distribution and the scene proportion to obtain the comprehensive performance indicator of the target chip includes: weighting the first performance indicator using the frequency distribution to obtain a second performance indicator; The second performance indicator is weighted by using the scenario proportion to obtain the comprehensive performance indicator.

6. The method according to claim 1, characterized in that The obtaining of the frequency distribution and the proportion of the scene in the real scene corresponding to the target chip includes: Obtaining the usage time of each frequency point of each core in real scenarios corresponding to multiple target chips; The frequency distribution corresponding to each frequency point of each core in the target scenario is obtained by using the usage time of each frequency point of each core; Get the scene ratio of the target scene.

7. A chip performance comparison method, characterized in that: The method comprises: Obtaining a first comprehensive performance indicator of a first type of chip, and obtaining a second comprehensive performance indicator of a second type of chip; the first comprehensive performance indicator and the second comprehensive performance indicator are obtained according to the method according to any one of claims 1 to 6; The first comprehensive performance index and the second comprehensive performance index are compared to obtain a comparison result between the first type of chip and the second type of chip.

8. A chip performance testing device, characterized in that: The chip performance testing device comprises: A first acquisition module is used to acquire a first performance indicator of each frequency point in a target chip, wherein the first performance indicator is obtained by testing the target chip; The second acquisition module acquires the frequency distribution and scene proportion in the real scene corresponding to the target chip; A processing module performs weighted processing on the first performance indicator using the frequency distribution and the scenario proportion to obtain a comprehensive performance indicator of the target chip.

9. An electronic device, characterized in that: The electronic device includes a processor and a memory coupled to the processor; The memory is used to store a computer program, and the processor is used to execute the computer program to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the computer program implements the method according to any one of claims 1 to 7.

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