Testing method, testing device and testing system for wafer-level ultrasonic chip

Abstract

The invention is applicable to the technical field of semiconductor integrated circuit testing, and provides a wafer-level ultrasonic chip testing method, device and system, and the method comprises the steps: measuring a first echo peak value of a to-be-tested chip when a detachable baffle plate is not arranged at a position, which is a preset distance away from the tip plane of a probe, on a probe card; the first echo peak value is an air echo peak value of the to-be-tested chip, the probe is connected with the to-be-tested chip, and the probe card is connected with the tester through a flat cable; when the probe card is provided with a detachable baffle which is away from the tip plane of the probe by a preset distance, measuring a second echo peak value of the chip to be measured to the detachable baffle; and according to the second echo peak-to-peak value, the first echo peak-to-peak value and a preset peak-to-peak value design parameter, determining an echo peak-to-peak value test result of the to-be-tested chip, the echo peak-to-peak value test result being used for indicating the distance measurement capability of the to-be-tested chip. According to the technical scheme provided by the invention, the testing accuracy of the wafer-level ultrasonic chip is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuit testing technology, and in particular to a testing method, a testing device and a testing system for a wafer-level ultrasonic chip. Background Art

[0002] Ultrasonic ranging chip refers to a chip designed using the ultrasonic time of flight (ToF) measurement principle. With the rapid development and application of robots, smart homes, portable devices, etc., micro-ranging technology has become increasingly important. Compared with traditional radar ranging, laser ranging, infrared ranging and other technical paths, ultrasonic ranging has the advantages of not being affected by the transparency and color of the target object, being insensitive to environmental noise, and having low power consumption, and has been increasingly widely used.

[0003] When testing wafer-level ultrasonic chips, since many chips are densely connected to each other on the same wafer, when the chip to be tested emits ultrasonic waves, other chips on the same wafer are physically connected to the chip to be tested, and other ultrasonic chips will also resonate, thereby generating background noise and affecting the test results. On the other hand, the chip to be tested itself will have a certain amount of background noise in the air, which will also affect the test results, resulting in lower test accuracy.

[0004] Therefore, how to improve the accuracy of wafer-level ultrasonic chip testing has become an urgent problem to be solved. Summary of the invention

[0005] The embodiments of the present application provide a test method, a test device and a test system for a wafer-level ultrasonic chip, aiming to solve the problem of low accuracy in testing wafer-level ultrasonic chips.

[0006] In a first aspect, an embodiment of the present application provides a method for testing a wafer-level ultrasonic chip, the method comprising: in a case where a removable baffle is not provided on the probe card at a preset distance from the needle tip plane of the probe, measuring a first echo peak-to-peak value of the chip to be tested, the first echo peak-to-peak value being the peak-to-peak value of an empty echo of the chip to be tested, the probe being connected to the chip to be tested, and the probe card being connected to a tester via a flat cable; in a case where a removable baffle is provided on the probe card at a preset distance from the needle tip plane of the probe, measuring a second echo peak-to-peak value of the chip to be tested at the removable baffle; determining an echo peak-to-peak value test result of the chip to be tested based on the second echo peak-to-peak value and the first echo peak-to-peak value, as well as preset peak-to-peak value design parameters, the echo peak-to-peak value test result being used to indicate the ranging capability of the chip to be tested.

[0007] In a possible implementation, the echo peak-to-peak value test result of the chip to be tested is determined based on the second echo peak-to-peak value and the first echo peak-to-peak value, as well as preset peak-to-peak value design parameters, including: subtracting the second echo peak-to-peak value from the first echo peak-to-peak value to obtain a target echo peak-to-peak value; and determining the echo peak-to-peak value test result of the chip to be tested based on the target echo peak-to-peak value and the preset peak-to-peak value design parameters.

[0008] In a possible implementation, when no removable baffle is provided at a preset distance from the probe tip plane on the probe card, measuring the peak-to-peak value of the first echo of the chip to be tested includes: sending a sinusoidal wave of a preset frequency to the chip to be tested to determine the first main frequency of the chip to be tested; determining a single cycle time of a first waveform based on the first main frequency of the chip to be tested; based on the single cycle time of the first waveform, performing frequency acquisition of the echo of the chip to be tested for a first preset number of acquisitions to obtain a plurality of first frequency measurement values ​​corresponding to the first preset number of acquisitions; screening out a first target frequency measurement value set from the plurality of first frequency measurement values, the first target frequency measurement value set including the first frequency measurement values ​​corresponding to the echo at the preset distance from the plurality of first frequency measurement values; determining a first wave peak value and a first wave trough value based on the first target frequency measurement value set; determining the first echo peak-to-peak value based on the first wave peak value and the first wave trough value.

[0009] In a possible implementation, when a removable baffle is provided on the probe card at a preset distance from the needle tip plane of the probe, measuring the peak-to-peak value of the second echo of the chip to be tested at the removable baffle includes: sending a sinusoidal wave of a preset frequency to the chip to be tested to determine the second main frequency of the chip to be tested; determining a single cycle time of a second waveform based on the second main frequency of the chip to be tested; based on the single cycle time of the second waveform, performing frequency acquisition of the echo of the chip to be tested for a second preset number of acquisitions to obtain a plurality of second frequency measurement values ​​corresponding to the second preset number of acquisitions; screening out a second target frequency measurement value set from the plurality of second frequency measurement values, the second target frequency measurement value set including the second frequency measurement value corresponding to the echo at the removable baffle in the plurality of second frequency measurement values; determining a second wave peak value and a second wave trough value based on the second target frequency measurement value set; determining the second echo peak-to-peak value based on the second wave peak value and the second wave trough value.

[0010] In a possible implementation, before measuring the first echo peak-to-peak value of the chip to be tested, the method also includes: performing a DC characteristic parameter test on the chip to be tested, the DC characteristic parameter test including an open-short circuit test and a static current test; when the DC characteristic parameter test of the chip to be tested passes, executing the operation of measuring the first echo peak-to-peak value or the second echo peak-to-peak value of the chip to be tested.

[0011] In a possible implementation, the DC characteristic parameter test of the chip to be tested includes: when the voltage of other pins in the chip to be tested except the pin to be tested is a first voltage value, using a pin precision measurement unit to provide a current of a preset intensity for the pin to be tested, and the pin to be tested is a pin in the chip to be tested connected to the probe; using the pin precision measurement unit to measure the target voltage value of the pin to be tested; based on the target voltage value, determining the open and short circuit test result of the chip to be tested, and the open and short circuit test result is used to indicate the connectivity of the pin to be tested.

[0012] In one possible implementation, the DC characteristic parameter test of the chip under test includes: using a pin precision measurement unit to control the chip under test to enter a low power consumption mode; when the chip under test enters the low power consumption mode, measuring a target current value flowing into a drain power supply voltage VDD pin; based on the target current value, determining a static current test result of the chip under test, wherein the static current test result is used to indicate the static power consumption of the chip under test.

[0013] In a possible implementation, the preset distance is 6 centimeters.

[0014] In the second aspect, an embodiment of the present application provides a test device for a wafer-level ultrasonic chip, the device comprising: a measuring module, for measuring a first echo peak-to-peak value of the chip to be tested when a removable baffle is not provided on the probe card at a preset distance from the needle tip plane of the probe, the first echo peak-to-peak value being the peak-to-peak value of the air echo of the chip to be tested, the probe being connected to the chip to be tested, and the probe card being connected to the tester through a flat cable; the measuring module, for measuring a second echo peak-to-peak value of the chip to be tested at a removable baffle provided on the probe card at a preset distance from the needle tip plane of the probe; a determination module, for determining an echo peak-to-peak value test result of the chip to be tested based on the second echo peak-to-peak value and the first echo peak-to-peak value, as well as preset peak-to-peak value design parameters.

[0015] In a third aspect, an embodiment of the present application provides a testing system for a wafer-level ultrasonic chip, the system comprising a probe card and a tester, the probe card being provided with a probe and a removable baffle arranged at a preset distance from the needle tip plane of the probe; the tester being used to execute the method described in the first aspect or any one of the implementations thereof.

[0016] In a fourth aspect, an embodiment of the present application provides a test instrument, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method described in the first aspect or any one of the implementation methods thereof is implemented.

[0017] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method described in the first aspect or any one of the implementation methods thereof is implemented.

[0018] In a sixth aspect, an embodiment of the present application provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, it implements the steps of the method described in the first aspect or any one of the implementation methods thereof.

[0019] Compared with the prior art, the embodiments of the present application have the following beneficial effects: when a detachable baffle is not provided at a preset distance from the probe tip plane on the probe card, the first echo peak-to-peak value of the chip to be tested is measured, the first echo peak-to-peak value is the peak-to-peak value of the air echo of the chip to be tested, the probe is connected to the chip to be tested, and the probe card is connected to the tester through a flat cable; when a detachable baffle is provided at a preset distance from the probe tip plane on the probe card, the second echo peak-to-peak value of the chip to be tested at the detachable baffle is measured; according to the second echo peak-to-peak value and the first echo peak-to-peak value, as well as the preset peak-to-peak value design parameters, the echo peak-to-peak value test result of the chip to be tested is determined. Since the influence of the air echo peak-to-peak value of the chip to be tested is taken into account when measuring the echo peak-to-peak value of the chip to be tested, that is, the influence of the background noise generated by the chip resonance and the background noise of the chip itself to the air is taken into account, rather than just measuring the echo peak-to-peak value of the chip to be tested at the preset distance to determine the test result, the technical solution provided by the present application can improve the accuracy of wafer-level ultrasonic chip testing.

[0020] It can be understood that the wafer-level ultrasonic chip testing device, testing system, tester, computer-readable storage medium and computer program product provided in the embodiments of the present application have the same beneficial effects as the above-mentioned wafer-level ultrasonic chip testing method, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of the architecture of a wafer-level ultrasonic chip testing system provided in one embodiment of the present application;

[0023] Figure 2 A physical diagram of a probe card 110 provided in one embodiment of the present application;

[0024] Figure 3 A peripheral circuit schematic diagram of a probe card 110 provided in one embodiment of the present application;

[0025] Figure 4 A schematic flow chart of a method for testing a wafer-level ultrasonic chip provided in one embodiment of the present application;

[0026] Figure 5 A schematic flow chart of another wafer-level ultrasonic chip testing method provided in one embodiment of the present application;

[0027] Figure 6 A schematic diagram of an open-short circuit test provided by an embodiment of the present application;

[0028] Figure 7 A schematic diagram of another open-short circuit test provided by an embodiment of the present application;

[0029] Figure 8 A structural block diagram of a wafer-level ultrasonic chip testing device provided in one embodiment of the present application;

[0030] Fig. 9 A schematic diagram of the structure of a tester provided in one embodiment of the present application. DETAILED DESCRIPTION

[0031] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0032] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0033] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0034] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0035] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0036] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0037] Ultrasonic ranging chip refers to a chip designed using the ToF measurement principle. With the rapid development and application of robots, smart homes, and portable devices, micro-ranging technology has become increasingly important. Compared with traditional radar ranging, laser ranging, infrared ranging and other technical paths, ultrasonic ranging has the advantages of not being affected by the transparency and color of the target object, being insensitive to environmental noise, and having low power consumption.

[0038] At present, there are two technical difficulties in ultrasonic chip wafer-level testing: on the one hand, wafer-level testing has many chips densely connected to each other on the same wafer. When the chip to be tested emits ultrasonic waves, other chips on the same wafer are physically connected to the chip to be tested, and other ultrasonic chips will also resonate, thereby generating background noise and affecting the test results; on the other hand, the chip to be tested itself will have a certain amount of background noise in the air, which will also affect the test results. In addition, the probe card for ultrasonic chip wafer-level testing is also different in structure from the probe card for conventional chip testing, and requires additional design and production of reflective baffles.

[0039] In order to solve the above technical problems, the present application proposes a testing method for wafer-level ultrasonic chips. When a removable baffle is not provided at a preset distance from the needle tip plane of the probe on the probe card, the first echo peak-to-peak value of the chip to be tested is measured, where the first echo peak-to-peak value is the peak-to-peak value of the air echo of the chip to be tested. The probe is connected to the chip to be tested, and the probe card is connected to the tester through a cable. When a removable baffle is provided at a preset distance from the needle tip plane of the probe on the probe card, the second echo peak-to-peak value of the chip to be tested at the removable baffle is measured. According to the second echo peak-to-peak value and the first echo peak-to-peak value, as well as the preset peak-to-peak value design parameters, the echo peak-to-peak value test result of the chip to be tested is determined, and the echo peak-to-peak value test result is used to indicate the ranging capability of the chip to be tested, thereby improving the accuracy of wafer-level ultrasonic chip testing.

[0040] For ease of understanding, the technical solution of the present application will be described in detail below with reference to the accompanying drawings.

[0041] Figure 1 A schematic diagram of the architecture of a wafer-level ultrasonic chip testing system provided in one embodiment of the present application is shown in FIG. Figure 1 As shown, the wafer-level ultrasonic chip testing system 100 includes a probe card 110 and a tester 120 . The probe card 110 is provided with a probe 111 and a detachable baffle 112 disposed at a preset distance from the tip plane of the probe 111 .

[0042] Specifically, the probe card 110 is a medium for connecting the chip to be tested and the tester 120 , on which the peripheral circuits required for testing the chip to be tested are designed. The probes 111 contact the pin pads on the chip to be tested and are connected to the tester 120 using cables.

[0043] As an example, a physical diagram of the probe card 110 can be found in Figure 2 The schematic diagram of the peripheral circuit of the probe card 110 can be found in Figure 3 .

[0044] Specifically, the tester 120 is used to perform direct current (DC) parameter test and echo peak-to-peak test on the chip to be tested, wherein the DC parameter test includes open-short (OS) test and static current test.

[0045] As an example, the tester 120 uses the Chroma 3380P tester, which is a digital-analog hybrid tester, including multiplex bus (MXBUS), multiplex logic pin control (MXLPC), multiplex AWI2 (MXAWI2), multiplex pulse generator 3 (MXPG3) and other boards. The MXBUS board is usually used to provide signals for controlling relays; the pin precision measurement unit (PPMU) and precision measurement unit (PMU) resources on the MXLPC board can perform operations such as adding current to measure pressure, adding pressure to measure current, etc. The main difference between PPMU and PMU is the different test accuracy and range; the time measurement unit (TMU) tests frequency and time-related parameters; the MXAWI2 board provides a waveform generator (WG) mode and a waveform digitizer (WD) mode. In WG mode, the tester can send a sine wave with a preset frequency. In WD mode, the tester can sample the echo of the sine wave. For example, the fastest sending and sampling rate is 50 nanoseconds (ns).

[0046] Exemplarily, the tester 120 uses the PPMU on the MXLPC board to perform a DC parameter test on the chip under test, and uses the WG mode and the WD mode on the MXAWI2 board to perform an echo peak-to-peak value test on the chip under test.

[0047] In a possible implementation, the wafer-level ultrasonic chip testing system 100 further includes a probe station, which is used to place the wafer on which the chip to be tested is located, and to accurately move the wafer so that the chip to be tested contacts the probe 111 .

[0048] Understandably, Figure 1The system architecture shown is only an example of the wafer-level ultrasonic chip test system provided by the present application. In other embodiments of the present application, the wafer-level ultrasonic chip test system 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware, and the present application does not limit this.

[0049] Figure 4 A flow chart of a method for testing a wafer-level ultrasonic chip provided in an embodiment of the present application. For ease of explanation, only the part related to the present embodiment is shown. The method provided in the present embodiment is applied to Figure 1 The wafer-level ultrasonic chip testing system 100 shown is executed by a tester 120. The method provided in this embodiment includes the following steps:

[0050] S410, when no removable baffle is provided at a preset distance from the needle tip plane of the probe on the probe card, the first echo peak-to-peak value of the chip to be tested is measured, the first echo peak-to-peak value is the peak-to-peak value of the air echo of the chip to be tested, the probe is connected to the chip to be tested, and the probe card is connected to the tester through a cable.

[0051] Specifically, wafer testing is between wafer manufacturing and packaging in the entire chip production process. It tests every chip on the entire wafer. The chip to be tested is an ultrasonic chip connected to a probe among multiple chips on the wafer.

[0052] In a specific implementation, a removable baffle is not provided at a preset distance from the probe tip plane on the probe card, and the WG mode and WD mode in the MXAWI2 board are used to measure the first echo peak-to-peak value of the chip to be tested. Since a removable baffle is not provided at the preset position on the probe card at this time, the measured first echo peak-to-peak value is the peak-to-air echo peak-to-peak value of the chip to be tested. The peak-to-air echo peak-to-peak value indicates the background noise generated by the resonance of other chips on the same wafer with the chip to be tested, as well as the background noise of the chip to be tested itself.

[0053] Preferably, the preset distance is 6 centimeters (cm).

[0054] S420, in a case where a detachable baffle plate which is at a preset distance from a probe tip plane is provided on the probe card, measuring a peak value of a second echo of the chip to be tested at the detachable baffle plate.

[0055] In a specific implementation, when a removable baffle is provided on the probe card at a preset distance from the needle tip plane of the probe, the WG mode and WD mode in the MXAWI2 board are used to measure the second echo peak-to-peak value of the chip to be tested at the removable baffle, that is, the echo peak-to-peak value of the chip to be tested at the preset position.

[0056] It should be noted that the present application does not limit the execution order of S210 and S220, that is, the first echo peak-to-peak value of the chip to be tested can be measured first, and then the second echo peak-to-peak value of the chip to be tested can be measured; or the second echo peak-to-peak value of the chip to be tested can be measured first, and then the first echo peak-to-peak value of the chip to be tested can be measured.

[0057] S430, determining an echo peak-to-peak value test result of the chip to be tested according to the second echo peak-to-peak value and the first echo peak-to-peak value, as well as preset peak-to-peak value design parameters, wherein the echo peak-to-peak value test result is used to indicate the ranging capability of the chip to be tested.

[0058] Specifically, different types of chips to be tested correspond to different preset peak-to-peak value design parameters, the preset peak-to-peak value design parameters include a preset range of the echo peak-to-peak value, and the echo peak-to-peak value test results include pass and fail.

[0059] In the specific implementation, the preset peak-to-peak value design parameters corresponding to the chip to be tested are first determined, and then the second echo peak-to-peak value and the first echo peak-to-peak value of the chip to be tested obtained by measuring are compared with the preset peak-to-peak value design parameters corresponding to the chip to be tested to determine the echo peak-to-peak value test result of the chip to be tested.

[0060] The technical solution provided in this embodiment measures the first echo peak-to-peak value of the chip to be tested when no detachable baffle is provided at a preset distance from the probe tip plane on the probe card, the first echo peak-to-peak value is the peak-to-peak value of the air echo of the chip to be tested, the probe is connected to the chip to be tested, and the probe card is connected to the tester through a flat cable; when a detachable baffle is provided at a preset distance from the probe tip plane on the probe card, the second echo peak-to-peak value of the chip to be tested at the detachable baffle is measured; according to the second echo peak-to-peak value and the first echo peak-to-peak value, as well as the preset peak-to-peak value design parameters, the echo peak-to-peak value test result of the chip to be tested is determined. Since the influence of the air echo peak-to-peak value of the chip to be tested is taken into account when measuring the echo peak-to-peak value of the chip to be tested, that is, the influence of the background noise generated by the chip resonance and the background noise of the chip itself to the air is taken into account, rather than just measuring the echo peak-to-peak value of the chip to be tested at the preset distance to determine the test result, the technical solution provided in this application can improve the accuracy of wafer-level ultrasonic chip testing.

[0061] On the basis of the above embodiment, this embodiment further illustrates and optimizes the technical solution. Specifically, in this embodiment, according to the peak-to-peak value of the second echo and the peak-to-peak value of the first echo, and the preset peak-to-peak value design parameters, the peak-to-peak value test result of the echo of the chip to be tested is determined, including:

[0062] Subtract the peak value of the second echo from the peak value of the first echo to obtain the peak value of the target echo;

[0063] Based on the target echo peak-to-peak value and the preset peak-to-peak value design parameters, the echo peak-to-peak value test result of the chip to be tested is determined.

[0064] In a specific implementation, the peak value of the second echo is subtracted from the peak value of the first echo to obtain a target echo peak value, which is the echo peak value corresponding to the preset position after eliminating the resonance background noise of other chips on the same wafer and the chip to be tested and the air background noise of the chip to be tested itself. The target echo peak value is then compared with the preset peak-to-peak value design parameters corresponding to the chip to be tested to determine the echo peak-to-peak value test result of the chip to be tested.

[0065] As an example, the preset peak-to-peak value design parameter corresponding to the chip to be tested is the echo peak-to-peak value preset range. When the target echo peak-to-peak value is within the echo peak-to-peak value preset range, the echo peak-to-peak value test result of the chip to be tested is determined to be passed; when the target echo peak-to-peak value is not within the echo peak-to-peak value preset range, the echo peak-to-peak value test result of the chip to be tested is determined to be failed.

[0066] The technical solution provided in this embodiment subtracts the second echo peak-to-peak value of the chip to be tested from the first echo peak-to-peak value to obtain a target echo peak-to-peak value that eliminates the resonant background noise of other chips on the same wafer and the chip to be tested and the air background noise of the chip to be tested itself, and then determines the echo peak-to-peak value test result of the chip to be tested based on the comparison between the target echo peak-to-peak value and the preset peak-to-peak value design parameters, thereby improving the accuracy of the echo peak-to-peak value test.

[0067] Based on the above embodiment, this embodiment further illustrates and optimizes the technical solution. Specifically, in this embodiment, when no detachable baffle is provided at a preset distance from the needle tip plane of the probe on the probe card, the peak value of the first echo of the chip to be tested is measured, including:

[0068] Sending a sine wave of a preset frequency to the chip under test to determine the first main frequency of the chip under test;

[0069] Determine a single cycle time of the first waveform based on a first main frequency of the chip to be tested;

[0070] Based on a single cycle time of the first waveform, frequency acquisition is performed for a first preset acquisition number of times on the echo of the chip to be tested, to obtain a plurality of first frequency measurement values ​​corresponding to the first preset acquisition number of times;

[0071] Filtering out a first target frequency measurement value set from the plurality of first frequency measurement values, the first target frequency measurement value set including first frequency measurement values ​​corresponding to the echo at the preset distance from the plurality of first frequency measurement values;

[0072] Determining a first peak value and a first trough value based on the first target frequency measurement value set;

[0073] Based on the first wave peak value and the first wave trough value, a first echo peak-to-peak value is determined.

[0074] In the specific implementation, the preset frequency is 800 kilohertz (Khz), and the first preset number of acquisitions is 5 times. When a removable baffle is not set at the preset distance from the probe tip plane on the probe card, the WG mode of the MXAWI2 board is used to send an 800Khz sine wave to the chip under test, and the WD mode is used to measure the frequency of the echo of the sine wave from the chip under test 10 times to obtain 10 frequency measurement values, and these 10 frequency measurement values ​​are stored in the FREQ

[10] array, and the FREQ

[10] array is traversed to take out the mode and store it in the min variable, and the mode of the 10 frequency measurement values ​​is confirmed as the first main frequency of the chip under test; since the main frequency and the single cycle time of the waveform are reciprocal to each other, then based on the first main frequency of the chip under test, the single cycle time of the first waveform can be obtained; based on the single cycle time of the first waveform, the WD mode of the MXAWI2 board is used to measure the frequency of the echo of the sine wave from the chip under test 5 times, and each of the 5 measurements is captured 9 at an interval of 50ns. 000 times, 9000 first frequency measurement values ​​are obtained, and 5 groups of 9000 first frequency measurement values ​​are obtained in total from 5 measurements; since 6cm corresponds to an echo within the time range of 370us to 410us, the first frequency measurement values ​​of the 7400th to 8200th captures in each group of 9000 captures are screened out and stored in the data

[800] array, and 5 data

[800] arrays, i.e., the first target frequency measurement value sets, are obtained. Each data

[800] array is traversed, the maximum value (i.e., the first wave peak value) is taken out and stored in the MAX_VALUE1[5] array, the minimum value (i.e., the first wave trough value) is taken out and stored in the MAX_VALUE2[5] array, the time point corresponding to the first wave peak value is stored in the MAX_TIME1[5] array, and the time point corresponding to the first wave trough value is stored in the MAX_TIME2[5] array. Store the peak-to-peak value in each of the five data

[800] arrays in MAX_VALUE[5], traverse the MAX_VALUE[5] array, take out the maximum value as the peak-to-peak value of the first echo, and store it in the MAX_VALUE_final variable. Correspondingly, store the peak value corresponding to the peak-to-peak value of the first echo and the time point of the peak in MAX_VALUE3 and MAX_TIME3 respectively, and store the trough value corresponding to the peak-to-peak value of the first echo and the time point of the trough in MAX_VALUE4 and MAX_TIME4 respectively.

[0075] The technical solution provided in this embodiment, when measuring the first main frequency of the chip to be tested, due to the instability of the measured waveform, the first main frequency of the chip to be tested is determined by measuring the frequencies of the echo of the sine wave of the chip to be tested 10 times and taking the mode, thereby improving the accuracy of determining the first main frequency of the chip to be tested; when measuring the peak-to-peak value of the first echo of the chip to be tested, due to the relative stability of the echo of the chip to be tested in the empty state, the frequencies of the echo of the sine wave of the chip to be tested are only measured 5 times, thereby improving the efficiency of determining the peak-to-peak value of the first echo of the chip to be tested.

[0076] Based on the above embodiments, this embodiment further illustrates and optimizes the technical solution. Specifically, in this embodiment, when a detachable baffle with a preset distance from the probe tip plane is provided on the probe card, measuring the peak value of the second echo of the chip to be tested at the detachable baffle includes:

[0077] Sending a sine wave of a preset frequency to the chip under test to determine the second main frequency of the chip under test;

[0078] Determine a single cycle time of the second waveform based on a second main frequency of the chip to be tested;

[0079] Based on a single cycle time of the second waveform, frequency acquisition is performed for a second preset acquisition number of times on the echo of the chip to be tested, to obtain a plurality of second frequency measurement values ​​corresponding to the second preset acquisition number of times;

[0080] Filtering out a second target frequency measurement value set from the plurality of second frequency measurement values, the second target frequency measurement value set including second frequency measurement values ​​corresponding to the echo at the detachable baffle among the plurality of second frequency measurement values;

[0081] determining a second wave peak and a second wave trough based on the second target frequency measurement value set;

[0082] Based on the second echo peak value and the second echo trough value, a second echo peak-to-peak value is determined.

[0083] In a specific implementation, the preset frequency is 800Khz, and the second preset number of acquisition times is 50 times. When a removable baffle with a preset distance from the probe tip plane is provided on the probe card, the WG mode of the MXAWI2 board is used to send an 800Khz sine wave to the chip under test, and the WD mode is used to measure the frequency of the echo of the sine wave from the chip under test 10 times to obtain 10 frequency measurement values, and the 10 frequency measurement values ​​are stored in the FREQ

[10] array, the FREQ

[10] array is traversed, the mode thereof is taken out and stored in the min variable, and the mode of the 10 frequency measurement values ​​is confirmed as the second main frequency of the chip under test; since the main frequency and the single cycle time of the waveform are reciprocal to each other, the single cycle time of the second waveform can be obtained based on the second main frequency of the chip under test; based on the single cycle time of the second waveform, the WD mode of the MXAWI2 board is used to measure the frequency of the echo of the sine wave from the chip under test 50 times, and each measurement in the 50 measurements is captured 9000 times at an interval of 50ns to obtain 9000 second frequency measurement values, and a total of 50 measurements 50 groups of 9000 second frequency measurement values ​​are obtained. Since the removable baffle at a distance of 6 cm corresponds to an echo within the time range of 370us to 410us, the second frequency measurement values ​​of the 7400th to 8200th captures in each group of 9000 captures are stored in the data_6cm

[800] array, and a total of 50 data_6cm

[800] arrays, i.e., the second target frequency measurement value set, are obtained. Each of the 50 data_6cm

[800] arrays is traversed, the maximum value (i.e., the second wave peak value) is taken out and stored in the MAX_VALUE1_6cm

[50] array, the minimum value (i.e., the second wave trough value) is taken out and stored in the MAX_VALUE2_6cm

[50] array, the time point corresponding to the wave peak is stored in the MAX_TIME1_6cm

[50] array, and the time point corresponding to the wave trough is stored in the MAX_TIME2_6cm

[50] array. Store the peak-to-peak value of each of the 50 data_6cm

[800] arrays in MAX_VALUE_6cm

[50] , traverse the MAX_VALUE

[50] _6cm array, take out the maximum value as the peak-to-peak value of the second echo of the chip to be tested, and store it in the MAX_VALUE_final_6cm variable. Correspondingly, store the peak corresponding to the peak-to-peak value of the second echo and the time point of the peak in MAX_VALUE3_6cm and MAX_TIME3_6cm respectively, and store the trough corresponding to the peak-to-peak value of the second echo and the time point of the trough in MAX_VALUE4_6cm and MAX_TIME_6cm4 respectively.

[0084] The technical solution provided in this embodiment measures the peak-to-peak value of the second echo of the chip to be tested by measuring the frequency of the echo of the sine wave of the chip to be tested 50 times, because the echo of the chip to be tested at the 6 cm removable baffle is relatively unstable, thereby improving the accuracy of determining the peak-to-peak value of the second echo of the chip to be tested.

[0085] Figure 5 A flowchart of another wafer-level ultrasonic chip testing method provided in one embodiment of the present application. Figure 5 As shown, before measuring the peak-to-peak value of the first echo of the chip to be tested, the method further includes:

[0086] Conduct DC characteristic parameter test on the chip under test, including open-short circuit test and static current test;

[0087] When the DC characteristic parameter test of the chip to be tested passes, an operation of measuring the first echo peak-to-peak value or the second echo peak-to-peak value of the chip to be tested is performed.

[0088] In the specific implementation, PPMU is first used to perform DC parameter tests such as open-short circuit test and static current test on the chip to be tested. If the DC parameter test of the chip to be tested fails, the test is stopped; when the DC parameter test of the chip to be tested passes, the echo peak-to-peak value test is performed, that is, the operation of measuring the first echo peak-to-peak value or the second echo peak-to-peak value of the chip to be tested is executed. If the echo peak-to-peak value test of the chip to be tested passes, the chip to be tested is qualified; if the echo peak-to-peak value test of the chip to be tested fails, the chip to be tested is unqualified.

[0089] The technical solution provided in this embodiment first performs a DC parameter test on the chip to be tested, and then performs an echo peak value test after the DC parameter test passes. This can detect defective chips as early as possible and terminate the test in time, shortening the test time and improving the efficiency of chip testing.

[0090] Based on the above embodiment, this embodiment further illustrates and optimizes the technical solution. Specifically, in this embodiment, a DC characteristic parameter test is performed on the chip to be tested, including:

[0091] When the voltage of other pins of the chip under test except the pin under test is a first voltage value, a pin precision measurement unit is used to provide a current of a preset intensity for the pin under test, where the pin under test is a pin of the chip under test connected to the probe;

[0092] Use the pin precision measurement unit to measure the target voltage value of the pin to be tested;

[0093] Based on the target voltage value, the open and short circuit test result of the chip to be tested is determined, and the open and short circuit test result is used to indicate the connectivity of the pin to be tested.

[0094] Specifically, the OS test is used to confirm that all signal pins are electrically connected to the corresponding channels of the test system when the chip under test is tested, and no signal pin is short-circuited with other signal pins, power supply or ground. The OS test performs an open and short circuit check on the input and output (IO) pins of the chip under test when the chip under test is not powered on.

[0095] In a possible implementation, the first voltage value is 0 volt (V), the preset intensity is -100 microamperes (uA), and the connectivity test between the pin to be tested and the ground or other pins is tested.

[0096] In the specific implementation, Figure 6 As shown, PPMU is used to set the voltages of all pins of the chip under test except the pin to be tested to 0V; a current of -100uA is provided to the pin to be tested; the target voltage value on the pin to be tested is measured; when the target voltage value is around -0.7V or within the range of (-1.5V, -0.2V), it is determined that the pin to be tested is in good contact with the tester and the probe card, and that the pin to be tested itself does not have any open circuit or short circuit to the power pin, ground pin or other IO pin; if the target voltage value is a large negative voltage, for example, less than -1.5V, it means that the pin to be tested has an open circuit to the ground; if the target voltage value is close to 0V or greater than -0.2V, it means that the pin to be tested is short-circuited to the power pin, ground pin, or other IO pin.

[0097] In another possible implementation, the first voltage value is 0V, the preset intensity is +100uA, and the connectivity between the chip under test and the VDD pin or other pins is tested.

[0098] In the specific implementation, Figure 7 As shown, PPMU is used to set the voltages of all pins except the pin to be tested in the chip to 0V; a +100uA current is provided to the pin to be tested; the target voltage value on the pin to be tested is measured; when the target voltage value is around 0.7V or within the range of (0.2V, 1.5V), it is determined that the pin to be tested is in good contact with the tester and the probe card, and that the pin to be tested itself does not have any open circuit or short circuit to the power pin, ground pin or other IO pin; if the target voltage value is a large positive voltage, for example, greater than 1.5V, it means that the pin to be tested has an open circuit fault to the corresponding power pin; if the target voltage value is close to 0V or less than 0.2V, it means that the pin to be tested is short-circuited to the power pin, ground pin or other IO pin.

[0099] The technical solution provided in this embodiment uses a pin precision measurement unit to complete the open and short circuit test in the DC parameter test, tests the connectivity of the pin to be tested, and improves the accuracy of chip detection.

[0100] Based on the above embodiment, this embodiment further illustrates and optimizes the technical solution. Specifically, in this embodiment, a DC characteristic parameter test is performed on the chip to be tested, including:

[0101] Use the pin precision measurement unit to control the chip under test to enter low power consumption mode;

[0102] When the chip under test enters low power mode, measure the target current value flowing into the drain power supply voltage VDD pin;

[0103] Based on the target current value, a static current test result of the chip under test is determined, and the static current test result is used to indicate the static power consumption of the chip under test.

[0104] Specifically, the static current test usually presets the chip under test to a specific state, such as low power mode or sleep mode, and then measures the current flowing into the VDD pin, and compares the measured value with the preset parameters to determine whether the chip under test is normal.

[0105] In the specific implementation, PPMU is used to provide 3.3V voltage to the VDD pin of the chip under test, so that the chip under test enters low power consumption mode; the target current value flowing into the VDD pin is measured; the preset range of the static current is set to (-0.5uA, 10uA), when the target current value is within the preset range of the static current, the static current test result of the chip under test is passed; when the target current value is not within the preset range of the static current, the static current test result of the chip under test is failed.

[0106] The technical solution provided in this embodiment uses PPMU to complete the static current test in the DC parameter test, tests the static power consumption of the chip to be tested, and improves the accuracy of chip detection.

[0107] Figure 8 This is a structural block diagram of a wafer-level ultrasonic chip testing device provided in one embodiment of the present application. For the sake of convenience, only the parts related to the embodiment of the present application are shown. Figure 8 The wafer-level ultrasonic chip testing device 800 may include a measuring module 801 and a determining module 802 .

[0108] The measuring module 801 is used to measure the first echo peak-to-peak value of the chip to be tested when no detachable baffle is provided at a preset distance from the needle tip plane of the probe on the probe card, where the first echo peak-to-peak value is the peak-to-peak value of the air echo of the chip to be tested, the probe is connected to the chip to be tested, and the probe card is connected to the tester through a flat cable;

[0109] The measuring module 801 is further used to measure the peak value of the second echo of the chip to be tested at the detachable baffle when a detachable baffle with a preset distance from the probe tip plane is provided on the probe card;

[0110] The determination module 802 is used to determine the echo peak-to-peak value test result of the chip to be tested according to the second echo peak-to-peak value and the first echo peak-to-peak value, as well as preset peak-to-peak value design parameters.

[0111] A wafer-level ultrasonic chip testing device provided in an embodiment of the present application has the same beneficial effects as the above-mentioned wafer-level ultrasonic chip testing method.

[0112] In one embodiment, the determining module 802 includes:

[0113] A first determination submodule is used to subtract the peak-to-peak value of the second echo from the peak-to-peak value of the first echo to obtain the peak-to-peak value of the target echo;

[0114] The second determination submodule is used to determine the echo peak-to-peak value test result of the chip to be tested based on the target echo peak-to-peak value and the preset peak-to-peak value design parameters.

[0115] In one embodiment, the measurement module 801 includes:

[0116] A first main frequency determination submodule, used for sending a sine wave of a preset frequency to the chip to be tested to determine a first main frequency of the chip to be tested;

[0117] A first waveform single cycle time determination submodule, used to determine a first waveform single cycle time based on a first main frequency of the chip to be tested;

[0118] A first frequency acquisition submodule, configured to perform frequency acquisition of a first preset number of times on the echo of the chip to be tested based on a single cycle time of the first waveform, and obtain a plurality of first frequency measurement values ​​corresponding to the first preset number of acquisitions;

[0119] A first data screening submodule, configured to screen out a first target frequency measurement value set from the plurality of first frequency measurement values, wherein the first target frequency measurement value set includes first frequency measurement values ​​corresponding to the echo at the preset distance from the plurality of first frequency measurement values;

[0120] A first peak value determination submodule, configured to determine a first wave peak value and a first wave valley value based on a first target frequency measurement value set;

[0121] The first echo peak-to-peak value determination submodule is used to determine the first echo peak-to-peak value based on the first wave peak value and the first wave valley value.

[0122] In one embodiment, the measurement module 801 includes:

[0123] A second main frequency determination submodule, used for sending a sine wave of a preset frequency to the chip to be tested to determine the second main frequency of the chip to be tested;

[0124] A second waveform single cycle time determination submodule, used to determine a second waveform single cycle time based on a second main frequency of the chip to be tested;

[0125] A second frequency acquisition submodule is used to perform frequency acquisition of the echo of the chip to be tested for a second preset number of acquisitions based on a single cycle time of the second waveform, and obtain a plurality of second frequency measurement values ​​corresponding to the second preset number of acquisitions;

[0126] A second data screening submodule, used to screen out a second target frequency measurement value set from the plurality of second frequency measurement values, wherein the second target frequency measurement value set includes second frequency measurement values ​​corresponding to the echo at the detachable baffle among the plurality of second frequency measurement values;

[0127] A second peak value determination submodule, used to determine a second wave peak value and a second wave valley value based on a second target frequency measurement value set;

[0128] The second echo peak-to-peak value determination submodule is used to determine the second echo peak-to-peak value based on the second wave peak value and the second wave trough value.

[0129] In one embodiment, the wafer-level ultrasonic chip testing device 800 further includes:

[0130] The DC characteristic parameter test module performs DC characteristic parameter test on the chip under test. The DC characteristic parameter test includes open-short circuit test and static current test.

[0131] In one embodiment, the DC characteristic parameter test module includes:

[0132] The current providing submodule is used to provide a current of a preset intensity for the pin to be tested by using the pin precision measurement unit when the voltage of other pins of the chip to be tested except the pin to be tested is a first voltage value, and the pin to be tested is the pin of the chip to be tested connected to the probe;

[0133] The target voltage value measurement submodule is used to measure the target voltage value of the pin to be tested by using the pin precision measurement unit;

[0134] The open-short circuit test submodule is used to determine the open-short circuit test result of the chip to be tested based on the target voltage value. The open-short circuit test result is used to indicate the connectivity of the pin to be tested.

[0135] In one embodiment, the DC characteristic parameter test module includes:

[0136] The control submodule is used to control the chip under test to enter a low power consumption mode by using the pin precision measurement unit;

[0137] The target current value measurement submodule is used to measure the target current value flowing into the drain power supply voltage VDD pin when the chip under test enters the low power consumption mode;

[0138] The static current test submodule is used to determine the static current test result of the chip to be tested based on the target current value, and the static current test result is used to indicate the static power consumption of the chip to be tested.

[0139] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0140] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0141] Fig. 9 This is a schematic diagram of the structure of a tester provided in one embodiment of the present application. Fig. 9 As shown, the tester 9 of this embodiment includes: at least one processor 90 ( Fig. 9 Only one is shown), a memory 91 and a computer program 92 stored in the memory 91 and executable on at least one processor 90, the processor 90 executes the computer program 92 to implement the above Figure 4 or Figure 5 The steps in the method embodiment, or the implementation of the above Figure 8 Functions of each module / unit in the device embodiment.

[0142] As an example, the tester 9 may be Figure 1 Tester 120 in.

[0143] The tester 9 may include but is not limited to a processor 90 and a memory 91. Those skilled in the art will appreciate that Fig. 9 This is only an example of the tester 9 and does not constitute a limitation on the tester 9. The tester 9 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0144] The processor 90 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0145] In some embodiments, the memory 91 may be an internal storage unit of the tester 9, such as a hard disk or memory of the tester 9. In other embodiments, the memory 91 may also be an external storage device of the tester 9, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the tester 9. Furthermore, the memory 91 may also include both an internal storage unit of the tester 9 and an external storage device. The memory 91 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as program codes of computer programs. The memory 91 may also be used to temporarily store data that has been output or is to be output.

[0146] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0147] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Wherein, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying the computer program code to the tester, a recording medium, a computer memory, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), an electric carrier signal, a telecommunication signal and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a disk or an optical disk.

[0148] A computer-readable storage medium provided in an embodiment of the present application has the same beneficial effects as the above-mentioned method for testing a wafer-level ultrasonic chip.

[0149] An embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0150] A computer program product provided in an embodiment of the present application has the same beneficial effects as the above-mentioned method for testing a wafer-level ultrasonic chip.

[0151] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0152] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0153] In the embodiments provided in the present application, it should be understood that the disclosed device / tester and method can be implemented in other ways. For example, the device / tester embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0154] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0155] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for testing a wafer-level ultrasonic chip, characterized in that: The method comprises: In the case where no detachable baffle is provided at a preset distance from the needle tip plane of the probe on the probe card, measuring the first echo peak-to-peak value of the chip to be tested, wherein the first echo peak-to-peak value is the peak-to-peak value of the air echo of the chip to be tested, the probe is connected to the chip to be tested, and the probe card is connected to the tester through a flat cable; In a case where a detachable baffle plate which is at a preset distance from the needle tip plane of the probe is provided on the probe card, measuring the peak value of the second echo of the chip to be tested at the detachable baffle plate; According to the second echo peak-to-peak value and the first echo peak-to-peak value, and preset peak-to-peak value design parameters, an echo peak-to-peak value test result of the chip to be tested is determined, and the echo peak-to-peak value test result is used to indicate the ranging capability of the chip to be tested.

2. The method according to claim 1, characterized in that The step of determining the echo peak-to-peak value test result of the chip to be tested according to the second echo peak-to-peak value and the first echo peak-to-peak value, as well as preset peak-to-peak value design parameters, comprises: Subtracting the peak-to-peak value of the second echo from the peak-to-peak value of the first echo to obtain the peak-to-peak value of the target echo; Based on the target echo peak-to-peak value and the preset peak-to-peak value design parameter, an echo peak-to-peak value test result of the chip to be tested is determined.

3. The method according to claim 1, characterized in that The method of measuring the peak-to-peak value of the first echo of the chip to be tested when no detachable baffle is provided at a preset distance from the needle tip plane of the probe on the probe card comprises: Sending a sine wave of a preset frequency to the chip under test to determine a first main frequency of the chip under test; Determine a single cycle time of a first waveform based on a first main frequency of the chip to be tested; Based on a single cycle time of the first waveform, frequency acquisition is performed on the echo of the chip to be tested for a first preset acquisition number of times, to obtain a plurality of first frequency measurement values ​​corresponding to the first preset acquisition number of times; Filtering out a first target frequency measurement value set from the plurality of first frequency measurement values, wherein the first target frequency measurement value set includes first frequency measurement values ​​corresponding to the echo at the preset distance among the plurality of first frequency measurement values; determining a first wave peak value and a first wave valley value based on the first target frequency measurement value set; The first echo peak-to-peak value is determined based on the first echo peak value and the first echo trough value.

4. The method according to claim 1, characterized in that: In the case where a detachable baffle plate which is at a preset distance from the needle tip plane of the probe is provided on the probe card, measuring the peak value of the second echo of the chip to be tested at the detachable baffle plate comprises: Sending a sine wave of a preset frequency to the chip under test to determine a second main frequency of the chip under test; Determine a single cycle time of a second waveform based on a second main frequency of the chip to be tested; Based on a single cycle time of the second waveform, frequency acquisition is performed on the echo of the chip to be tested for a second preset acquisition number of times, to obtain a plurality of second frequency measurement values ​​corresponding to the second preset acquisition number of times; Filtering out a second target frequency measurement value set from the plurality of second frequency measurement values, the second target frequency measurement value set including second frequency measurement values ​​corresponding to the echo at the detachable baffle among the plurality of second frequency measurement values; determining a second wave peak value and a second wave trough value based on the second target frequency measurement value set; The second echo peak-to-peak value is determined based on the second echo peak value and the second echo trough value.

5. The method according to any one of claims 1 to 4, characterized in that: Before measuring the peak value of the first echo of the chip to be tested, the method further includes: Performing a DC characteristic parameter test on the chip to be tested, wherein the DC characteristic parameter test includes an open-short circuit test and a static current test; When the DC characteristic parameter test of the chip under test passes, the operation of measuring the first echo peak-to-peak value or the second echo peak-to-peak value of the chip under test is performed.

6. The method according to claim 5, characterized in that The DC characteristic parameter test of the chip to be tested includes: When the voltage of other pins of the chip under test except the pin under test is a first voltage value, a pin precision measurement unit is used to provide a current of a preset intensity to the pin under test, wherein the pin under test is a pin of the chip under test connected to the probe; Measuring the target voltage value of the pin to be tested by using the pin precision measurement unit; Based on the target voltage value, an open-short circuit test result of the chip to be tested is determined, and the open-short circuit test result is used to indicate the connectivity of the pin to be tested.

7. The method according to claim 5, characterized in that The DC characteristic parameter test of the chip to be tested includes: Using the pin precision measurement unit to control the chip under test to enter a low power consumption mode; When the chip under test enters a low power consumption mode, measuring a target current value flowing into a drain power supply voltage VDD pin; Based on the target current value, a static current test result of the chip under test is determined, and the static current test result is used to indicate the static power consumption of the chip under test.

8. The method according to any one of claims 1 to 4, characterized in that: The preset distance is 6 cm.

9. A wafer-level ultrasonic chip testing device, characterized in that: The device comprises: A measuring module, for measuring a first echo peak-to-peak value of a chip to be tested when no detachable baffle is provided at a preset distance from a needle tip plane of the probe on the probe card, wherein the first echo peak-to-peak value is an air echo peak-to-peak value of the chip to be tested, the probe is connected to the chip to be tested, and the probe card is connected to a tester via a flat cable; The measuring module is further used for measuring the peak value of the second echo of the chip to be tested at the detachable baffle plate when a detachable baffle plate with a preset distance from the needle tip plane of the probe is provided on the probe card; The determination module is used to determine the echo peak-to-peak value test result of the chip to be tested according to the second echo peak-to-peak value and the first echo peak-to-peak value, as well as preset peak-to-peak value design parameters.

10. A wafer-level ultrasonic chip testing system, characterized in that: The system comprises a probe card and a tester, wherein the probe card is provided with a probe and a detachable baffle plate arranged at a preset distance from a needle tip plane of the probe; The tester is used to perform the method according to any one of claims 1 to 8.

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