Sparse representation chaff interference resisting algorithm based on FPGA

Abstract

The invention discloses an FPGA (Field Programmable Gate Array)-based sparse representation chaff interference resisting algorithm, which comprises the following steps of: 1, training chaff signal echo data, target signal echo data and mixed echo signal data with different speeds, directions and distances by using a K-SVD (K-Singular Value Decomposition) algorithm to obtain three corresponding sparse dictionaries; 2, simulating to obtain any echo signal Y, and converting the echo signal Y to serve as an input signal of a top module; 3, three OMP modules are arranged according to different used sparse dictionaries, each OMP module reconstructs a signal obtained through MATLAB simulation through the used sparse dictionary, and the error between the reconstructed signal and an original signal is calculated; and 4, in the sparse representation module, comparing the reconstruction errors output by the three OMP modules, and distinguishing echo signal types by comparing the reconstruction errors of the three dictionaries output by the OMP modules. According to the invention, the echo signal can be effectively identified.

Description

Technical Field

[0001] The invention belongs to the technical field of radio fuze interference, and in particular relates to a sparse representation anti-chaff interference algorithm based on FPGA. Background Art

[0002] Wickerhauser MV and Coifman RR proposed the concept of sparse decomposition in Entropy-based algorithms for best basis selection, believing that the sparser the signal decomposition, the closer it can be to the fundamental structure of the signal.

[0003] In the 1990s, Zhifeng Z and Mallat SG proposed the idea of ​​decomposing signals on an overcomplete dictionary (or sparse dictionary) in Matching pursuits with time-frequency dictionaries. The idea is to find the elements that are most similar to the signal to be decomposed in the overcomplete dictionary, with the number of elements being as small as possible, and use these elements to reconstruct the signal to obtain a sparse representation of the signal. This operation process is called sparse decomposition.

[0004] David LD et al. verified in Sparse Solution of Underdetermined Systems of LinearEquations by Stagewise Orthogonal Matching Pursuit that the OMP algorithm has fast convergence speed and good reconstruction effect.

[0005] Chaff is the earliest and most effective jammer in passive jamming technology. How to effectively counteract chaff interference is a problem that needs to be solved. Summary of the invention

[0006] The present invention aims to provide a sparse representation anti-chaff interference algorithm based on FPGA, which can effectively identify echo signals.

[0007] The scheme of the present invention to achieve the above object is:

[0008] A sparse representation anti-chaff interference algorithm based on FPGA includes the following steps:

[0009] Step 1: Use the K-SVD algorithm to train the chaff signal echo data, target signal echo data, and mixed echo signal data with different speeds, azimuths, and distances to obtain the corresponding three sparse dictionaries, which are respectively counted as sparse dictionaries D 1 , D 2 , D 3, using three ROMs to store three sparse dictionaries respectively, and using the three dictionaries as inputs of a sparse representation module, the sparse representation module functions including: calling corresponding three OMP modules according to the three sparse dictionaries respectively, and identifying incoming wave signals according to reconstruction errors;

[0010] Step 2: Use MATLAB simulation to obtain any echo signal Y, and after conversion, use it as the input signal of the top-level module. The functions of the top-level module include: using the IP core to generate the required clock, using IBUFDS to perform differential processing on the input signal, setting a triangle wave signal for synchronization with FFT, and using the differentially processed data as input to call the sparse representation module;

[0011] Step 3: According to the different sparse dictionaries used, three OMP modules are set, each of which reconstructs the signal obtained by the above MATLAB simulation by using the sparse dictionary used, and calculates the error between the reconstructed signal and the original signal;

[0012] Step 4: In the sparse representation module, the reconstruction errors output by the three OMP modules are compared. The echo signal type is distinguished by comparing the reconstruction errors of the three dictionaries output by the OMP modules. If the reconstruction error output by the target dictionary is the smallest, the echo signal is identified as the target signal; if the reconstruction error output by the chaff dictionary is the smallest, the echo signal is identified as the chaff signal; if the reconstruction error output by the mixed dictionary is the smallest, the echo signal is identified as a mixed signal, thereby realizing the fuze's anti-chaff interference.

[0013] Furthermore, the step 3 is specifically as follows:

[0014] The inverse matrix module is called and the orthogonal matching pursuit algorithm is used to complete the reconstruction of the input signal and calculate the reconstruction error. Each OMP module uses a three-stage state machine, which is divided into twelve states. The twelve states of the OMP module are:

[0015] IDLE state: reset state, after receiving the enable signal, it switches to INIT state;

[0016] INIT state: initialization state, initialize the residual signal resi to the echo signal Y, initialize the maximum value sequence to 0, initialize the sparse signal A to the input signal Y, initialize the error threshold, and then switch to PROJ state after completion;

[0017] PROJ state: projection coefficient calculation state, sparse dictionary D x The transposed matrix of is multiplied by the residual signal resi to obtain the projection coefficient vector, and then converted to COMP state, where x is 1, 2 or 3;

[0018] COMP state: maximum value calculation state, compare the projection coefficient vectors, get the maximum value and its corresponding position number, store it in the maximum value vector, and convert to INDX state after completion;

[0019] INDX state: vector selection state, according to the maximum value vector, select the corresponding sparse dictionary column vector, and then convert to PINV state after completion;

[0020] PINV state: inverse matrix calculation state, call the inverse matrix calculation module to calculate the inverse matrix of the matrix composed of some sparse dictionary column vectors, and then switch to XTEM state after completion;

[0021] XTEM state: matrix multiplication state, multiply the above inverse matrix by the sparse signal A on the right to obtain a new sparse signal, and then switch to the YTEM state after completion;

[0022] YTEM state: matrix multiplication state, calculate D x *A, after completion, switch to RESD state;

[0023] RESD state: Update residual state: According to the formula resi=YD x *A updates the residual signal and switches to the ERRO state after completion;

[0024] ERRO state: error calculation state: call the two-norm module to calculate the two-norm square value of the residual signal, that is, the reconstruction error, and determine whether it is lower than the set error threshold. If it is lower than the threshold and has not reached the maximum number of cycles, it will switch to the OUTP state, otherwise it will switch to the PROJ state for looping;

[0025] OUTP state: output state. When the error of the reconstructed signal is less than the threshold or reaches the maximum number of cycles, it switches to the FINI state.

[0026] FINI state: completion state, output sparse matrix and reconstruction error, and output valid signal. After completion, reset the OMP module for the next call.

[0027] Furthermore, the inverse matrix calculation module mainly calls the SVD module and performs matrix multiplication to complete the inverse matrix calculation, converts the input enable signal pulse into a level signal as the module internal enable signal, first calls the SVD module to complete the singular value decomposition of the input matrix, obtains the unitary matrix U, V and the diagonal matrix S, and then according to the formula:

[0028] H=USV -1 , H is any M*N order matrix;

[0029] Among them: U is an M-order square matrix, V is an N-order square matrix, and both U matrix and V matrix are unitary matrices, that is, U HU=I、V H V = I, Σ is an N-order diagonal matrix with non-negative diagonal elements, and S is an M×N matrix composed of Σ, that is:

[0030]

[0031] For a unitary matrix, V -1 =V * , where V * is the conjugate transpose of V, the matrix elements are real numbers, V * =V T At this time, the formula H = USV -1 It is expressed as:

[0032] H=USV T

[0033] The generalized inverse matrix of H is expressed as:

[0034] H + =VS + U -1 =VS + U T =V[Σ -1 ,0]U T

[0035] Among them, Σ -1 That is, take the inverse of the diagonal elements of Σ, and finding the generalized inverse matrix is ​​converted into calculating the singular value decomposition of the matrix;

[0036] get Call the Divider IP core, take the V matrix elements and the corresponding S matrix diagonal elements as input, and calculate V T ×S -1 ;

[0037] Then call the multiplier IP core to calculate the inverse matrix, and output the calculation result and valid signal after the calculation is completed. Then reset the inverse matrix module for the next call.

[0038] Furthermore, the singular value decomposition module that calculates the SVD decomposition call mainly uses the one-sided Jacobi algorithm and the ring sequence to perform singular value decomposition on the input signal. The SVD module uses a three-stage state machine, which is divided into ten states:

[0039] IDLE state: reset state, after receiving the enable signal, it switches to INIT state;

[0040] INIT state: initialization state, initialize U and V matrices; initialize ring sequences A and B; calculate the square of the bi-norm of the row vector of the input matrix, and switch to DEGR state after the calculation is completed;

[0041] DEGR state: angle calculation state, according to the ring sequences a and b, calculate the inner product γ of the two row vectors of the matrix, as well as their respective bi-norms α and β; according to the formula Calculate tan2θ, θ, sinθ and cosθ. After the calculation is completed, switch to MULT state;

[0042] MULT state: multiplication calculation state, respectively calculate V[a i ]×cosθ,V[a i ]×(-sinθ), V[a j ]×cosθ,V[a j ]×sinθ,U[a i ]×cosθ,U[a i ]×(-sinθ),U[a j ]×cosθ,U[a j ]×sinθ, after the calculation is completed, it is converted to UPDA state;

[0043] UPDA state: update state, update U matrix and V matrix; update ring sequences a and b; update the square of the row vector bi-norm, and then switch to COUN state;

[0044] COUN state: counting state, judging whether all row operations are completed, if completed, switching to ERRO state, otherwise switching to DEGR state;

[0045] ERRO state: error calculation state, judging whether the error is lower than the set threshold. If it is lower than the threshold or the number of repetitions reaches the maximum value, it will be converted to OUTP state, otherwise it will be converted to ITER state;

[0046] ITER state: Iteration state, reinitialize the ring sequences a and b, and then switch to DEGR state after completion;

[0047] OUTP state: output state, calculate the output matrix U matrix, S matrix, V matrix, and convert to FINI state after completion;

[0048] FINI state: completion state, keeps U matrix, S matrix, V matrix, and outputs valid signals. After completion, it switches to INIT state and resets the SVD module for the next call.

[0049] Furthermore, the two-norm module can convert the input enable signal pulse into a level signal as an internal enable signal of the two-norm module, store the input data to prevent external data from changing during calculation, and define a counter in the two-norm module to count the number of loops. According to the length of the input data, the multiplier IP core is called cyclically to calculate the square value of each data, and the multiplier calculation result is accumulated through the accumulator to obtain the sum of the squares of the input signals, which is the square of the two-norm. After the calculation is completed, the calculation result and the valid signal are output, and then the module is reset for the next call.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] (1) At present, most of the research on foil anti-interference is in the theoretical analysis stage. The present invention implements the sparse representation anti-foil interference algorithm on FPGA and verifies the feasibility of the algorithm; (2) The OMP algorithm and the one-sided Jacobi algorithm of the ring sequence are used to reduce the redundancy of calculation, and it has strong real-time performance and high recognition rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is the overall process framework diagram of the present invention.

[0053] Figure 2 This is the state diagram of the OMP module.

[0054] Figure 3 This is the state diagram of the SVD module.

[0055] Figure 4 This is the calling relationship diagram of each module. DETAILED DESCRIPTION

[0056] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0057] Combination Figure 1 , a sparse representation anti-chaff interference algorithm based on FPGA, comprising the following steps:

[0058] Step 1: Use the K-SVD algorithm to train the chaff signal echo data, target signal echo data, and mixed echo signal data with different speeds, azimuths, and distances to obtain the corresponding three sparse dictionaries, which are respectively counted as sparse dictionaries D 1 , D2 , D 3 , using three ROMs to store three sparse dictionaries respectively, and using the three dictionaries as inputs of a sparse representation module, the sparse representation module functions including: calling corresponding three OMP modules according to the three sparse dictionaries respectively, and identifying incoming wave signals according to reconstruction errors;

[0059] Step 2: Use MATLAB simulation to obtain any echo signal Y, and after conversion, use it as the input signal of the top-level module. The functions of the top-level module include: using the IP core to generate the required clock, using IBUFDS to perform differential processing on the input signal, setting a triangle wave signal for synchronization with FFT, and using the differentially processed data as input to call the sparse representation module;

[0060] Step 3: According to the different sparse dictionaries used, three OMP modules are set, each of which reconstructs the signal obtained by the above MATLAB simulation by using the sparse dictionary used, and calculates the error between the reconstructed signal and the original signal;

[0061] Step 4: In the sparse representation module, the reconstruction errors output by the three OMP modules are compared. The target dictionary has strong reconstruction capability for target signals and small reconstruction error, but weak reconstruction capability for chaff and mixed signals and large reconstruction error; the chaff dictionary has weak reconstruction capability for target signals and large reconstruction error, and the reconstruction results for chaff and mixed signals are quite different; the mixed dictionary has weak reconstruction capability for target signals and large reconstruction error, and the reconstruction results for chaff and mixed signals are quite different. By comparing the reconstruction errors of the three dictionaries output by the OMP module, the echo signal type is distinguished. If the reconstruction error output by the target dictionary is the smallest, the echo signal is identified as the target signal; if the reconstruction error output by the chaff dictionary is the smallest, the echo signal is identified as the chaff signal; if the reconstruction error output by the mixed dictionary is the smallest, the echo signal is identified as the mixed signal, thereby realizing the fuze's anti-chaff interference.

[0062] Furthermore, the step 3 is specifically as follows:

[0063] The inverse matrix module is called and the orthogonal matching pursuit algorithm is used to complete the reconstruction of the input signal and calculate the reconstruction error. Each OMP module uses a three-stage state machine, which is divided into twelve states. Figure 2 , the twelve states of the OMP module are:

[0064] IDLE state: reset state, after receiving the enable signal, it switches to INIT state;

[0065] INIT state: initialization state, initialize the residual signal resi to the echo signal Y, initialize the maximum value sequence to 0, initialize the sparse signal A to the input signal Y, initialize the error threshold, and then switch to PROJ state after completion;

[0066] PROJ state: projection coefficient calculation state, sparse dictionary D x The transposed matrix of is multiplied by the residual signal resi to obtain the projection coefficient vector, and then converted to COMP state, where x is 1, 2 or 3;

[0067] COMP state: maximum value calculation state, compare the projection coefficient vectors, get the maximum value and its corresponding position number, store it in the maximum value vector, and convert to INDX state after completion;

[0068] INDX state: vector selection state, according to the maximum value vector, select the corresponding sparse dictionary column vector, and then convert to PINV state after completion;

[0069] PINV state: inverse matrix calculation state, call the inverse matrix calculation module to calculate the inverse matrix of the matrix composed of some sparse dictionary column vectors, and then switch to XTEM state after completion;

[0070] XTEM state: matrix multiplication state, multiply the above inverse matrix by the sparse signal A on the right to obtain a new sparse signal, and then switch to the YTEM state after completion;

[0071] YTEM state: matrix multiplication state, calculate D x *A, after completion, switch to RESD state;

[0072] RESD state: Update residual state: According to the formula resi=YD x *A updates the residual signal and switches to the ERRO state after completion;

[0073] ERRO state: error calculation state: call the two-norm module to calculate the two-norm square value of the residual signal, that is, the reconstruction error, and determine whether it is lower than the set error threshold. If it is lower than the threshold and has not reached the maximum number of cycles, it will switch to the OUTP state, otherwise it will switch to the PROJ state for looping;

[0074] OUTP state: output state. When the error of the reconstructed signal is less than the threshold or reaches the maximum number of cycles, it switches to the FINI state.

[0075] FINI state: completion state, output sparse matrix and reconstruction error, and output valid signal. After completion, reset the OMP module for the next call.

[0076] Furthermore, the inverse matrix calculation module mainly calls the SVD module and performs matrix multiplication to complete the inverse matrix calculation, converts the input enable signal pulse into a level signal as the module internal enable signal, first calls the SVD module to complete the singular value decomposition of the input matrix, obtains the unitary matrix U, V and the diagonal matrix S, and then according to the formula:

[0077] H=USV -1 , H is any M*N order matrix;

[0078] Among them: U is an M-order square matrix, V is an N-order square matrix, and both U matrix and V matrix are unitary matrices, that is, U H U=I、V H V = I, Σ is an N-order diagonal matrix with non-negative diagonal elements, and S is an M×N matrix composed of Σ, that is:

[0079]

[0080] For a unitary matrix, V -1 =V * , where V * is the conjugate transpose of V, the matrix elements are real numbers, V * =V T At this time, the formula H = USV -1 It is expressed as:

[0081] H=USV T

[0082] The generalized inverse matrix of H is expressed as:

[0083] H + =VS + U -1 =VS + U T =V[Σ -1 ,0]U T

[0084] Among them, Σ -1 That is, take the inverse of the diagonal elements of Σ, and finding the generalized inverse matrix is ​​converted into calculating the singular value decomposition of the matrix;

[0085] get Call the Divider IP core, take the V matrix elements and the corresponding S matrix diagonal elements as input, and calculate V T ×S -1 ;

[0086] Then call the multiplier IP core to calculate the inverse matrix, and output the calculation result and valid signal after the calculation is completed. Then reset the inverse matrix module for the next call.

[0087] Furthermore, the singular value decomposition module that calculates the SVD decomposition call mainly uses the one-sided Jacobi algorithm and the ring sequence to perform singular value decomposition on the input signal. The SVD module uses a three-stage state machine, combined with Figure 3 , divided into ten states:

[0088] IDLE state: reset state, after receiving the enable signal, it switches to INIT state;

[0089] INIT state: initialization state, initialize U and V matrices; initialize ring sequences a and b; calculate the square of the bi-norm of the row vector of the input matrix, and switch to DEGR state after the calculation is completed;

[0090] DEGR state: angle calculation state, according to the ring sequences a and b, calculate the inner product γ of the two row vectors of the matrix, as well as their respective bi-norms α and β; according to the formula Calculate tan2θ, θ, sinθ and cosθ. After the calculation is completed, switch to MULT state;

[0091] MULT state: multiplication calculation state, respectively calculate V[a i ]×cosθ,V[a i ]×(-sinθ), V[a j ]×cosθ,V[a j ]×sinθ,U[a i ]×cosθ,U[a i ]×(-sinθ),U[a j ]×cosθ,U[a j ]×sinθ, after the calculation is completed, it is converted to UPDA state;

[0092] UPDA state: update state, update U matrix and V matrix; update ring sequences a and b; update the square of the row vector bi-norm, and then switch to COUN state;

[0093] COUN state: counting state, judging whether all row operations are completed, if completed, switching to ERRO state, otherwise switching to DEGR state;

[0094] ERRO state: error calculation state, judging whether the error is lower than the set threshold. If it is lower than the threshold or the number of repetitions reaches the maximum value, it will be converted to OUTP state, otherwise it will be converted to ITER state;

[0095] ITER state: Iteration state, reinitialize the ring sequences a and b, and then switch to DEGR state after completion;

[0096] OUTP state: output state, calculate the output matrix U matrix, S matrix, V matrix, and convert to FINI state after completion;

[0097] FINI state: completion state, keeps U matrix, S matrix, V matrix, and outputs valid signals. After completion, it switches to INIT state and resets the SVD module for the next call.

[0098] Furthermore, the two-norm module can convert the input enable signal pulse into a level signal as an internal enable signal of the two-norm module, store the input data to prevent external data from changing during calculation, and define a counter in the two-norm module to count the number of loops. According to the length of the input data, the multiplier IP core is called cyclically to calculate the square value of each data, and the multiplier calculation result is accumulated through the accumulator to obtain the sum of the squares of the input signals, which is the square of the two-norm. After the calculation is completed, the calculation result and the valid signal are output, and then the module is reset for the next call. Figure 4 This is the calling relationship diagram of each module.

[0099] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A sparse representation anti-chaff interference algorithm based on FPGA, characterized in that: The following steps are involved: Step 1: Use the K-SVD algorithm to train the chaff signal echo data, target signal echo data and mixed echo signal data with different speeds, azimuths and distances, and obtain three corresponding sparse dictionaries, which are respectively counted as sparse dictionaries D1, D2 and D3. Use three ROMs to store the three sparse dictionaries respectively, and use the three dictionaries as inputs of the sparse representation module. The functions of the sparse representation module include: calling the corresponding three OMP modules according to the three sparse dictionaries respectively, and identifying the incoming wave signal according to the reconstruction error; Step 2: Use MATLAB simulation to obtain any echo signal Y, and after conversion, use it as the input signal of the top-level module. The functions of the top-level module include: using the IP core to generate the required clock, using IBUFDS to perform differential processing on the input signal, setting a triangle wave signal for synchronization with FFT, and using the differentially processed data as input to call the sparse representation module; Step 3: According to the different sparse dictionaries used, three OMP modules are set, each of which reconstructs the signal obtained by the above MATLAB simulation by using the sparse dictionary used, and calculates the error between the reconstructed signal and the original signal; Step 4: In the sparse representation module, the reconstruction errors output by the three OMP modules are compared. The echo signal type is distinguished by comparing the reconstruction errors of the three dictionaries output by the OMP modules. If the reconstruction error output by the target dictionary is the smallest, the echo signal is identified as the target signal; if the reconstruction error output by the chaff dictionary is the smallest, the echo signal is identified as the chaff signal; if the reconstruction error output by the mixed dictionary is the smallest, the echo signal is identified as a mixed signal, thereby realizing the fuze's anti-chaff interference.

2. The FPGA-based sparse representation anti-chaff interference algorithm according to claim 1, characterized in that: The step 3 is specifically as follows: The inverse matrix module is called and the orthogonal matching pursuit algorithm is used to complete the reconstruction of the input signal and calculate the reconstruction error. Each OMP module uses a three-stage state machine, which is divided into twelve states. The twelve states of the OMP module are: IDLE state: reset state, after receiving the enable signal, it switches to INIT state; INIT state: initialization state, initialize the residual signal resi to the echo signal Y, initialize the maximum value sequence to 0, initialize the sparse signal A to the input signal Y, initialize the error threshold, and then switch to PROJ state after completion; PROJ state: projection coefficient calculation state, sparse dictionary D x The transposed matrix of is multiplied by the residual signal resi to obtain the projection coefficient vector, and then converted to COMP state, where x is 1, 2 or 3; COMP state: maximum value calculation state, compare the projection coefficient vectors, get the maximum value and its corresponding position number, store it in the maximum value vector, and convert to INDX state after completion; INDX state: vector selection state, according to the maximum value vector, select the corresponding sparse dictionary column vector, and then convert to PINV state after completion; PINV state: inverse matrix calculation state, call the inverse matrix calculation module to calculate the inverse matrix of the matrix composed of some sparse dictionary column vectors, and then switch to XTEM state after completion; XTEM state: matrix multiplication state, multiply the above inverse matrix by the sparse signal A on the right to obtain a new sparse signal, and then switch to the YTEM state after completion; YTEM state: matrix multiplication state, calculate D x *A, after completion, switch to RESD state; RESD state: Update residual state: According to the formula resi=YD x *A updates the residual signal and switches to the ERRO state after completion; ERRO state: error calculation state: call the two-norm module to calculate the two-norm square value of the residual signal, that is, the reconstruction error, and determine whether it is lower than the set error threshold. If it is lower than the threshold and has not reached the maximum number of cycles, it will switch to the OUTP state, otherwise it will switch to the PROJ state for looping; OUTP state: output state. When the error of the reconstructed signal is less than the threshold or reaches the maximum number of cycles, it switches to the FINI state. FINI state: completion state, output sparse matrix and reconstruction error, and output valid signal. After completion, reset the OMP module for the next call.

3. The FPGA-based sparse representation anti-chaff interference algorithm according to claim 2, characterized in that: The inverse matrix calculation module mainly calls the SVD module and performs matrix multiplication to complete the inverse matrix calculation, converts the input enable signal pulse into a level signal as the module internal enable signal, first calls the SVD module to complete the singular value decomposition of the input matrix, obtains the unitary matrix U, V and the diagonal matrix S, and then according to the formula: H=USV -1 , H is any M*N order matrix; Among them: U is an M-order square matrix, V is an N-order square matrix, and both U matrix and V matrix are unitary matrices, that is, U H U=I、V H V = I, Σ is an N-order diagonal matrix with non-negative diagonal elements, and S is an M×N matrix composed of Σ, that is: For a unitary matrix, V -1 =V * , where V * is the conjugate transpose of V, the matrix elements are real numbers, V * =V T At this time, the formula H = USV -1 It is expressed as: H=USV T The generalized inverse matrix of H is expressed as: H + =VS + U -1 =VS + U T =V[Σ -1 ,0]U T Among them, Σ -1 That is, take the inverse of the diagonal elements of Σ, and finding the generalized inverse matrix is ​​converted into calculating the singular value decomposition of the matrix; get Call the Divider IP core, take the V matrix elements and the corresponding S matrix diagonal elements as input, and calculate V T ×S -1 ; Then call the multiplier IP core to calculate the inverse matrix, and output the calculation result and valid signal after the calculation is completed. Then reset the inverse matrix module for the next call.

4. The FPGA-based sparse representation anti-chaff interference algorithm according to claim 3 is characterized in that: The singular value decomposition module used to calculate the SVD decomposition mainly uses the one-sided Jacobi algorithm and the ring sequence to perform singular value decomposition on the input signal. The SVD module uses a three-stage state machine, which is divided into ten states: IDLE state: reset state, after receiving the enable signal, it switches to INIT state; INIT state: initialization state, initialize U and V matrices; initialize ring sequences a and b; calculate the square of the bi-norm of the row vector of the input matrix, and switch to DEGR state after the calculation is completed; DEGR state: angle calculation state, according to the ring sequences a and b, calculate the inner product γ of the two row vectors of the matrix, as well as their respective bi-norms α and β; according to the formula Calculate tan2θ, θ, sinθ and cosθ. After the calculation is completed, switch to MULT state; MULT state: multiplication calculation state, respectively calculate V[a i ]×cosθ,V[a i ]×(-sinθ), V[a j ]×cosθ,V[a j ]×sinθ,U[a i ]×cosθ,U[a i ]×(-sinθ),U[a j ]×cosθ,U[a j ]×sinθ, after the calculation is completed, it is converted to UPDA state; UPDA state: update state, update U matrix and V matrix; update ring sequences a and b; update the square of the row vector bi-norm, and then switch to COUN state; COUN state: counting state, judging whether all row operations are completed, if completed, switching to ERRO state, otherwise switching to DEGR state; ERRO state: error calculation state, judging whether the error is lower than the set threshold. If it is lower than the threshold or the number of repetitions reaches the maximum value, it will be converted to OUTP state, otherwise it will be converted to ITER state; ITER state: Iteration state, reinitialize the ring sequences a and b, and then switch to DEGR state after completion; OUTP state: output state, calculate the output matrix U matrix, S matrix, V matrix, and convert to FINI state after completion; FINI state: completion state, keeps U matrix, S matrix, V matrix, and outputs valid signals. After completion, it switches to INIT state and resets the SVD module for the next call.

5. The FPGA-based sparse representation anti-chaff interference algorithm according to claim 4 is characterized in that: The two-norm module can convert the input enable signal pulse into a level signal as the internal enable signal of the two-norm module, store the input data to prevent external data from changing during calculation, define a counter in the two-norm module to count the number of cycles, and call the multiplier IP core cyclically according to the length of the input data to calculate the square value of each data. At the same time, the multiplier calculation result is accumulated through the accumulator to obtain the square sum of the input signal, which is the square of the two-norm. After the calculation is completed, the calculation result and the valid signal are output, and then the module is reset for the next call.

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