Memory control method, memory storage device and memory control circuit unit

Abstract

The invention provides a memory control method, a memory storage device and a memory control circuit unit, which are used for a rewritable nonvolatile memory module. The method comprises the following steps: judging the load degree of a rewritable nonvolatile memory module; determining a pause interval among the plurality of pause instructions according to the load degree; and sequentially issuing a pause instruction to the rewritable nonvolatile memory module according to the pause interval. The pause instruction is used for enabling the rewritable nonvolatile memory module to pause the currently executed operation so as to execute the read operation. The time interval from the end of the read operation to the reception of the next pause instruction is greater than or equal to the pause interval. Therefore, the overall efficiency can be improved by dynamically adjusting the pause interval.

Description

Technical Field

[0001] The present disclosure relates to a memory control method, and more particularly to a memory control method for adjusting a suspend instruction interval, a memory storage device, and a memory control circuit unit. Background Art

[0002] Portable electronic devices such as mobile phones and notebook computers have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into the various portable electronic devices listed above because they have the characteristics of data non-volatility, power saving, small size, and no mechanical structure.

[0003] Rewritable non-volatile memory modules can perform operations such as writing (also known as programming), reading, and erasing. When performing an erase or write operation, the read operation cannot be performed. Some rewritable non-volatile memory modules can also receive a suspend instruction. If a suspend instruction is received during a write or erase operation, the currently executed write or erase operation will be temporarily stopped, and the read operation will be performed first, and then the write or erase operation will be resumed. In order to avoid frequent suspension of write or erase operations, it can be set that after receiving a suspend instruction, a time interval must be waited before the next suspend instruction can be received. The size of this time interval will affect the performance of various operations. Summary of the invention

[0004] In order to solve the above problems, the present invention proposes a memory control method, a memory storage device and a memory control circuit unit, which can dynamically determine the pause interval between multiple pause instructions according to the load level of the rewritable non-volatile memory module, thereby reducing the delay of reading instructions and improving the overall performance of the system.

[0005] An embodiment of the present invention provides a memory control method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units. The method includes: determining the load level of the rewritable non-volatile memory module; determining the pause interval between a plurality of pause instructions according to the load level; and sequentially issuing pause instructions to the rewritable non-volatile memory module according to the pause interval. The pause instruction is used to cause the rewritable non-volatile memory module to pause the currently executed operation to perform a read operation. The time interval from the end of the read operation to the receipt of the next pause instruction is greater than or equal to the pause interval.

[0006] In one embodiment, the memory control method further comprises: determining whether the load level of the rewritable non-volatile memory module is a light load or a heavy load. The step of determining the pause interval between the pause instructions according to the load level comprises: if the load level is a light load, reducing the pause interval; and if the load level is a heavy load, increasing the pause interval.

[0007] In one embodiment, the above operation is an erase operation, and the pause interval is an erase pause interval. The step of determining whether the load level of the rewritable non-volatile memory module is a light load or a heavy load includes: receiving a write instruction from a host system and storing the write instruction in a buffer memory; when the free memory space of the buffer memory is greater than or equal to a first buffer threshold, determining that the load level is a light load; and when the free memory space of the buffer memory is less than or equal to a second buffer threshold, determining that the load level is a heavy load, wherein the second buffer threshold is less than the first buffer threshold.

[0008] In one embodiment, the memory control method further includes: when the free memory space of the buffer memory is less than the first buffer threshold and greater than the second buffer threshold, maintaining the pause interval unchanged.

[0009] In one embodiment, the above operation is a write operation, and the pause interval is a write pause interval. The step of determining whether the load level of the rewritable non-volatile memory module is a light load or a heavy load includes: receiving a command from a host system, adding the command to a command queue; if the occupancy rate of the command queue is greater than a first queue threshold, determining that the load level is a heavy load; and if the occupancy rate of the command queue is less than a second queue threshold, determining that the load level is a light load.

[0010] In one embodiment, the above operation is a write operation, and the pause interval is a write pause interval. The step of determining whether the load level of the rewritable non-volatile memory module is a light load or a heavy load includes: calculating the write speed of the host system; if the write speed is less than a first write threshold, determining the load level is a light load; and if the write speed is greater than a second write threshold, determining the load level is a heavy load.

[0011] In one embodiment, when the rewritable non-volatile memory module resumes operation from the suspend command, the rewritable non-volatile memory module first undergoes a warm-up period before executing the operation. The memory control method further includes: in response to the number of read commands issued by the host system being greater than the number of write commands, setting the suspend interval to be less than the warm-up period.

[0012] From another perspective, an embodiment of the present invention proposes a memory storage device, comprising: a connection interface unit for coupling to a host system; a rewritable non-volatile memory module, comprising a plurality of physical units; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to perform a plurality of steps: determining the load level of the rewritable non-volatile memory module; determining the pause interval between a plurality of pause instructions according to the load level; and sequentially issuing pause instructions to the rewritable non-volatile memory module according to the pause interval. The pause instruction is used to cause the rewritable non-volatile memory module to pause the currently executed operation to perform a read operation. The time interval from the end of the read operation to the receipt of the next pause instruction is greater than or equal to the pause interval.

[0013] From another perspective, an embodiment of the present invention proposes a memory control circuit unit for controlling a rewritable non-volatile memory module, which includes a plurality of physical units. The memory control circuit unit includes: a host interface for coupling to a host system; a memory interface for coupling to a rewritable non-volatile memory module; and a memory management circuit coupled to the host interface and the memory interface. The memory management circuit is used to perform a plurality of steps: determining the load level of the rewritable non-volatile memory module; determining the pause interval between a plurality of pause instructions according to the load level; and sequentially issuing pause instructions to the rewritable non-volatile memory module according to the pause interval. The pause instruction is used to cause the rewritable non-volatile memory module to pause the currently executed operation to perform a read operation, wherein the time interval from the end of the read operation to the receipt of the next pause instruction is greater than or equal to the pause interval.

[0014] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0016] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0017] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0018] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0019] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0020] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0021] Figure 7 is a timing diagram showing execution of a pause instruction according to an embodiment of the present invention;

[0022] Figure 8 is a timing diagram showing when the pause interval is large according to an embodiment of the present invention;

[0023] Fig. 9 is a timing diagram showing that the pause interval is less than the warm-up time according to an embodiment of the present invention;

[0024] Fig.10 FIG. 4 is a flow chart of a memory control method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] Some embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementation methods of the present invention. More specifically, these embodiments are only examples of the systems and methods in the claims of the present invention.

[0026] The terms “first”, “second”, etc. used in this document do not particularly refer to the order or sequence, but are only used to distinguish components or operations described with the same technical terms.

[0027] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used together with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0028] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0029] Please refer to Figure 1 and Figure 2The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be coupled to a system bus 110.

[0030] In an exemplary embodiment, the host system 11 may be coupled to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be coupled to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0031] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless manner.

[0032] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be coupled to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0033] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 A memory storage device 30 and a host system 31.

[0034] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0035] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42 and a rewritable non-volatile memory module 43.

[0036] The connection interface unit 41 is used to couple to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, Parallel Advanced Technology Attachment (PATA) standard, Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Memory Stick (MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 41 may be packaged in one chip with the memory control circuit unit 42, or the connection interface unit 41 may be arranged outside a chip including the memory control circuit unit 42.

[0037] The memory control circuit unit 42 is coupled to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0038] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules, or other memory modules with the same characteristics.

[0039] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing the voltage (hereinafter also referred to as the critical voltage). Specifically, there is a charge capture layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge capture layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the critical voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the critical voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in this memory cell.

[0040] In an exemplary embodiment, the storage cells of the rewritable non-volatile memory module 43 may constitute a plurality of physical programming units, and these physical programming units may constitute a plurality of physical erasing units. Specifically, the storage cells on the same character line may constitute one or more physical programming units. If each storage cell can store more than 2 bits, the physical programming units on the same character line may be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LSB) of a storage cell belongs to the lower physical programming unit, and the most significant bit (MSB) of a storage cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the write speed of the lower physical programming unit is greater than the write speed of the upper physical programming unit, and / or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

[0041] In an exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit may be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include a data bit area and a redundancy bit area. The data bit area includes a plurality of physical sectors for storing user data, and the redundancy bit area is used to store system data (for example, management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of a physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit of erasure. That is, each physical erasure unit contains the minimum number of storage cells that are erased together. For example, the physical erasure unit is a physical block.

[0042] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0043] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control instructions, and when the memory storage device 10 is in operation, these control instructions are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to describing the operation of the memory control circuit unit 42 and the memory storage device 10.

[0044] In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in the form of firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are recorded in the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0045] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a specific area of ​​the rewritable non-volatile memory module 43 (for example, a system area in the memory module dedicated to storing system data) in the form of program code. In addition, the memory management circuit 51 has a microprocessor unit (not shown), a read-only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit will first execute the boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

[0046] In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a storage unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit and a data processing circuit. The storage unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are coupled to the microcontroller. The storage unit management circuit is used to manage the storage unit or storage unit group of the rewritable non-volatile memory module 43. The memory write circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit is used to issue an erase instruction sequence to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 43 and data to be read from the rewritable non-volatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may each include one or more program codes or scripts and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of command sequences to the rewritable non-volatile memory module 43 to instruct the execution of corresponding operations.

[0047] The host interface 52 is coupled to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data transmitted by the host system 11. For example, the instructions and data transmitted by the host system 11 can be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this, and the host interface 52 can also be compatible with the SATA standard, the PATA standard, the IEEE 1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

[0048] The memory interface 53 is coupled to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, the data to be written to the rewritable non-volatile memory module 43 will be converted into a format acceptable to the rewritable non-volatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations (for example, changing a read voltage level or performing a garbage collection (GC) operation, etc.). These instruction sequences are, for example, generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 through the memory interface 53. These instruction sequences may include one or more signals, or data on a bus. These signals or data may include scripts or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, etc. may be included.

[0049] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0050] The error checking and correction circuit 54 is coupled to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 obtains a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or an error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correcting code and / or error detecting code. For example, the ECC circuit 54 may use various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. to encode and decode data.

[0051] The buffer memory 55 is coupled to the memory management circuit 51 and used for temporarily storing data. The power management circuit 56 is coupled to the memory management circuit 51 and used for controlling the power of the memory storage device 10 .

[0052] In an exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In an exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In an exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0053] Figure 6 FIG. 1 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 6 The memory management circuit 51 may logically group the physical units 610 ( 0 ) to 610 (C) in the rewritable non-volatile memory module 43 into a storage area 601 , a spare area 602 , and a system area 603 .

[0054] In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of multiple continuous or discontinuous physical addresses. In an exemplary embodiment, a physical unit may also refer to a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an exemplary embodiment, a virtual block may include one or more physical erase units.

[0055] In an exemplary embodiment, the physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g., from Figure 1 The user data of the host system 11 of the storage area 601). For example, the physical units 610(0)~610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1)~610(B) in the idle area 602 do not store data (such as valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In an exemplary embodiment, the idle area 602 is also called a free pool.

[0056] In an exemplary embodiment, the memory management circuit 51 may configure the logical units 612(0)-612(D) to map the physical units 610(0)-610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In an exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple continuous or discontinuous logical addresses.

[0057] It should be noted that a logical unit can be mapped to one or more physical units. If a physical unit is currently mapped by a logical unit, it means that the data currently stored in the physical unit is valid data. On the contrary, if a physical unit is not currently mapped by any logical unit, it means that the data currently stored in the physical unit is invalid data.

[0058] In an exemplary embodiment, the memory management circuit 51 may record management data describing the mapping relationship between the logical unit and the physical unit (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table (L2Ptable). When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in the logical-to-physical mapping table.

[0059] In an exemplary embodiment, the memory management circuit 51 may store a specific type of data in the system area 603. For example, the physical units 610(B+1)-610(C) in the system area 603 may be dedicated to store data of higher importance and / or data that is not intended to be accessed or modified by the host system 11. For example, the data of higher importance and / or data that is not intended to be accessed or modified by the host system 11 may include a logical-to-physical mapping table, a bad block management table, a wear leveling management table, a valid data management table and / or other types of management data, and the present invention is not limited thereto. The logical-to-physical mapping table is used to record mapping information. This mapping information may reflect the mapping relationship between the logical unit and the physical unit. The bad block management table is used to record information related to at least one bad block in the rewritable non-volatile memory module 43. The wear leveling management table may be used to record information related to the wear status of at least one physical unit in the rewritable non-volatile memory module 43 (e.g., a read count, a write count and / or an erase count). The valid data management table may be used to record information related to the valid count of at least one physical unit in the rewritable non-volatile memory module 43 .

[0060] In an exemplary embodiment, the memory management circuit 51 may not map any logical unit to a physical unit in the system area 603. Thus, the data stored in the system area 603 may be prevented from being accessed or modified by the host system 11.

[0061] The memory management circuit 51 generates a command sequence for the rewritable non-volatile memory module 43, and these command sequences can control the rewritable non-volatile memory module 43 to perform operations such as reading, writing, and erasing. The memory management circuit 51 can also issue a pause command to the rewritable non-volatile memory module 43, so that the rewritable non-volatile memory module 43 pauses the currently executed operation and performs the read operation first.

[0062] Figure 7 FIG. 1 is a timing diagram showing the execution of a pause instruction according to an embodiment of the present invention. Figure 7Before time point T1, the rewritable non-volatile memory module 43 performs an operation 701, which can be a write operation or an erase operation. At time point T1, the memory management circuit 51 issues a suspend instruction to the rewritable non-volatile memory module 43, so that the rewritable non-volatile memory module 43 suspends the currently executed operation 701 to perform a read operation 702.

[0063] At time point T2, the read operation 702 ends, and the rewritable non-volatile memory module 43 must first go through a warm-up period 720 before returning to operation 703, wherein operation 703 is used to continue the work that has not been completed in operation 701. For example, if operation 701 is a write operation, not all data is written into the rewritable non-volatile memory module 43 when operation 701 is suspended, so the remaining data is continued to be written in operation 703. Alternatively, if operation 701 is an erase operation, operation 703 is used to complete the erase that has not been completed in operation 701.

[0064] At time point T3, the memory management circuit 51 again issues a pause command to the rewritable non-volatile memory module 43, so the rewritable non-volatile memory module 43 must pause operation 703 and prioritize the read operation 704. At time point T4, the read operation 704 ends, and after the warm-up time, the rewritable non-volatile memory module 43 continues the write operation or erase operation.

[0065] The memory management circuit 51 can set a pause interval 710 between two pause instructions. The time interval from when the rewritable non-volatile memory module 43 finishes the read operation 702 to when the next pause instruction is received must be greater than or equal to the pause interval 710. In other words, each time the memory management circuit 51 issues a pause instruction and the corresponding read operation is completed, the memory management circuit 51 must wait for the pause interval 710 before issuing the next pause instruction.

[0066] The pause interval 710 may correspond to a write operation or an erase operation. When the operation 701 is a write operation, the pause interval 710 is also called a write pause interval. When the operation 701 is an erase operation, the pause interval 710 is also called an erase pause interval. In some embodiments, the write pause interval and the erase pause interval are two values, respectively, and the memory management circuit 51 can adjust these two values ​​independently. Figure 7 The timing diagram is applicable to both the write operation and the erase operation, and thus is not shown repeatedly.

[0067] When the pause interval 710 is shorter, the rewritable non-volatile memory module 43 is more likely to be paused and the read operation is performed first, so the latency of the read command is shortened for the host system 11, but this will increase the time of the erase or write operation. On the contrary, when the pause interval 710 is longer, the rewritable non-volatile memory module 43 is less likely to be paused, so the erase or write operation will be completed faster, and the latency of the read command for the host system 11 will be greater. For example, Figure 8 is a timing diagram showing a large pause interval according to an embodiment of the present invention. Figure 8 , Figure 8 The pause interval 810 set in Figure 7 The pause interval 710 set in , the order of other operations does not change. Figure 8 In the embodiment, the time interval between the two read operations 702 and 704 is longer, and the delay of the read instruction for the host system 11 will increase.

[0068] Here, we use variables to discuss the time required for the read operation and the erase operation. Assuming that there is no pause instruction, the rewritable non-volatile memory module 43 needs a time length T to complete the erase operation E In this setting, if a read operation collides with an erase operation, it will take a waiting time of T E Add the time of direct memory access (DMA), that is, the delay of reading instructions will be greater than or equal to the time length T E On the other hand, it takes a time length T to perform the read operation 702 R , which includes the time to read data from the rewritable non-volatile memory module 43 plus the time for direct memory access. The length of the warm-up time 720 is T W , the length of the pause interval 710 is T S .exist Figure 7 In the embodiment of the present invention, the time required to complete the erase operation is increased to T E +2*T R +2*T W , the delay of reading the instruction becomes T S +T R , this value is less than T E The above time calculation for the erase operation can also be applied to the write operation, and will not be repeated here.

[0069] In the prior art, the pause interval 710 is a fixed value, but in this embodiment, the memory management circuit 51 can first determine the load level of the rewritable non-volatile memory module 43, and determine the pause interval 710 between multiple pause instructions according to the load level. After determining the pause interval, the memory management circuit 51 can sequentially issue multiple pause instructions to the rewritable non-volatile memory module 43 according to the pause interval. As described above, the size of the pause interval will affect the speed of completing the read operation, and will also affect the time required for the erase operation or the write operation. The memory management circuit 51 can dynamically determine the pause interval according to the current state of the system.

[0070] In some embodiments, the load level of the rewritable non-volatile memory module 43 can be divided into heavy load and light load. Generally speaking, since the time required for a read operation is usually shorter (and the read operation can be performed preferentially by a pause instruction), the time required for a write operation and an erase operation is usually longer. Therefore, when the load level of the rewritable non-volatile memory module 43 is heavy load, the accumulated unfinished operations are mostly write operations or erase operations. At this time, the memory management circuit 51 will increase the pause interval so that the write operation or erase operation will not be suspended. On the contrary, when the load level of the rewritable non-volatile memory module 43 is light load, even if the rewritable non-volatile memory module 43 is frequently paused, it is still capable of processing these write operations or erase operations. Therefore, the memory management circuit 51 will reduce the pause interval, thereby quickly completing the read operation. When the read operation is completed quickly, the delay of the read instruction for the host system 11 will be reduced, so the host system 11 can issue more instructions, which will increase the overall performance of the memory storage device 10. Several embodiments are given below to illustrate how to measure the load level.

[0071] When the host system 11 issues a write instruction to the memory management circuit 51, the memory management circuit 51 stores the write instruction (including the data to be written) in the buffer memory 55, and then reports to the host system 11 that the write instruction has been completed. Afterwards, the memory management circuit 51 issues a write instruction sequence to the rewritable non-volatile memory module 43 to write the data in the buffer memory 55 into the rewritable non-volatile memory module 43. Since the write operation may evoke an erase operation, if the erase operation is executed for too long, many write instructions will be temporarily stored in the buffer memory 55 and cannot be executed. Therefore, in some embodiments, the erase pause interval can be determined based on the free memory space in the buffer memory 55. Specifically, when the free memory space of the buffer memory 55 is greater than or equal to the first buffer threshold, it is determined that the load level is light load, so the memory management circuit 51 will reduce the erase pause interval. If the write instructions in the buffer memory 55 gradually increase, so that the free memory space of the buffer memory 55 is less than or equal to the second buffer threshold, the load level is determined to be heavy load, and the memory management circuit 51 will increase the erase pause interval to accelerate the execution of the erase operation. The second buffer threshold is less than the first buffer threshold, and the two buffer thresholds can be percentages of the memory space in the buffer memory 55. For example, the first buffer threshold can be 10%, and the second buffer threshold can be 2%, but the present invention is not limited thereto. In some embodiments, if the free memory space of the buffer memory 55 is less than the first buffer threshold and greater than the second buffer threshold, the memory management circuit 51 will maintain the pause interval unchanged.

[0072] The memory management circuit 51 manages a command queue. When the host system issues a command to the memory management circuit 51, the memory management circuit 51 adds the command to the command queue. The memory management circuit 51 can determine the load level and the write pause interval based on the occupancy rate of the command queue, where the occupancy rate refers to the percentage of space in the command queue that has been occupied by commands. Specifically, when the occupancy rate of the command queue is greater than the first queue threshold, the load level is judged to be heavy load, so the memory management circuit 51 increases the write pause interval. When the occupancy rate of the command queue is less than the second queue threshold, the load level is judged to be light load, so the memory management circuit 51 reduces the write pause interval. The above-mentioned first queue threshold may be greater than or equal to the second queue threshold.

[0073] In some embodiments, the load level can also be determined based on the write speed of the host system 11. When the rewritable non-volatile memory module 43 processes many write operations, the load is large. At this time, the write speed of the host system 11 is high, and the write pause interval should be increased so that the rewritable non-volatile memory module 43 can quickly perform write operations. Specifically, the memory management circuit 51 will first calculate the write speed of the host system 11. If this write speed is less than the first write threshold, the memory management circuit 51 determines that the load level is a light load, and thus the write pause interval will be reduced. If the write speed is greater than the second write threshold, the memory management circuit 51 determines that the load level is a heavy load, and thus the write pause interval will be increased. The above-mentioned first write threshold may be less than or equal to the second write threshold.

[0074] In some embodiments, the above-mentioned determination of the load level and the corresponding adjustment of the pause interval can be arbitrarily matched. For example, in one embodiment, the write pause interval can be determined according to the free memory space in the buffer memory 55, the erase pause interval can be determined according to the occupancy rate of the instruction queue, and the erase pause interval can be determined according to the write speed of the host system 11. Alternatively, the pause interval can be increased based on one load level, and the pause interval can be reduced based on another load level.

[0075] The host system 11 also manages a command queue, and the read commands, write commands, etc. generated by the host system 11 are added to this command queue. The queue depth (queue depth, QD) of this command queue will affect the load level of the rewritable non-volatile memory module 43. When the queue depth is large, the load of the rewritable non-volatile memory module 43 is higher, and vice versa, when the queue depth is small, the load of the rewritable non-volatile memory module 43 is lower. In this embodiment, the pause interval is dynamically adjusted, so it can be applicable to host systems 11 with different queue depths.

[0076] In some embodiments, the pause interval (which may be a write pause interval or an erase pause interval) has an upper limit and a lower limit, and the memory management circuit 51 adjusts the pause interval within this numerical range. In some embodiments, the lower limit of the pause interval may be lower than Figure 7 and Figure 8 The warm-up time 720 is shown. For example, Fig. 9 is a timing diagram showing that the pause interval is less than the warm-up time according to an embodiment of the present invention. Fig. 9, the pause interval 910 set here is less than the original warm-up time, so at time point T3 the memory management circuit 51 can issue another pause instruction. At this time, the warm-up procedure has not yet ended, and the rewritable non-volatile memory module 43 needs to be paused again to perform the read operation 704. This setting does not allow time to perform erase or write operations between the two read operations 702 and 704, but it is reasonable in some situations. For example, when the number of read instructions issued by the host system 11 is greater than the number of write instructions, it becomes more important to complete the read instructions first. Setting the pause interval 910 to be less than the warm-up time 720 can quickly complete the read instructions, reduce the delay of the read instructions, and improve the overall performance.

[0077] Fig.10 is a flow chart of a memory control method according to an embodiment of the present invention. Fig.10 In step 1001, the load level of the rewritable non-volatile memory module is determined. In step 1002, the pause interval between multiple pause instructions is determined according to the load level. In step 1003, the pause instructions are sequentially issued to the rewritable non-volatile memory module according to the pause interval. Fig.10 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig.10 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig.10 The method can be used in conjunction with the above embodiment or can be used alone. In other words, Fig.10 Other steps may also be added between the steps.

[0078] In the above disclosed technical means, the pause interval is dynamically determined according to the load level of the rewritable non-volatile memory module, thereby reducing the delay of the read instruction when the load is light, which can improve the overall performance of the system.

[0079] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control method, characterized in that: For a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the memory control method includes: Determining the load level of the rewritable non-volatile memory module; Determining a pause interval between a plurality of pause instructions according to the load level; and The plurality of suspend instructions are sequentially issued to the rewritable non-volatile memory module according to the suspend interval, the plurality of suspend instructions are used to cause the rewritable non-volatile memory module to suspend a currently executed operation to execute a read operation, wherein a time interval from the end of the read operation to the receipt of a next one of the plurality of suspend instructions is greater than or equal to the suspend interval.

2. The memory control method according to claim 1, characterized in that: Also includes: determining whether the load level of the rewritable non-volatile memory module is a light load or a heavy load, The step of determining the pause interval between the plurality of pause instructions according to the load level comprises: If the load level is the light load, reducing the pause interval; as well as If the load level is the heavy load, the pause interval is increased.

3. The memory control method according to claim 2, characterized in that: The operation is an erase operation, the pause interval is an erase pause interval, and the step of determining whether the load level of the rewritable non-volatile memory module is the light load or the heavy load includes: receiving a write instruction from a host system and storing the write instruction in a buffer memory; When the free memory space of the buffer memory is greater than or equal to a first buffer threshold, determining that the load level is the light load; and When the free memory space of the buffer memory is less than or equal to a second buffer threshold, the load level is determined to be the heavy load, wherein the second buffer threshold is less than the first buffer threshold.

4. The memory control method according to claim 3, characterized in that: Also includes: When the free memory space of the buffer memory is less than the first buffer threshold and greater than the second buffer threshold, the pause interval is maintained unchanged.

5. The memory control method according to claim 2, characterized in that: Wherein the operation is a write operation, the pause interval is a write pause interval, and the step of determining whether the load level of the rewritable non-volatile memory module is the light load or the heavy load comprises: Receive instructions from the host system and add the instructions to the instruction queue; If the occupancy rate of the instruction queue is greater than the first queue threshold, determining that the load level is the heavy load; and If the occupancy rate of the instruction queue is less than a second queue threshold, the load level is determined to be the light load.

6. The memory control method according to claim 2, characterized in that: Wherein the operation is a write operation, the pause interval is a write pause interval, and the step of determining whether the load level of the rewritable non-volatile memory module is the light load or the heavy load comprises: Calculate the host system's write speed; If the writing speed is less than a first writing threshold, determining that the load level is the light load; and If the writing speed is greater than a second writing threshold, the load level is determined to be the heavy load.

7. The memory control method according to claim 1, characterized in that: When the rewritable non-volatile memory module returns to the operation from one of the plurality of suspend instructions, the rewritable non-volatile memory module first undergoes a warm-up period before executing the operation. The memory control method further includes: In response to the number of the plurality of read instructions issued by the host system being greater than the number of the plurality of write instructions, the pause interval is set to be less than the warm-up time.

8. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units; as well as A memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to perform multiple steps: Determining the load level of the rewritable non-volatile memory module; Determining a pause interval between a plurality of pause instructions according to the load level; and The plurality of suspend instructions are sequentially issued to the rewritable non-volatile memory module according to the suspend interval, the plurality of suspend instructions are used to cause the rewritable non-volatile memory module to suspend a currently executed operation to execute a read operation, wherein a time interval from the end of the read operation to the receipt of a next one of the plurality of suspend instructions is greater than or equal to the suspend interval.

9. The memory storage device according to claim 8, characterized in that: The multiple steps also include: determining whether the load level of the rewritable non-volatile memory module is a light load or a heavy load, The step of determining the pause interval between the plurality of pause instructions according to the load level comprises: If the load level is the light load, reducing the pause interval; and If the load level is the heavy load, the pause interval is increased.

10. The memory storage device according to claim 9, characterized in that: The operation is an erase operation, the pause interval is an erase pause interval, and the step of determining whether the load level of the rewritable non-volatile memory module is the light load or the heavy load includes: receiving a write instruction from the host system and storing the write instruction in a buffer memory; When the free memory space of the buffer memory is greater than or equal to a first buffer threshold, determining that the load level is the light load; and When the free memory space of the buffer memory is less than or equal to a second buffer threshold, the load level is determined to be the heavy load, wherein the second buffer threshold is less than the first buffer threshold.

11. The memory storage device according to claim 10, characterized in that: The multiple steps also include: When the free memory space of the buffer memory is less than the first buffer threshold and greater than the second buffer threshold, the pause interval is maintained unchanged.

12. The memory storage device according to claim 9, characterized in that Wherein the operation is a write operation, the pause interval is a write pause interval, and the step of determining whether the load level of the rewritable non-volatile memory module is the light load or the heavy load comprises: Receiving instructions from the host system and adding the instructions to an instruction queue; If the occupancy rate of the instruction queue is greater than the first queue threshold, determining that the load level is the heavy load; and If the occupancy rate of the instruction queue is less than a second queue threshold, the load level is determined to be the light load.

13. The memory storage device according to claim 9, characterized in that Wherein the operation is a write operation, the pause interval is a write pause interval, and the step of determining whether the load level of the rewritable non-volatile memory module is the light load or the heavy load comprises: Calculating a write speed of the host system; If the writing speed is less than a first writing threshold, determining that the load level is the light load; and If the writing speed is greater than a second writing threshold, the load level is determined to be the heavy load.

14. The memory storage device according to claim 8, characterized in that When the rewritable non-volatile memory module returns to the operation from one of the plurality of suspend instructions, the rewritable non-volatile memory module first undergoes a warm-up period before executing the operation, and the plurality of steps further include: In response to the number of the plurality of read instructions issued by the host system being greater than the number of the plurality of write instructions, the pause interval is set to be less than the warm-up time.

15. A memory control circuit unit, characterized in that: Used to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the memory control circuit unit includes: A host interface for coupling to a host system; A memory interface, for coupling to the rewritable non-volatile memory module; A memory management circuit is coupled to the host interface and the memory interface, The memory management circuit is used to perform multiple steps: Determining the load level of the rewritable non-volatile memory module; Determining a pause interval between a plurality of pause instructions according to the load level; and The plurality of suspend instructions are sequentially issued to the rewritable non-volatile memory module according to the suspend interval, the plurality of suspend instructions are used to cause the rewritable non-volatile memory module to suspend a currently executed operation to execute a read operation, wherein a time interval from the end of the read operation to the receipt of a next one of the plurality of suspend instructions is greater than or equal to the suspend interval.

16. The memory control circuit unit according to claim 15, characterized in that: The multiple steps also include: determining whether the load level of the rewritable non-volatile memory module is a light load or a heavy load, The step of determining the pause interval between the plurality of pause instructions according to the load level comprises: If the load level is the light load, reducing the pause interval; and If the load level is the heavy load, the pause interval is increased.

17. The memory control circuit unit according to claim 16, characterized in that: The operation is an erase operation, the pause interval is an erase pause interval, and the step of determining whether the load level of the rewritable non-volatile memory module is the light load or the heavy load includes: receiving a write instruction from the host system and storing the write instruction in a buffer memory; When the free memory space of the buffer memory is greater than or equal to a first buffer threshold, determining that the load level is the light load; and When the free memory space of the buffer memory is less than or equal to a second buffer threshold, the load level is determined to be the heavy load, wherein the second buffer threshold is less than the first buffer threshold.

18. The memory control circuit unit according to claim 17, characterized in that: The multiple steps also include: When the free memory space of the buffer memory is less than the first buffer threshold and greater than the second buffer threshold, the pause interval is maintained unchanged.

19. The memory control circuit unit according to claim 16, wherein: Wherein the operation is a write operation, the pause interval is a write pause interval, and the step of determining whether the load level of the rewritable non-volatile memory module is the light load or the heavy load comprises: Receiving instructions from the host system and adding the instruction sequence to an instruction queue; If the occupancy rate of the instruction queue is greater than the first queue threshold, determining that the load level is the heavy load; and If the occupancy rate of the instruction queue is less than a second queue threshold, the load level is determined to be the light load.

20. The memory control circuit unit according to claim 16, wherein: Wherein the operation is a write operation, the pause interval is a write pause interval, and the step of determining whether the load level of the rewritable non-volatile memory module is the light load or the heavy load comprises: Calculating a write speed of the host system; If the writing speed is less than a first writing threshold, determining that the load level is the light load; and If the writing speed is greater than a second writing threshold, the load level is determined to be the heavy load.

21. The memory control circuit unit according to claim 15, characterized in that: When the rewritable non-volatile memory module returns to the operation from one of the plurality of suspend instructions, the rewritable non-volatile memory module first undergoes a warm-up period before executing the operation, and the plurality of steps further include: In response to the number of the plurality of read instructions issued by the host system being greater than the number of the plurality of write instructions, the pause interval is set to be less than the warm-up time.

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