Code analysis method, electronic equipment and computer readable medium

Abstract

The invention provides a code analysis method which comprises the steps that according to an assembly instruction in assembly codes, an abstract instruction is generated, and the abstract instruction is used for converting abstract attributes of a register; determining an abstract attribute of at least one target register corresponding to the assembly instruction according to the abstract instruction; and determining whether the assembly code has an error or not according to the abstract attribute of the target register. The invention further provides electronic equipment and a computer readable medium.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a code analysis method, an electronic device, and a computer-readable medium. Background Art

[0002] The adaptation of different central processing units (CPUs) and other hardware (mainly CPUs) is usually completed by embedded operating system developers. For example, developers need to manually write assembly code according to the CPU architecture to use CPU capabilities such as interrupts, exceptions, system calls, and memory management. The amount of assembly code is generally not very large, but when a software failure occurs in the operating system, it is difficult to trace back to the assembly code from the failure site. Therefore, it is crucial to ensure the accuracy of the assembly code during the development review stage.

[0003] Most of the industry's source code-level static analysis tools are for high-level programming languages, and assembly code mainly relies on manual review. However, assembly code is less readable than high-level programming languages, and it is difficult to clearly correspond the specific business logic with the semantics of the assembly code itself during the manual review process, resulting in low efficiency and high error-proneness of manual review, and the accuracy of the assembly code cannot be ensured. Summary of the invention

[0004] The embodiments of the present disclosure provide a code analysis method, an electronic device, and a computer-readable medium.

[0005] In a first aspect, an embodiment of the present disclosure provides a code analysis method, comprising: generating an abstract instruction based on assembly instructions in an assembly code, wherein the abstract instruction is used to convert abstract properties of a register; determining, based on the abstract instruction, an abstract property of at least one target register corresponding to the assembly instruction; and determining whether there is an error in the assembly code based on the abstract property of the target register.

[0006] In a second aspect, an embodiment of the present disclosure provides an electronic device, comprising: one or more processors; a memory on which one or more programs are stored, and when the one or more programs are executed by the one or more processors, the one or more processors implement the code analysis method described in the first aspect of the embodiment of the present disclosure.

[0007] In a third aspect, an embodiment of the present disclosure provides a computer-readable medium having a computer program stored thereon, and when the program is executed by a processor, the code analysis method described in the first aspect of the embodiment of the present disclosure is implemented.

[0008] In the code analysis method provided by the embodiment of the present disclosure, abstract attributes of registers and abstract instructions for converting the abstract attributes of registers are defined; abstract instructions are generated according to assembly instructions, and the abstract attributes of target registers corresponding to the assembly instructions are determined according to the abstract instructions, so that the abstract attributes of the target registers are converted as the assembly instructions in the assembly code perform read / write operations on the target registers, so that it is possible to determine whether the assembly instructions in the assembly code use the target registers correctly according to the abstract attributes of the target registers, and then determine whether there are errors in the assembly code, thereby realizing automatic checking of the assembly code, improving the efficiency of assembly code review, and ensuring the accuracy of the assembly code. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a flow chart of a code analysis method in an embodiment of the present disclosure;

[0010] Figure 2 is a schematic diagram of the composition of an electronic device in an embodiment of the present disclosure;

[0011] Figure 3 is a schematic diagram of the composition of a computer-readable medium in an embodiment of the present disclosure;

[0012] Figure 4 is a schematic diagram of an abstract instruction stream initial state in an embodiment of the present disclosure;

[0013] Figure 5 is a schematic diagram of an abstract instruction stream end state in an embodiment of the present disclosure;

[0014] Figure 6 is a schematic diagram of another abstract instruction stream initial state in an embodiment of the present disclosure;

[0015] Figure 7 It is a schematic diagram of another abstract instruction stream end state in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the code analysis method, electronic device, and computer-readable medium provided by the present disclosure are described in detail below in conjunction with the accompanying drawings.

[0017] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0018] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0019] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0020] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0022] First, refer to Figure 1 , the present disclosure provides a code analysis method, including:

[0023] S1. Generate an abstract instruction according to the assembly instruction in the assembly code, wherein the abstract instruction is used to convert the abstract attribute of the register;

[0024] S2. Determine, according to the abstract instruction, an abstract attribute of at least one target register corresponding to the assembly instruction;

[0025] S3. Determine whether there is an error in the assembly code according to the abstract attribute of the target register.

[0026] In the embodiment of the present disclosure, abstract attributes of registers and abstract instructions for converting the abstract attributes of registers are defined.

[0027] The embodiments of the present disclosure do not specifically limit the abstract attributes of the defined registers. In some embodiments, the abstract attributes of the registers include at least one of readable (R), writable (W), read-write (RW), unknown (T), and error (E).

[0028] When an assembly instruction is executed, it will perform a read / write operation on at least one target register, generate an abstract instruction based on the assembly instruction, and determine the abstract attribute of the target register corresponding to the assembly instruction based on the abstract instruction, that is, as the assembly instruction in the assembly code performs a read / write operation on the target register, the abstract attribute of the target register is converted.

[0029] In the disclosed embodiment, according to the abstract attribute of the target register, it is possible to determine whether the assembly instruction in the assembly code uses the target register correctly. For example, if the abstract attribute of at least one target register is wrong, it means that the assembly instruction uses the target register incorrectly; if the abstract attributes of each target register corresponding to the assembly code are all correct, it means that the assembly instruction uses the target register correctly.

[0030] In the disclosed embodiment, based on determining whether the assembly instructions in the assembly code use the target register correctly through the abstract attributes of the target register, it is possible to further determine whether there are errors in the assembly code, thereby achieving automated checking of the assembly code.

[0031] The embodiments of the present disclosure do not specifically limit how to generate abstract instructions based on assembly instructions in assembly code.

[0032] When the assembly instruction is executed, it will perform a read / write operation on at least one target register. Each read or write operation performed by the assembly instruction on the target register will cause a change in the state of the target register. In some embodiments, corresponding to a read or write operation of the assembly instruction on the target register, an abstract instruction is generated to convert the abstract attribute of the target register corresponding to the change in the state of the target register.

[0033] Accordingly, in some embodiments, generating an abstract instruction according to the assembly instruction in the assembly code includes:

[0034] According to the operation of the assembly instruction on the target register, an abstract instruction corresponding to the assembly instruction is determined, wherein one operation of the assembly instruction on the target register corresponds to one abstract instruction.

[0035] In the disclosed embodiment, for the operation of reading or writing the target register by the assembly instruction, the corresponding abstract instruction is defined, and the conversion of the abstract attribute of the target register by the abstract instruction can reflect the change of the state of the target register caused by the corresponding operation. For example, corresponding to the operation of reading the target register by the assembly instruction, the read instruction (read) and the status instruction (status) are defined; corresponding to the operation of writing the target register by the assembly instruction, the write instruction (write) and the control instruction (control) are defined.

[0036] In some embodiments, when assembly instructions perform read / write operations on different types of registers, the state changes of different types of registers may be different. Corresponding abstract instructions are defined for assembly instructions performing read or write operations on different types of registers.

[0037] Accordingly, in some embodiments, determining the abstract instruction corresponding to the assembly instruction according to the operation of the assembly instruction on the target register includes:

[0038] The abstract instruction is determined according to the type of the target register and the operation of the assembly instruction on the target register, wherein the type of the target register includes a general register and / or a special register.

[0039] For example, a read instruction (read) is defined corresponding to the operation of an assembly instruction to read a general register; a write instruction (write) is defined corresponding to the operation of an assembly instruction to write a general register; a status instruction (status) is defined corresponding to the operation of an assembly instruction to read a special register; and a control instruction (control) is defined corresponding to the operation of an assembly instruction to write a special register.

[0040] Accordingly, in some embodiments, determining the abstract instruction according to the type of the target register and the operation of the assembly instruction on the target register includes:

[0041] Generate a read instruction corresponding to the read operation of the assembly instruction on the general register; and / or

[0042] Generate a write instruction corresponding to the write operation of the assembly instruction on the general register; and / or

[0043] Generate a status instruction corresponding to the read operation of the assembly instruction on the special register; and / or

[0044] Corresponding to the write operation of the assembly instruction to the special register, a control instruction is generated.

[0045] In some embodiments, the abstract attribute of the register includes at least one of readable (R), writable (W), read-write (RW), unknown (T), and error (E).

[0046] In the embodiments of the present disclosure, the abstract attribute of the register is readable, indicating that the value in the register is valid and should at least be read in sequence; the abstract attribute of the register is writable, indicating that the value in the register is unreliable and should be written before use; the abstract attribute of the register is read-write, indicating that the value in the register is valid and can be read and a new value can be written; the abstract attribute of the register is unknown, indicating that the state of the register is unknown; the abstract attribute of the register is error, indicating that the register is error and cannot be read or written.

[0047] In the disclosed embodiment, based on the abstract attributes of the above-defined registers, calculation rules for the abstract attributes of corresponding conversion registers are defined for different abstract instructions, so that the conversion of the abstract attributes of the target register by the abstract instruction can reflect the change in the state of the target register caused by the operation corresponding to the assembly instruction.

[0048] In some embodiments, a calculation rule for an abstract attribute of a read instruction conversion register is defined.

[0049] Accordingly, in some embodiments, the abstract instruction includes a read instruction; determining the abstract attribute of the target register according to the abstract instruction includes:

[0050] According to the read instruction, determining the abstract attribute of the target register whose initial attribute is readable as read-write; and / or

[0051] According to the read instruction, determining the abstract attribute of the target register whose initial attribute is writable as an error; and / or

[0052] According to the read instruction, the abstract attribute of the target register whose initial attribute is read-write is determined as read-write; and / or

[0053] According to the read instruction, the abstract attribute of the target register whose initial attribute is error is determined to be error.

[0054] In some embodiments, calculation rules for abstract attributes of a write instruction (write) conversion register are defined.

[0055] Accordingly, in some embodiments, the abstract instruction includes a write instruction; determining the abstract attribute of the target register according to the abstract instruction includes:

[0056] According to the write instruction, determining the abstract attribute of the target register whose initial attribute is readable as an error; and / or

[0057] According to the write instruction, determining the abstract attribute of the target register whose initial attribute is writable to be readable; and / or

[0058] According to the write instruction, determining the abstract attribute of the target register whose initial attribute is read-write as readable; and / or

[0059] According to the write instruction, the abstract attribute of the target register whose initial attribute is error is determined to be error.

[0060] In some embodiments, calculation rules for abstract attributes of a status conversion register are defined.

[0061] Accordingly, in some embodiments, the abstract instruction includes a status instruction; determining the abstract attribute of the target register according to the abstract instruction includes:

[0062] According to the status instruction, determining the abstract attribute of the target register whose initial attribute is readable as readable; and / or

[0063] According to the status instruction, determining the abstract attribute of the target register whose initial attribute is writable as an error; and / or

[0064] According to the state instruction, the abstract attribute of the target register whose initial attribute is read-write is determined as read-write; and / or

[0065] According to the status instruction, the abstract attribute of the target register whose initial attribute is error is determined to be error.

[0066] In some embodiments, calculation rules for abstract attributes of a control instruction conversion register are defined.

[0067] Accordingly, in some embodiments, the abstract instruction includes a control instruction; determining the abstract attribute of the target register according to the abstract instruction includes:

[0068] According to the control instruction, determining the abstract attribute of the target register whose initial attribute is readable as an error; and / or

[0069] According to the control instruction, determining the abstract attribute of the target register whose initial attribute is writable as writable; and / or

[0070] According to the control instruction, the abstract attribute of the target register whose initial attribute is read-write is determined as read-write; and / or

[0071] According to the control instruction, the abstract attribute of the target register whose initial attribute is error is determined to be error.

[0072] It should be noted that, in the embodiment of the present disclosure, the initial attribute of the target register refers to the abstract attribute of the target register before the current abstract instruction is executed; it also refers to the abstract attribute of the target register before the assembly instruction corresponding to the current abstract instruction operates on the target register.

[0073] In some embodiments, based on the definition of abstract attributes of registers such as readable (R), writable (W), read-write (RW), unknown (T), and error (E), determining whether the assembly code has an error according to the abstract attributes of the target register includes:

[0074] When the abstract attribute of at least one of the target registers is wrong, it is determined that an error exists in the assembly code.

[0075] In the disclosed embodiment, if the abstract attribute of any target register is an error, it means that there is an error in the use of the target register by the assembly instructions in the assembly code, thereby determining that there is an error in the assembly code; only when the abstract attributes of each target register corresponding to the assembly instructions in the assembly code are not errors, that is, when the assembly instructions in the assembly code use each target register correctly, can it be determined that there is no error in the assembly code.

[0076] Based on the abstract attributes of registers, abstract instructions, and calculation rules of abstract instructions defined in the embodiments of the present disclosure, it is possible to implement overall semantic analysis of assembly code.

[0077] In some embodiments, the assembly code is abstracted into a computation graph, each abstract instruction corresponds to a computation node on the computation graph, and the abstract attributes of each target register corresponding to the assembly code are used as the attributes of the computation node. Starting from the initial computation node of the computation graph, the attributes of each computation node in the computation graph are analyzed according to an abstract instruction stream composed of multiple abstract instructions to obtain the attributes of the end computation node of the computation graph, that is, the abstract attributes of each target register corresponding to the assembly code, and then it is determined whether there is an error in the assembly code based on the abstract attributes of each target register.

[0078] In some embodiments, before determining the abstract attribute of at least one target register corresponding to the assembly instruction according to the abstract instruction, the code analysis method further includes:

[0079] Generate a computation graph according to the assembly code, wherein the computation graph includes a plurality of computation nodes executed sequentially, one computation node corresponds to one abstract instruction, and one operation of the assembly instruction on the target register corresponds to one abstract instruction;

[0080] Determine the abstract attribute of each of the target registers corresponding to the initial computing node in the computing graph;

[0081] The abstract attribute of each of the target registers corresponding to the computing nodes other than the initial computing node in the computing graph is set to unknown.

[0082] In some embodiments, determining, according to the abstract instruction, an abstract attribute of at least one target register corresponding to the assembly instruction includes:

[0083] Determine a set of computing nodes to be analyzed, wherein the set of computing nodes to be analyzed is composed of computing nodes to be analyzed in the computing graph;

[0084] When the set of computing nodes to be analyzed is not empty, according to the execution order of multiple computing nodes in the computation graph, the computing nodes to be analyzed in the set of computing nodes to be analyzed are selected in turn as current computing nodes, and the following steps are performed:

[0085] Determining, according to the abstract instruction corresponding to the current computing node, the abstract attribute of each of the target registers corresponding to the current computing node;

[0086] The computing node to be analyzed that is the current computing node is removed from the computing nodes to be analyzed.

[0087] The disclosed embodiment also defines the intersection operation and calculation rules of the abstract instructions that intersect the same target register.

[0088] In some embodiments, determining the abstract attribute of the target register according to the abstract instruction includes:

[0089] In the case where a plurality of the abstract instructions converge on the same target register, determining the intermediate abstract attribute of the target register corresponding to each of the abstract instructions according to each of the abstract instructions;

[0090] Intersection operations are performed on the intermediate abstract attributes of the target register corresponding to each of the abstract instructions to determine the abstract attribute of the target register.

[0091] In the embodiment of the present disclosure, multiple abstract instructions converge on the same target register, which means that multiple abstract instructions act on the target register at the same time, and the abstract attribute of the target register is jointly determined by the conversion operations of the multiple abstract instructions on the abstract attribute of the target register.

[0092] When the abstract attribute of the target register is jointly determined according to the conversion operations of the abstract attributes of the target register by the multiple abstract instructions, the calculation rules of the intersection operation defined in the embodiment of the present disclosure are followed.

[0093] Accordingly, in some embodiments, performing an intersection operation on the intermediate abstract attributes of the target register corresponding to each of the abstract instructions to determine the abstract attribute of the target register includes:

[0094] Performing an intersection operation on the non-empty attribute and the unknown, obtaining the abstract attribute of the target register as the non-empty attribute, wherein the non-empty attribute is any one of readable, writable, read-write, unknown, and error;

[0095] Performing an intersection operation on readable and read-write, obtaining the abstract attribute of the target register as read-write;

[0096] Performing an intersection operation on writable and read-write, obtaining the abstract attribute of the target register as read-write;

[0097] Performing an intersection operation on readable and writable, the abstract attribute of the target register is obtained to be an error;

[0098] The empty attribute and the error are intersected to obtain the abstract attribute of the target register as error.

[0099] Second, refer to Figure 2 , an embodiment of the present disclosure provides an electronic device, comprising:

[0100] One or more processors 101;

[0101] A memory 102, on which one or more programs are stored. When the one or more programs are executed by one or more processors, the one or more processors implement the code analysis method described in the first aspect of the embodiment of the present disclosure;

[0102] One or more I / O interfaces 103 are connected between the processor and the memory and are configured to implement information exchange between the processor and the memory.

[0103] Among them, the processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU) and the like; the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 103 is connected between the processor 101 and the memory 102, and can realize information interaction between the processor 101 and the memory 102, including but not limited to a data bus (Bus) and the like.

[0104] In some embodiments, the processor 101 , the memory 102 , and the I / O interface 103 are connected to each other via a bus 104 , and further connected to other components of the computing device.

[0105] Thirdly, refer to Figure 3 The embodiment of the present disclosure provides a computer-readable medium on which a computer program is stored. When the program is executed by a processor, the code analysis method described in the first aspect of the embodiment of the present disclosure is implemented.

[0106] In order to enable those skilled in the art to more clearly understand the technical solutions provided by the embodiments of the present disclosure, the technical solutions provided by the embodiments of the present disclosure are described in detail below through specific embodiments:

[0107] Embodiment 1

[0108] (1) This embodiment defines the abstract domain of register attributes operated by assembly instructions, that is, the abstract attributes of registers:

[0109] The abstract domain is defined as the set S = {R, W, RW, E, T}, where R indicates that the value in the register is valid and should be read at least once, W indicates that the value in the register is unreliable and should be written before use, RW indicates that the value in the register is valid and can be read and replaced with a new value, E indicates that the register is wrong and cannot be read or written, and T indicates that the status is unknown.

[0110] (2) This embodiment defines four abstract instructions: read, write, status, and control, and defines the calculation rules for the abstract attributes of each abstract instruction conversion register:

[0111] read(r:R)={r←RW}

[0112] read(r:W)={r←E}

[0113] read(r:RW)={r←RW}

[0114] read(r:E)={r←E}

[0115] write(r:R,v)={r←E}

[0116] write(r:W,v)={r←R}

[0117] write(r:RW,v)={r←R}

[0118] write(r:E,v)={r←E}

[0119] status(r:R)={r←R}

[0120] status(r:W)={r←E}

[0121] status(r:RW)={r←RW}

[0122] status(r:E)={r←E}

[0123] control(r:R)={r←E}

[0124] control(r:W)={r←W}

[0125] control(r:RW)={r←RW}

[0126] control(r:E)={r←E}

[0127] Among them, : represents the abstract value of the current register, and ← represents the update of the abstract value.

[0128] (3) This embodiment defines an abstract attribute conversion function:

[0129] f end =id;

[0130] f v =Abstract instruction operation result.

[0131] (4) This embodiment defines the intersection operation join:

[0132]

[0133] in, Represents an intersection operation.

[0134] The calculation rules for intersection operations are defined:

[0135]

[0136]

[0137]

[0138]

[0139]

[0140] Among them, x represents a non-empty attribute, and _ represents an empty attribute.

[0141] (5) This embodiment defines an intersection function:

[0142] meet(v)=join(w),w∈pred(v)

[0143] Among them, pred(v) represents all the predecessor nodes of v.

[0144] (6) This embodiment defines the initial attributes of each computing node in the computing graph, where the initial attribute of the initial computing node is I, and the initial attributes of other computing nodes are defined as {T, T, T...}.

[0145] (7) The code analysis algorithm is defined and expressed in the following pseudocode form:

[0146]

[0147]

[0148] Embodiment 2

[0149] This embodiment is based on the first embodiment, taking the powerpc e500v2 ISA as an example, and analyzes the following assembly code fragment:

[0150]

[0151] (1) This embodiment converts the e500v2 assembly instructions into abstract instructions of the abstract domain. The conversion rule definition is as follows:

[0152]

[0153] The correspondence between the converted assembly instructions and abstract instructions is as follows:

[0154]

[0155] (2) Figure 4 As shown in the figure, two computing nodes entry and exit are defined to indicate the start and end of the abstract instruction stream, and the initial state of the abstract instruction stream is set. Among them, the initial attributes of the computing node entry are: the abstract attribute of register r0 is W, the abstract attribute of register sp is R, the abstract attribute of register r22 is W, and the abstract attribute of register r31 is W; the abstract states of the registers corresponding to the computing nodes other than the computing node entry are all set to T.

[0156] (3) Set the abstract state predicate to Value(r)≠E, that is, there is no register in the result whose state is E.

[0157] (4) After running the abstract instructions one by one according to the analysis algorithm, the results are as follows Figure 5 As shown in the result, the abstract attribute of register r0 is E, which does not meet the condition of the abstract state predicate. Therefore, it is determined that there is a problem with the use of register r0 in this assembly code, that is, there is an error in this assembly code.

[0158] Embodiment 3

[0159] This embodiment is based on the first embodiment, takes the powerpc e500v2 ISA as the operation object, and analyzes the following assembly code fragment:

[0160]

[0161] (1) This embodiment converts the e500v2 assembly instructions into abstract instructions of the abstract domain. A new conversion rule is added on the basis of the second embodiment, as shown below:

[0162]

[0163] The correspondence between the converted assembly instructions and abstract instructions is as follows:

[0164]

[0165] (2) Figure 6 As shown in the figure, two computing nodes entry and exit are defined to indicate the start and end of the abstract instruction stream, and the initial state of the abstract instruction stream is set. Among them, the initial attributes of the computing node entry are: the abstract attribute of register r0 is W, the abstract attribute of register sp is R, the abstract attribute of register msr is RW, and the abstract attribute of register r31 is W; the abstract states of the registers corresponding to the computing nodes other than the computing node entry are all set to T.

[0166] (3) Set the abstract state predicate to Value(r)≠E, that is, there is no register in the result whose state is E.

[0167] (4) After running the abstract instructions one by one according to the analysis algorithm, we get the following Figure 7 As shown in the result, the abstract attribute of register r31 is E, which does not meet the condition of the abstract state predicate. Therefore, it is determined that there is a problem with the use of register r31 in this assembly code, that is, there is an error in this assembly code.

[0168] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0169] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A code analysis method, comprising: Generate an abstract instruction according to the assembly instruction in the assembly code, wherein the abstract instruction is used to convert the abstract attribute of the register; Determining, according to the abstract instruction, an abstract attribute of at least one target register corresponding to the assembly instruction; It is determined whether the assembly code has an error according to the abstract attribute of the target register.

2. The code analysis method according to claim 1, wherein: The abstract attributes of the register include at least one of readable, writable, read-write, unknown, and error.

3. The code analysis method according to claim 2, wherein: The abstract instruction includes a read instruction; determining the abstract attribute of the target register according to the abstract instruction includes: According to the read instruction, determining the abstract attribute of the target register whose initial attribute is readable as read-write; and / or According to the read instruction, determining the abstract attribute of the target register whose initial attribute is writable as an error; and / or According to the read instruction, the abstract attribute of the target register whose initial attribute is read-write is determined as read-write; and / or According to the read instruction, the abstract attribute of the target register whose initial attribute is error is determined to be error.

4. The code analysis method according to claim 2, wherein: The abstract instruction includes a write instruction; determining the abstract attribute of the target register according to the abstract instruction includes: According to the write instruction, determining the abstract attribute of the target register whose initial attribute is readable as an error; and / or According to the write instruction, determining the abstract attribute of the target register whose initial attribute is writable to be readable; and / or According to the write instruction, determining the abstract attribute of the target register whose initial attribute is read-write as readable; and / or According to the write instruction, the abstract attribute of the target register whose initial attribute is error is determined to be error.

5. The code analysis method according to claim 2, wherein: The abstract instruction includes a status instruction; determining the abstract attribute of the target register according to the abstract instruction includes: According to the status instruction, determining the abstract attribute of the target register whose initial attribute is readable as readable; and / or According to the status instruction, determining the abstract attribute of the target register whose initial attribute is writable as an error; and / or According to the state instruction, the abstract attribute of the target register whose initial attribute is read-write is determined as read-write; and / or According to the status instruction, the abstract attribute of the target register whose initial attribute is error is determined to be error.

6. The code analysis method according to claim 2, wherein: The abstract instruction includes a control instruction; determining the abstract attribute of the target register according to the abstract instruction includes: According to the control instruction, determining the abstract attribute of the target register whose initial attribute is readable as an error; and / or According to the control instruction, determining the abstract attribute of the target register whose initial attribute is writable as writable; and / or According to the control instruction, the abstract attribute of the target register whose initial attribute is read-write is determined as read-write; and / or According to the control instruction, the abstract attribute of the target register whose initial attribute is error is determined to be error.

7. The code analysis method according to any one of claims 1 to 6, wherein: Generate abstract instructions based on the assembly instructions in the assembly code, including: According to the operation of the assembly instruction on the target register, an abstract instruction corresponding to the assembly instruction is determined, wherein one operation of the assembly instruction on the target register corresponds to one abstract instruction.

8. The code analysis method according to claim 7, wherein: Determining an abstract instruction corresponding to the assembly instruction according to the operation of the assembly instruction on the target register includes: The abstract instruction is determined according to the type of the target register and the operation of the assembly instruction on the target register, wherein the type of the target register includes a general register and / or a special register.

9. The code analysis method according to claim 8, wherein: Determining the abstract instruction according to the type of the target register and the operation of the assembly instruction on the target register includes: Generate a read instruction corresponding to the read operation of the assembly instruction on the general register; and / or Generate a write instruction corresponding to the write operation of the assembly instruction on the general register; and / or Generate a status instruction corresponding to the read operation of the assembly instruction on the special register; and / or Corresponding to the write operation of the assembly instruction to the special register, a control instruction is generated.

10. The code analysis method according to any one of claims 2 to 6, wherein: Determining whether the assembly code has an error according to the abstract attribute of the target register includes: When the abstract attribute of at least one of the target registers is wrong, it is determined that an error exists in the assembly code.

11. The code analysis method according to any one of claims 2 to 6, wherein: Before determining the abstract attribute of at least one target register corresponding to the assembly instruction according to the abstract instruction, the code analysis method further includes: Generate a computation graph according to the assembly code, wherein the computation graph includes a plurality of computation nodes executed sequentially, one computation node corresponds to one abstract instruction, and one operation of the assembly instruction on the target register corresponds to one abstract instruction; Determine the abstract attribute of each of the target registers corresponding to the initial computing node in the computing graph; The abstract attribute of each of the target registers corresponding to the computing nodes other than the initial computing node in the computing graph is set to unknown.

12. The code analysis method according to claim 11, wherein: Determining, according to the abstract instruction, an abstract attribute of at least one target register corresponding to the assembly instruction includes: Determine a set of computing nodes to be analyzed, wherein the set of computing nodes to be analyzed is composed of computing nodes to be analyzed in the computing graph; When the set of computing nodes to be analyzed is not empty, according to the execution order of multiple computing nodes in the computation graph, the computing nodes to be analyzed in the set of computing nodes to be analyzed are selected in turn as current computing nodes, and the following steps are performed: Determining, according to the abstract instruction corresponding to the current computing node, the abstract attribute of each of the target registers corresponding to the current computing node; The computing node to be analyzed that is the current computing node is removed from the computing nodes to be analyzed.

13. The code analysis method according to any one of claims 1 to 6, wherein: Determining the abstract attribute of the target register according to the abstract instruction includes: In the case where a plurality of the abstract instructions converge on the same target register, determining the intermediate abstract attribute of the target register corresponding to each of the abstract instructions according to each of the abstract instructions; Intersection operations are performed on the intermediate abstract attributes of the target register corresponding to each of the abstract instructions to determine the abstract attribute of the target register.

14. The code analysis method according to claim 13, wherein: Performing an intersection operation on the intermediate abstract attributes of the target register corresponding to each of the abstract instructions to determine the abstract attribute of the target register includes: Performing an intersection operation on the non-empty attribute and the unknown, obtaining the abstract attribute of the target register as the non-empty attribute, wherein the non-empty attribute is any one of readable, writable, read-write, unknown, and error; Performing an intersection operation on readable and read-write, obtaining the abstract attribute of the target register as read-write; Performing an intersection operation on writable and read-write, obtaining the abstract attribute of the target register as read-write; Performing an intersection operation on readable and writable, the abstract attribute of the target register is obtained to be an error; The empty attribute and the error are intersected to obtain the abstract attribute of the target register as error.

15. An electronic device, comprising: one or more processors; A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the code analysis method according to any one of claims 1 to 14.

16. A computer-readable medium having a computer program stored thereon, wherein when the program is executed by a processor, the code analysis method according to any one of claims 1 to 14 is implemented.

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