Method for establishing data transmission link and related equipment

Abstract

The invention provides a data transmission link establishment method and related equipment, and the method comprises the steps: configuring interconnection ports of a processing chip and a calculation chip according to a first preset configuration parameter, so as to establish a first data transmission link between the processing chip and the calculation chip, the processing chip scans and discovers the computing chip through the first data transmission link; request information is sent to the computing chip through the first data transmission link, the computing chip returns a confirmation message after receiving the request information, and an interconnection port of the computing chip is configured according to a second preset configuration parameter; and in response to the confirmation message, configuring an interconnection port of the processing chip according to a second preset configuration parameter so as to establish a second data transmission link between the processing chip and the computing chip, the transmission rate of the second data transmission link being greater than the transmission rate of the first data transmission link. According to the invention, rapid link establishment between chips can be realized, and it can be ensured that the finally obtained data transmission link has relatively high data transmission capability.

Description

Technical Field

[0001] The present application relates to the field of Internet technology, and in particular to a method for establishing a data transmission link and related equipment. Background Art

[0002] In a hardware server system composed of multiple chips, the system may be composed of homogeneous chips or heterogeneous chips; the chips work together by exchanging data through the CPU bus / board-level bus. The interconnected board-level bus is PCIe or a bus protocol customized by the hardware manufacturer. At present, the application of multiple heterogeneous chips to form a hardware system is becoming more and more widespread. For example, in HPC, artificial intelligence has been widely used, and artificial intelligence relies on a lot of computing power. The general chips of general servers have reached the limit of Moore's Law and it is difficult to provide higher computer capabilities. Therefore, heterogeneous platforms composed of special chips have emerged for special application scenarios.

[0003] In the related art, in order to meet the requirements of large-scale data transmission between chips, the bandwidth of the interconnection bus between chips is getting larger and larger. However, as the bandwidth increases, it takes longer and longer to establish a physical transmission channel for high-speed interconnection between chips, which seriously affects the availability and versatility of the system. Summary of the invention

[0004] In view of this, the present application provides a method for establishing a data transmission link, which can realize rapid link establishment between chips and ensure that the final data transmission link has a high data transmission capacity.

[0005] The first aspect of the present application provides a method for establishing a data transmission link, comprising: configuring the interconnection ports of a processing chip and a computing chip respectively according to first preset configuration parameters to establish a first data transmission link between the processing chip and the computing chip, wherein the processing chip discovers the computing chip by scanning through the first data transmission link; sending request information to the computing chip through the first data transmission link, wherein the computing chip returns a confirmation message after receiving the request information and configures its own interconnection port according to second preset configuration parameters; in response to the confirmation message, configuring the interconnection port of the processing chip according to the second preset configuration parameters to establish a second data transmission link between the processing chip and the computing chip, wherein the transmission rate of the second data transmission link is greater than the transmission data of the first data transmission link.

[0006] Compared with the related art, the embodiments of the present application have at least the following advantages: by configuring the interconnection ports of the processing chip and the computing chip according to the first preset configuration parameters, a first data transmission link between the processing chip and the computing chip can be quickly established, so that the processing chip can quickly scan and discover the computing chip; and then the interconnection ports of the processing chip and the computing chip are configured according to the second preset configuration parameters to establish a second data transmission link between the processing chip and the computing chip, and the transmission rate of the second data transmission link is greater than the transmission rate of the first data transmission link, thereby improving the data transmission capacity between the processing chip and the computing chip.

[0007] In some possible implementations, the computing chip includes a shared register and a mode switching slave module; the sending of request information to the computing chip through the first data transmission link includes: sending the mode switching request information to the shared register through the first data transmission link; the computing chip returns a confirmation message after receiving the request information, including: the mode switching slave module reads the shared register, and after reading the mode switching request information, writes a mode switching response mark into the shared register; in response to the confirmation message, configuring the interconnection port of the processing chip according to the second preset configuration parameters, including: the processing chip reads the shared register, and after reading the mode switching response mark, configures the interconnection port of the processing chip according to the second preset configuration parameters.

[0008] By adopting this technical solution, a method of reconfiguring the interconnection ports of the processing chip and the computing chip is realized, which can ensure that after the processing chip scans and finds the computing chip, a second data transmission link with a faster transmission rate can be established between the processing chip and the computing chip.

[0009] In some possible implementations, after writing the mode switching response mark into the shared register, it also includes: starting a first timer of the computing chip, wherein the first timer has a first timing value; configuring its own interconnection port according to the second preset configuration parameters includes: after the first timer times out, the computing chip configures its own interconnection port according to the second preset configuration parameters.

[0010] By adopting this technical solution, it can be ensured that after the processing chip reads the mode switching response mark, the computing chip reconfigures its own interconnection port.

[0011] In some possible implementations, after the processing chip reads the mode switching response mark, it also includes: starting a second timer of the processing chip, wherein the second timer has a second timing value, and the second timing value is greater than the first timing value; configuring the interconnection port of the processing chip according to the second preset configuration parameters includes: after the second timer times out, configuring the interconnection port of the processing chip according to the second preset configuration parameters.

[0012] By adopting this technical solution, it is possible to ensure that a second data transmission link with a faster data transmission rate is established between the processing chip and the computing chip.

[0013] In some possible implementations, the processing chip and the computing chip are connected via a PCIe bus.

[0014] By adopting this technical solution, a connection method for a processing chip and a computing chip is provided.

[0015] In some possible implementations, a bus switching chip is further included, and there are multiple computing chips; the processing chip is connected to the bus switching chip via a chip interconnect bus; and the bus switching chip is connected to multiple computing chips via the chip interconnect bus.

[0016] By adopting this technical solution, a connection method between a processing chip and multiple computing chips is provided.

[0017] In some possible implementations, the processing chip includes a first low-speed interconnection port and a first high-speed interconnection port, and the computing chip includes a second low-speed interconnection port and a second high-speed interconnection port; the first low-speed interconnection port and the second low-speed interconnection port are connected via a PCIe bus, and the first high-speed interconnection port and the second high-speed interconnection port are connected via a high-speed interconnection bus; configuring the interconnection ports of the processing chip and the computing chip respectively according to the first preset configuration parameters includes: configuring the first low-speed interconnection port and the second low-speed interconnection port respectively according to the first preset configuration parameters; configuring its own interconnection port according to the second preset configuration parameters includes: configuring the second high-speed interconnection port according to the second preset configuration parameters.

[0018] In some possible implementations, a bus switching chip is also included, and there are multiple computing chips; the processing chip includes a first low-speed interconnection port and a first high-speed interconnection port, and the computing chip includes a second low-speed interconnection port and a second high-speed interconnection port; the first low-speed interconnection port and multiple second low-speed interconnection ports are connected through a PCIe bus; the first high-speed interconnection port is connected to the bus switching chip through a chip interconnection bus, and the bus switching chip is connected to each of the second high-speed interconnection ports through the chip interconnection bus.

[0019] The second aspect of the present application discloses an electronic device, which includes a processor and a memory, wherein the memory is used to store instructions, and the processor is used to call the instructions in the memory so that the electronic device executes the above-mentioned method for establishing a data transmission link.

[0020] The third aspect of the present application discloses a device having the function of implementing the electronic device behavior in the method provided in the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0021] In a fourth aspect, the present application discloses a computer-readable storage medium, comprising computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the above-mentioned method for establishing a data transmission link.

[0022] It can be understood that the electronic device of the second aspect provided above, the device provided in the third aspect, and the computer-readable storage medium of the fourth aspect all correspond to the method of the first aspect mentioned above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of functional modules of a system for establishing a data transmission link provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of the structure of a CPU chip and an AI chip provided in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of a process for establishing a data transmission link between a CPU chip and an AI chip provided in an embodiment of the present application;

[0026] Figure 4 A process for establishing a data transmission link provided in an embodiment of the present application;

[0027] Figure 5A schematic diagram of the structure of a CPU chip, a bus switching chip, and an AI chip provided in an embodiment of the present application;

[0028] Figure 6 A schematic diagram of a process for establishing a data transmission link between a CPU chip, a bus switching chip and an AI chip provided in an embodiment of the present application;

[0029] Figure 7 A schematic diagram of the structure of a CPU chip and an AI chip provided in an embodiment of the present application;

[0030] Figure 8 A schematic diagram of a process for establishing a data transmission link between a CPU chip and an AI chip provided in an embodiment of the present application;

[0031] Fig. 9 A schematic diagram of the structure of a CPU chip, a bus switching chip, and an AI chip provided in an embodiment of the present application;

[0032] Fig.10 A schematic diagram of a process for establishing a data transmission link between a CPU chip, a bus switching chip and an AI chip provided in an embodiment of the present application;

[0033] Fig.11 A schematic diagram of the hardware structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific implementation methods. It should be noted that the implementation methods of the present application and the features in the implementation methods can be combined with each other without conflict.

[0035] In the following description, many specific details are set forth to facilitate a full understanding of the present application. The described implementations are only part of the implementations of the present application, rather than all the implementations.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0037] It should be further noted that, in this article, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0038] In this application, "at least one" means one or more, and "more than one" means two or more than two. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims and drawings of this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0039] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0040] To facilitate understanding, some illustrations of concepts related to the embodiments of the present application are given by way of example for reference.

[0041] Bus switching chip: A chip that implements data forwarding function between multiple chips based on board-level bus interconnection.

[0042] Interconnect port: A port module on a processing chip or computing chip that connects to external devices.

[0043] Shared register: An address space on the interconnect port of a computing chip that can be accessed by the processing chip through the interconnect bus, and can also be accessed by the computing chip to achieve data exchange between the processing chip and the computing chip.

[0044] Heterogeneous system: A system composed of multiple heterogeneous servers.

[0045] Board-level bus: refers to the bus channel that transmits information between the CPU, memory, input and output devices in a computer server, such as PCIe (Peripheral Component Interconnect express, computer interconnect bus standard), CXL (Compute Express Link, computing express interconnect), etc.

[0046] Chip interconnect bus: equivalent to board-level bus.

[0047] PCIe SWITCH: A device that interconnects multiple devices through the PCIe protocol to forward data.

[0048] Please refer to Figure 1 , is a functional module diagram of a data transmission link establishment system provided in an embodiment of the present application. The data transmission link establishment system includes multiple modules, each module is used to implement a different function. In this embodiment, the data transmission link establishment system includes: a processing chip 1 and a computing chip 2.

[0049] The processing chip 1 in this embodiment can be a CPU chip, and the computing chip 2 can be an AI (Artificial Intelligence) chip. The AI ​​chip 2 includes an interconnection port 21, a mode switching slave module 22, and a first interconnection initialization module 23; the CPU chip 1 includes an interconnection port 11, a mode switching master module 12, and a second interconnection initialization module 13. The interconnection ports between the CPU chip 1 and the AI ​​chip 2 are connected through a board-level bus, the mode switching slave module 22 and the first interconnection initialization module 23 are both connected to the interconnection port 21 of the AI ​​chip 2, and the mode switching master module 12 and the second interconnection initialization module 13 are both connected to the interconnection port 11 of the CPU chip 1.

[0050] In some embodiments, the processing chip 1 may also be a chip such as a video codec, a network message processor, etc. This embodiment does not specifically limit the type of the processing chip 1 .

[0051] The following takes the case where the processing chip 1 is a CPU chip as an example to specifically describe the functions of each module included in the CPU chip 1:

[0052] The second interconnection initialization module 13 is a module used to initialize the interconnection port 11 during the startup process of the CPU chip 1. During the power-on initialization phase of the CPU chip 1, the module initializes the register configuration of the interconnection port 11, so that the CPU chip 1 establishes a transmission channel with the interconnection port 21 of the AI ​​chip 2 through the interconnection port 11, and the transmission channel includes the establishment of a physical link and the establishment of a transmission layer; the second interconnection initialization module 13 reads the device information of the AI ​​chip 2 through the board-level bus, completes the scanning and discovery of the AI ​​chip 2, and finally reports the device information to the OS system running on the CPU chip 1.

[0053] The mode switching main module 12 is responsible for sending a low-speed mode switching request to the AI ​​chip 2 via the board-level bus, and then processing the mode switching response fed back by the AI ​​chip 2.

[0054] The following is a detailed description of the functions of each module included in the AI ​​chip 2:

[0055] The first interconnection initialization module 23 is a module used by the AI ​​chip 2 to initialize the interconnection port 21 during the startup process. This module initializes the register configuration of the interconnection port 21 during the power-on initialization phase of the AI ​​chip 2, so that the interconnection port 21 establishes a physical link with other interconnection ports through a low-speed mode, such as establishing a physical link between the interconnection port 21 of the AI ​​chip 2 and the interconnection port 11 of the CPU chip 1; then a transmission channel is established through negotiation based on transmission protocols such as PCIe, CXL, etc. on the physical link; after completing the establishment of the transmission channel in the low-speed mode, the AI ​​chip 2 enters the WFE (Wait For Event) state.

[0056] The mode switching slave module 22 processes the rate mode switching request from the mode switching master module 12, configures the register of the interconnection port 21, and switches the current physical link from the low-speed mode to the high-speed mode.

[0057] In some embodiments, the computing chip 2 may also be a video encoding and decoding chip, a network message processing chip, etc., and the type of the computing chip 2 is not specifically limited.

[0058] For ease of understanding, the following example uses the CPU chip 1 as the processing chip and the AI ​​chip 2 as the computing chip. Figures 1 to 3 How to establish a data transmission link between the CPU chip 1 and the AI ​​chip 2 in this embodiment is specifically described:

[0059] Please refer to Figure 2, which is a structural diagram of the CPU chip and the AI ​​chip provided in the embodiment of the present application. Specifically, the CPU chip 1 includes a second interconnect initialization module 13, a mode switching main module 12 and a PCIe RC (Peripheral Component Interconnect express Root Complex, PCIe root complex) module 14; the AI ​​chip 2 includes a first interconnect initialization module 23, a mode switching slave module 22 and a PCIe EP (PCIe End Point, PCIe terminal equipment) module 24. The PCIe EP module 24 has an ECAM (Enhanced Configuration Access Mechanism) configuration space 241 and a shared register 242. The PCIe RC module 24 and the PCIe EP module 14 are connected via a PCIe bus.

[0060] Please refer to Figure 3 , which is a flow chart of establishing a data transmission link between the CPU chip 1 and the AI ​​chip 2 provided in an embodiment of the present application, combined with Figure 1 and Figure 2 , Figure 3 The specific process shown includes:

[0061] 1. In the scenario of power-on or hot reset of the CPU chip 1, the CPU chip 1 initializes its own interconnection port 11 through the second interconnection initialization module 13, and configures the interconnection port 11 at a relatively low rate according to the first preset configuration parameter. For example, the first preset configuration parameter is the frequency, and the value of the frequency is equal to 2.5Ghz. After configuring the interconnection port 11 at a relatively low rate, the mode switching main module 12 is in a low-speed mode.

[0062] 2. When the AI ​​chip 2 is powered on or hot reset, the AI ​​chip 2 initializes its own interconnection port 21 through the first interconnection initialization module 23, and also configures the interconnection port 21 at a relatively low rate according to the first preset configuration parameter. For example, the first preset configuration parameter is the frequency, and the value of the frequency is equal to 2.5Ghz. After configuring the interconnection port 21 at a relatively low rate, the mode switching slave module 22 is in a low-speed mode.

[0063] 3. After the CPU chip 1 and the AI ​​chip 2 establish a first data transmission link at a low speed, they complete the establishment of transmission protocols such as PCIe and CXL on the first data transmission link.

[0064] 4. The second interconnection initialization module 13 sends a device discovery scan message or a device configuration message to the AI ​​chip 2 through the first data transmission link, and reads the configuration space 241 on the AI ​​chip 2, so that the CPU chip 1 completes the scan and discovery of the AI ​​chip 2. Specifically, the device discovery scan message and the device configuration message are both used by the CPU chip 1 to scan and discover the AI ​​chip 2 and read the configuration space 241 of the AI ​​chip 2. After the CPU chip 1 reads the configuration space 241 of the AI ​​chip 2, the device information of the AI ​​chip 2 will be reported to the OS system of the CPU chip 1.

[0065] 5. The mode switching slave module 22 on the AI ​​chip 2 is converted from the low-speed mode state to the WFE state, the second interconnection initialization module 13 sends the request information to the shared register 242 of the AI ​​chip 2 through the first data transmission link, and the mode switching slave module 22 reads the shared register 242 through an interrupt mode or a loop mode.

[0066] Specifically, the second interconnect initialization module 13 sends the mode switching request value to the shared register 242 through the first data transmission link. Taking the mode switching slave module 22 reading the shared register 242 in a cyclic manner as an example, the mode switching slave module 22 continuously reads the data in the shared register 242 until the mode switching request value is read. After the mode switching slave module 22 reads the mode switching request value, the mode switching slave module 22 writes the mode switching response mark into the shared register 242, and then starts the timer T1, and the timer T1 has a first timing value.

[0067] 6. After timer T1 times out, the AI ​​chip 2 configures the interconnection port 21 according to the second preset configuration parameter. For example, the second preset configuration parameter is the frequency, and the value of the frequency is equal to 100 GHz, so that the interconnection port 21 switches from the low-speed mode to the high-speed mode.

[0068] 7. The mode switching main module 12 reads the shared register 242. After reading the mode switching response mark in the shared register 242, the interconnection port 11 is configured according to the second preset configuration parameter. For example, the second preset configuration parameter is the frequency, and the value of the frequency is equal to 100 GHz, so that the interconnection port 11 is switched from the low-speed mode state to the high-speed mode state. Then, the timer T2 is started, and the timer T2 has a second timing value.

[0069] 8. After timer T2 times out, the interconnection port 11 of CPU chip 1 and the interconnection port 21 of AI chip 2 are both in high-speed mode. At this time, the transmission rate of the second data transmission link between CPU chip 1 and AI chip 2 is much higher than the transmission rate of the first data transmission link. CPU chip 1 reads the device information on AI chip 2 through the second data transmission link.

[0070] Regarding steps 5 to 8, specifically, by setting timer T1, it can be ensured that after the CUP chip 1 reads the mode switching response mark, the AI ​​chip 2 configures the interconnection port 21 according to the second preset configuration parameter. By setting timer T2, and the second timing value is greater than the first timing value, it can be ensured that the interconnection port 11 of the CPU chip 1 and the interconnection port 21 of the AI ​​chip 2 are both converted from the low-speed mode state to the high-speed mode state. In addition, this embodiment does not specifically limit the type and value of the second preset configuration parameter, and can ensure that the transmission rate of the second data transmission link is greater than the transmission rate of the first data transmission link; this embodiment does not specifically limit the size of the first timing value and the second timing value, and can be set according to actual needs.

[0071] Compared with the related art, the embodiments of the present application have at least the following advantages: by configuring the interconnection ports of the processing chip and the computing chip according to the first preset configuration parameters, a first data transmission link between the processing chip and the computing chip can be quickly established, so that the processing chip can quickly scan and discover the computing chip; and then the interconnection ports of the processing chip and the computing chip are configured according to the second preset configuration parameters to establish a second data transmission link between the processing chip and the computing chip, and the transmission rate of the second data transmission link is greater than the transmission rate of the first data transmission link, thereby improving the data transmission capacity between the processing chip and the computing chip.

[0072] Please refer to Figure 4 , which is a flow chart of a method for establishing a data transmission link provided in an embodiment of the present application. This embodiment is applied to a system for establishing a data transmission link in the aforementioned embodiment, and the specific process is as follows Figure 4 As shown, the following steps are included:

[0073] Step 101: configuring interconnection ports of a processing chip and a computing chip respectively according to first preset configuration parameters to establish a first data transmission link between the processing chip and the computing chip.

[0074] In some embodiments, the first preset configuration parameter includes frequency. By configuring the interconnection ports of the processing chip and the computing chip to a relatively low frequency, such as 2.5 GHz, the interconnection ports of the processing chip and the computing chip are both in a low-speed mode, thereby speeding up the generation speed of the first data transmission link between the processing chip and the computing chip, thereby enabling the processing chip to more quickly scan and discover the computing chip through the first data transmission link.

[0075] Step 102: Send request information to the computing chip through the first data transmission link. After receiving the request information, the computing chip returns a confirmation message and configures its own interconnection port according to the second preset configuration parameters.

[0076] In some embodiments, the computing chip includes a shared register and a mode switching slave module. Specifically, the data transmission link establishment system sends the mode switching request information to the shared register through the first data transmission link. After reading the mode switching request information in the shared register, the computing chip writes the mode switching response mark into the shared register and configures its own interconnection port according to the second preset configuration parameter. In this way, the computing chip can be switched from a low-speed mode state to a high-speed mode state.

[0077] In some embodiments, the second preset configuration parameter includes a frequency, and the interconnection port of the computing chip is configured to a relatively high frequency, such as 100 GHz, so that the interconnection port of the computing chip is in a high-speed mode.

[0078] In some embodiments, after the computing chip writes the mode switching response mark into the shared register, the computing chip starts a first timer, and the first timer has a first timing value. After the first timer times out, the computing chip will configure its own interconnection port according to the second preset configuration parameter. In this way, it can be ensured that after the processing chip reads the mode switching response mark, the computing chip reconfigures its own interconnection port.

[0079] Step 103: In response to the confirmation message, configure the interconnection port of the processing chip according to the second preset configuration parameters to establish a second data transmission link between the processing chip and the computing chip.

[0080] In some embodiments, the processing chip reads the shared register, and after the processing chip reads the mode switching response mark, the data transmission link establishment system configures the interconnection port of the processing chip according to the second preset configuration parameter. In this way, the interconnection port of the processing chip can be configured to a relatively high frequency, such as 100 GHz, so that the interconnection port of the processing chip is also in a high-speed mode state.

[0081] It can be understood that after the interconnection ports of the processing chip and the computing chip are configured according to the second preset configuration parameters, a second data transmission link is established between the processing chip and the computing chip.

[0082] In some embodiments, after configuring the interconnection port of the processing chip according to the second preset configuration parameters, the data transmission link establishment system will start the second timer of the processing chip, the second timer has a second timing value, and the second timing value is greater than the first timing value. After the second timer times out, the processing chip reads the device information of the computing chip through the re-established second data transmission link.

[0083] In some embodiments, the data transmission link establishment system further includes a bus switching chip, and there are multiple computing chips. Specifically, the processing chip and the bus switching chip are connected via a chip interconnect bus; the bus switching chip and multiple computing chips are connected via a chip interconnect bus.

[0084] For ease of understanding, the following example uses the CPU chip 1 as the processing chip and the AI ​​chip 2 as the computing chips. Figure 5 and Figure 6 How to establish a data transmission link between the CPU chip 1 and the AI ​​chip 2 in this embodiment is specifically described:

[0085] Please refer to Figure 5 , is a schematic diagram of the structure of the CPU chip 1, bus switching chip 3 and AI chip 2 provided in the embodiment of the present application. The CPU chip 1 includes a second interconnection initialization module 13, a mode switching master module 12 and an interconnection port 11; the AI ​​chip 2 includes an interconnection port 21, a first interconnection initialization module 23, a mode switching slave module 22 and a PCIe EP module 24. The PCIe EP module 24 has an ECAM configuration space 241 and a shared register 242.

[0086] Specifically, AI chip 2 has ECAM configuration space 241 and shared register 242, both of which can be accessed from CPU chip 1 through chip interconnection bus 10, and the physical link between CPU chip 1 and AI chip 2 is interconnected through bus switching chip 3. Bus switching chip 3 is responsible for forwarding transmission messages between CPU chip 1 and AI chip 2. There are two sections in the physical link between CPU chip 1 and AI chip 2: CPU chip 1 / AI chip 2 to bus switching chip 3, and bus switching chip 3 to CPU chip 1 / AI chip 2; the physical link of each section is disconnected, or the rate mode is switched without affecting the physical link status of other sections. For example, the physical link from CPU chip 1 / AI chip 2 to bus switching chip 3 is not established, and the physical link from bus switching chip 3 to CPU chip 1 / AI chip 2 is established; for example, the physical link from CPU chip 1 / AI chip 2 to bus switching chip 3 is in low-speed mode, and the physical link from bus switching chip 3 to CPU chip 1 / AI chip 2 is in high-speed mode.

[0087] Please refer to Figure 6 , which is a flow chart of establishing a data transmission link between the CPU chip 1, the bus switching chip 3 and the AI ​​chip 2 provided in the embodiment of the present application, combined with Figure 5 , Figure 6 The specific process shown includes:

[0088] 1. In the scenario of power-on or hot reset of the CPU chip 1, the CPU chip 1 initializes the interconnection port 11 through the second interconnection initialization module 13, and configures the interconnection port 11 at a relatively low rate according to the first preset configuration parameter. For example, the first preset configuration parameter is the frequency, and the value of the frequency is equal to 2.5Ghz. After configuring the interconnection port 11 at a relatively low rate, the mode switching main module 12 is in a low-speed mode state.

[0089] 2. When the AI ​​chip 2 is powered on or hot reset, the AI ​​chip 2 initializes the interconnection port 21 through the first interconnection initialization module 23, and also configures the interconnection port 21 at a relatively low rate according to the first preset configuration parameter. For example, the first preset configuration parameter is the frequency, and the value of the frequency is equal to 2.5Ghz. After configuring the interconnection port 21 at a relatively low rate, the mode switching slave module 22 is in a low-speed mode.

[0090] 3. When the bus switch chip 3 is powered on or hot reset, the bus switch chip 3 configures its own interconnection port according to the first preset configuration parameter.

[0091] 4. A physical link is established between the CPU chip 1 and the bus switching chip 3 at a low speed; a physical link is established between the AI ​​chip 2 and the bus switching chip 3 at a low speed.

[0092] 5. There is a first data transmission link between the CPU chip 1 and the AI ​​chip 2, and the establishment of transmission protocols such as PCIe and CXL is completed on the first data transmission link.

[0093] 6. The second interconnection initialization module 13 sends a device discovery scan message or a device configuration message to the AI ​​chip 2 through the first data transmission link, and reads the configuration space 241 on the AI ​​chip 2, so that the CPU chip 1 completes the scan and discovery of the AI ​​chip 2. Specifically, the device discovery scan message and the device configuration message are both used to scan and discover the AI ​​chip 2 and read the configuration space 241 of the AI ​​chip 2. After the CPU chip 1 reads the configuration space 241 of the AI ​​chip 2, the device information of the AI ​​chip 2 will be reported to the OS system of the CPU chip 1.

[0094] 7. The mode switching slave module 22 on the AI ​​chip 2 is converted from the low-speed mode state to the WFE state, the second interconnection initialization module 13 sends the request information to the shared register 242 of the AI ​​chip 2 through the first data transmission link, and the mode switching slave module 22 reads the shared register 242 through an interrupt mode or a loop mode.

[0095] Specifically, the second interconnect initialization module 13 sends the mode switching request value to the shared register 242 through the first data transmission link. Taking the mode switching slave module 22 reading the shared register 242 in a cyclic manner as an example, the mode switching slave module 22 continuously reads the data in the shared register 242 until the mode switching request value is read. After the mode switching slave module 22 reads the mode switching request value, the mode switching slave module 22 writes the mode switching response mark into the shared register 242, and then starts the timer T1, and the timer T1 has a first timing value.

[0096] 8. After timer T1 times out, AI chip 2 sends a high-speed mode switching message to bus switching chip 3 to notify bus switching chip 3 to configure its own interconnection port according to the second preset configuration parameter; AI chip 2 will also configure interconnection port 21 according to the second preset configuration parameter. For example, the second preset configuration parameter is frequency, and the value of frequency is equal to 100Ghz, so that interconnection port 21 switches from low-speed mode to high-speed mode.

[0097] 9. The bus switching chip 3 switches all its interconnection ports from the low-speed mode to the high-speed mode.

[0098] 10. The mode switching main module 12 reads the shared register 242. After reading the mode switching response mark in the shared register 242, the interconnection port 11 is configured according to the second preset configuration parameter. For example, the second preset configuration parameter is the frequency, and the value of the frequency is equal to 100 GHz, so that the interconnection port 11 is switched from the low-speed mode state to the high-speed mode state. Then, the timer T2 is started, and the timer T2 has a second timing value.

[0099] 11. After timer T2 times out, the interconnection port 11 of the CPU chip 1 and the interconnection port 21 of the AI ​​chip 2 are both in high-speed mode. At this time, the transmission rate of the second data transmission link between the CPU chip 1 and the AI ​​chip 2 is greater than the transmission rate of the first data transmission link, and the CPU chip 1 reads the device information on the AI ​​chip 2 through the second data transmission link.

[0100] In some embodiments, the processing chip includes a first low-speed interconnection port and a first high-speed interconnection port, and the computing chip includes a second low-speed interconnection port and a second high-speed interconnection port; the first low-speed interconnection port and the second low-speed interconnection port are connected through a PCIe bus, and the first high-speed interconnection port and the second high-speed interconnection port are connected through a high-speed interconnection bus; the interconnection ports of the processing chip and the computing chip are respectively configured according to the first preset configuration parameters, including: configuring the first low-speed interconnection port and the second low-speed interconnection port respectively according to the first preset configuration parameters; configuring its own interconnection port according to the second preset configuration parameters, including: configuring the second high-speed interconnection port according to the second preset configuration parameters.

[0101] For ease of understanding, the following example takes the processing chip as CPU chip 1, the computing chip as AI chip 2, the first low-speed interconnection port as PCIe RC module 14, the first high-speed interconnection port as interconnection port 11 of CPU chip 1; the second low-speed interconnection port as PCIe EP module 24, and the second high-speed interconnection port as interconnection port 21 of AI chip 2 as an example. Figure 7 and Figure 8 How to establish a data transmission link between the CPU chip and the AI ​​chip in this embodiment is specifically described:

[0102] Please refer to Figure 7 , which is a schematic diagram of the structure of the CPU chip and the AI ​​chip provided in the embodiment of the present application. The CPU chip 1 includes two ports, one is a PCIe RC module 14 for connecting to the PCIe bus 20, and the other is an interconnection port 11 for connecting to the high-speed interconnection bus 30; the AI ​​chip 2 also includes two ports, one is a PCIe EP module 24 for connecting to the PCIe bus 20, and the other is an interconnection port 21 for connecting to the high-speed interconnection bus 30.

[0103] Specifically, the PCIe bus 20 is a low-bandwidth, low-speed interconnect bus; the high-speed interconnect bus 30 is a high-bandwidth, high-speed interconnect bus.

[0104] In some embodiments, the PCIe RC module 14 and the PCIe EP module 24 may be connected via a low-speed bus such as USB or I2C in addition to the PCIe bus 20. In other words, this embodiment does not specifically limit the type of the low-speed connection bus between the PCIe RC module 14 and the PCIe EP module 24.

[0105] Please refer to Figure 8 , which is a flow chart of establishing a data transmission link between the CPU chip 1 and the AI ​​chip 2 provided in an embodiment of the present application, combined with Figure 7 , Figure 8 The specific process shown includes:

[0106] 1. In the scenario of power-on or hot reset of CPU chip 1, CPU chip 1 initializes PCIe RC module 14 through second interconnect initialization module 13, and configures PCIe RC module 14 at a relatively low rate according to first preset configuration parameter. For example, the first preset configuration parameter is frequency, and the value of frequency is equal to 2.5Ghz. After configuring PCIe RC module 14 at a relatively low rate, mode switching main module 12 is in low speed mode.

[0107] 2. When the AI ​​chip 2 is powered on or hot reset, the AI ​​chip 2 initializes the PCIe EP module 24 through the first interconnect initialization module 23, and also configures the PCIe EP module 24 at a relatively low rate according to the first preset configuration parameter. For example, the first preset configuration parameter is the frequency, and the value of the frequency is equal to 2.5 GHz. After configuring the PCIe EP module 24 at a relatively low rate, the mode switching slave module 22 is in a low-speed mode.

[0108] 3. The CPU chip 1 and the AI ​​chip 2 establish a first data transmission link on the PCIe bus 20.

[0109] 4. The second interconnection initialization module 13 sends a device discovery scan message or a device configuration message to the AI ​​chip 2 through the PCIe bus 20, and reads the configuration space 241 on the AI ​​chip 2, so that the CPU chip 1 completes the scan and discovery of the AI ​​chip 2. At this time, the CPU chip 1 completes the first stage initialization of the AI ​​chip 2. Specifically, the device discovery scan message and the device configuration message are both used to scan and discover the AI ​​chip 2 and read the configuration space 241 of the AI ​​chip 2. After the CPU chip 1 reads the configuration space 241 of the AI ​​chip 2, the device information of the AI ​​chip 2 will be reported to the OS system of the CPU chip 1.

[0110] 5. The mode switching slave module 22 on the AI ​​chip 2 is converted from the low-speed mode state to the WFE state, and the mode switching master module 12 on the CPU chip 1 enters the mode switching state from the first stage of device initialization. The second interconnection initialization module 13 sends a request message to the shared register 242 of the AI ​​chip 2 through the PCIe bus 20, and the mode switching slave module 22 reads the shared register 242 through an interrupt or a loop.

[0111] Specifically, the second interconnect initialization module 13 sends the mode switching request value to the shared register 242 through the PCIe bus 20. Taking the mode switching slave module 22 reading the shared register 242 in a cyclic manner as an example, the mode switching slave module 22 continuously reads the data in the shared register 242 until the mode switching request value is read. After the mode switching slave module 22 reads the mode switching request value, the mode switching slave module 22 writes the mode switching response mark into the shared register 242.

[0112] 6. The AI ​​chip 2 configures the interconnection port 21 according to the second preset configuration parameter. For example, the second preset configuration parameter is the frequency, and the value of the frequency is equal to 100 GHz, so that the interconnection port 21 switches from the low-speed mode to the high-speed mode.

[0113] 7. The mode switching main module 12 reads the shared register 242. After reading the mode switching response mark in the shared register 242, the interconnection port 11 is configured according to the second preset configuration parameter. For example, the second preset configuration parameter is the frequency, and the value of the frequency is equal to 100Ghz, so that the interconnection port 11 is switched from the low-speed mode state to the high-speed mode state.

[0114] 8. The interconnection port 11 of the CPU chip 1 and the interconnection port 21 of the AI ​​chip 2 are both in high-speed mode. At this time, the CPU chip 1 and the AI ​​chip 2 establish a second data transmission link on the high-speed interconnection bus 30. The transmission rate of the second data transmission link is much higher than the transmission rate of the first data transmission link. The CPU chip 1 reads the device information on the AI ​​chip 2 through the second data transmission link.

[0115] In some embodiments, the system for establishing a data transmission link also includes a bus switching chip, and there are multiple computing chips; the processing chip includes a first low-speed interconnection port and a first high-speed interconnection port, and the computing chip includes a second low-speed interconnection port and a second high-speed interconnection port; the first low-speed interconnection port and multiple second low-speed interconnection ports are all connected through a PCIe bus; the first high-speed interconnection port is connected to the bus switching chip through a chip interconnection bus, and the bus switching chip is connected to each second high-speed interconnection port through a chip interconnection bus.

[0116] For ease of understanding, the following example uses the CPU chip 1 as the processing chip and the AI ​​chip 2 as the computing chips. Fig. 9 and Fig.10 How to establish a data transmission link between the CPU chip 1 and the AI ​​chip 2 in this embodiment is specifically described:

[0117] Please refer to Fig. 9 , is a structural diagram of a CPU chip 1, a bus switching chip 3 and an AI chip 2 provided in an embodiment of the present application. The CPU chip 1 includes a second interconnect initialization module 13, a mode switching master module 12, an interconnect port 11 and a PCIe RC module 14; the AI ​​chip 2 includes an interconnect port 21, a first interconnect initialization module 23, a mode switching slave module 22 and a PCIe EP module 24. The PCIe EP module 24 has an ECAM configuration space 241 and a shared register 242.

[0118] Specifically, AI chip 2 has ECAM configuration space 241 and shared register 242, both of which can be accessed from CPU chip 1 through PCIe bus 20, and the physical links between CPU chip 1 and AI chip 2 are interconnected through bus switch chip 3. Bus switch chip 3 is responsible for forwarding transmission messages between the two chips. There are two sections in the physical link between the two chips: CPU chip 1 / AI chip 2 to bus switch chip 3, and bus switch chip 3 to CPU chip 1 / AI chip 2; the physical link of each section is disconnected, or the rate mode is switched, which does not affect the physical link status of other sections. For example, the physical link from CPU chip 1 / AI chip 2 to bus switch chip 3 is not established, and the physical link from bus switch chip 3 to CPU chip 1 / AI chip 2 is established.

[0119] Please refer to Fig.10 , is a flow chart of establishing a data transmission link between the CPU chip 1, the bus switching chip 3 and the AI ​​chip 2 provided in an embodiment of the present application, and the specific process includes:

[0120] 1. In the scenario of power-on or hot reset of CPU chip 1, CPU chip 1 initializes PCIe RC module 14 through second interconnect initialization module 13, and configures PCIe RC module 14 at a relatively low rate according to first preset configuration parameter. For example, the first preset configuration parameter is frequency, and the value of frequency is equal to 2.5Ghz. After configuring PCIe RC module 14 at a relatively low rate, mode switching main module 12 is in low speed mode.

[0121] 2. When the AI ​​chip 2 is powered on or hot reset, the AI ​​chip 2 initializes the PCIe EP module 24 through the first interconnect initialization module 23, and also configures the PCIe EP module 24 at a relatively low rate according to the first preset configuration parameter. For example, the first preset configuration parameter is the frequency, and the value of the frequency is equal to 2.5 GHz. After configuring the PCIe EP module 24 at a relatively low rate, the mode switching slave module 22 is in a low-speed mode.

[0122] 3. The second interconnection initialization module 13 sends device discovery scan information or device configuration message to the AI ​​chip 2 through the PCIe bus 20, and reads the configuration space 241 on the AI ​​chip 2, so that the CPU chip 1 completes the scan discovery of the AI ​​chip 2. At this time, the CPU chip 1 completes the first stage initialization of the AI ​​chip 2. Specifically, the device discovery scan message and the device configuration message are both used to scan and discover the AI ​​chip 2 and read the configuration space 241 of the AI ​​chip 2. After the CPU chip 1 reads the configuration space 241 of the AI ​​chip 2, the device information of the AI ​​chip 2 will be reported to the OS system of the CPU chip 1.

[0123] 4. The mode switching slave module 22 on the AI ​​chip 2 is converted from the low-speed mode state to the WFE state, and the mode switching master module 12 on the CPU chip 1 enters the mode switching state from the first stage of device initialization. The second interconnection initialization module 13 sends a request message to the shared register 242 of the AI ​​chip 2 through the PCIe bus 20, and the mode switching slave module 22 reads the shared register 242 through an interrupt or a loop.

[0124] Specifically, the second interconnect initialization module 13 sends the mode switching request value to the shared register 242 through the PCIe bus 20. Taking the mode switching slave module 22 reading the shared register 242 in a cyclic manner as an example, the mode switching slave module 22 continuously reads the data in the shared register 242 until the mode switching request value is read. After the mode switching slave module 22 reads the mode switching request value, the mode switching slave module 22 writes the mode switching response mark into the shared register 242.

[0125] 5. The AI ​​chip 2 also configures the interconnection port 21 according to the second preset configuration parameter. For example, the second preset configuration parameter is the frequency, and the value of the frequency is equal to 100 GHz, so that the interconnection port 21 switches from the low-speed mode to the high-speed mode. After the interconnection port 21 is in the high-speed mode, the mode switching slave module 22 writes the mode switching completion mark into the shared register 242.

[0126] 6. AI chip 2 sends a mode switching message to bus switch chip 3, and bus switch chip 3 configures the interconnection ports with CPUI chip 1 and AI chip 2 according to the second preset configuration parameters.

[0127] 7. The mode switching main module 12 reads the shared register 242. After reading the mode switching response mark in the shared register 242, the interconnection port 11 is configured according to the second preset configuration parameter. For example, the second preset configuration parameter is the frequency, and the value of the frequency is equal to 100Ghz, so that the interconnection port 11 is switched from the low-speed mode state to the high-speed mode state.

[0128] 8. The interconnection ports of the CPU chip 1 , the AI ​​chip 2 and the bus switching chip 3 are all in high-speed mode, that is, a high-speed interconnection bus 30 is established between the CPU chip 1 , the AI ​​chip 2 and the bus switching chip 3 .

[0129] 9. The CPU chip 1 reads the mode switching completion mark in the shared register 242 through the PCIe bus 20, and the CPU chip 1 reads the device information on the AI ​​chip 2 through the high-speed interconnect bus 30.

[0130] Compared with the related art, the embodiments of the present application have at least the following advantages: by configuring the interconnection ports of the processing chip and the computing chip according to the first preset configuration parameters, a first data transmission link between the processing chip and the computing chip can be quickly established, so that the processing chip can quickly scan and discover the computing chip; and then the interconnection ports of the processing chip and the computing chip are configured according to the second preset configuration parameters to establish a second data transmission link between the processing chip and the computing chip, and the transmission rate of the second data transmission link is greater than the transmission rate of the first data transmission link, thereby improving the data transmission capacity between the processing chip and the computing chip.

[0131] Please refer to Fig.11 , is a schematic diagram of the hardware structure of the electronic device 1000 provided in the embodiment of the present application. Fig.11 As shown, the electronic device 1000 may include a processor 1001 and a memory 1002. The memory 1002 is used to store one or more computer programs 1003. The one or more computer programs 1003 are configured to be executed by the processor 1001. The one or more computer programs 1003 include instructions, and the above instructions can be used to implement the above method in the electronic device 1000.

[0132] It is understandable that the structure shown in this embodiment does not constitute a specific limitation on the electronic device 1000. In other embodiments, the electronic device 1000 may include more or fewer components than shown, or combine or separate some components, or arrange the components differently.

[0133] The processor 1001 may include one or more processing units, for example, the processor 1001 may include an application processor (AP), a modem, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0134] The processor 1001 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 1001 is a cache memory. The memory may store instructions or data that the processor 1001 has just used or circulated. If the processor 1001 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 1001, and thus improves the efficiency of the system.

[0135] In some embodiments, the processor 1001 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a SIM interface, and / or a USB interface, etc.

[0136] In some embodiments, memory 1002 may include high-speed random access memory and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0137] In addition, an embodiment of the present application also provides a device, which may specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer-executable instructions, and when the device is running, the processor may execute the computer-executable instructions stored in the memory so that the chip executes the methods in the above-mentioned method embodiments.

[0138] This embodiment further provides a computer-readable storage medium, in which computer instructions are stored. When the instructions are executed on an electronic device, the electronic device executes the above-mentioned related method steps to implement the method in the above-mentioned embodiment.

[0139] Among them, the electronic device and computer storage medium provided in this embodiment are used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0140] In practical applications, the above functions can be distributed to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0141] In several embodiments provided in the present application, the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are schematic. For example, the division of the modules or units is a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0142] The unit described as a separate component may or may not be physically separated, and the component shown as a unit may be one physical unit or multiple physical units, that is, it may be located in one place or distributed in multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.

[0143] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0144] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium, including several instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program code.

[0145] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application.

Claims

1. A method for establishing a data transmission link, characterized in that: include: configuring interconnection ports of the processing chip and the computing chip respectively according to first preset configuration parameters to establish a first data transmission link between the processing chip and the computing chip, wherein the processing chip scans and discovers the computing chip through the first data transmission link; Sending request information to the computing chip through the first data transmission link, wherein the computing chip returns a confirmation message after receiving the request information and configures its own interconnection port according to the second preset configuration parameters; In response to the confirmation message, the interconnection port of the processing chip is configured according to the second preset configuration parameters to establish a second data transmission link between the processing chip and the computing chip, wherein the transmission rate of the second data transmission link is greater than the transmission rate of the first data transmission link.

2. The method for establishing a data transmission link according to claim 1, characterized in that: The computing chip includes a shared register and a mode switching slave module; The sending the request information to the computing chip through the first data transmission link includes: Sending mode switching request information to the shared register through the first data transmission link; The computing chip returns a confirmation message after receiving the request information, including: The mode switching slave module reads the shared register, and after reading the mode switching request information, writes a mode switching response mark into the shared register; The step of configuring the interconnection port of the processing chip according to the second preset configuration parameter in response to the confirmation message includes: The processing chip reads the shared register, and after reading the mode switching response mark, configures the interconnection port of the processing chip according to the second preset configuration parameter.

3. The method for establishing a data transmission link according to claim 2, characterized in that: After writing the mode switching response flag into the shared register, the method further comprises: Starting a first timer of the computing chip, wherein the first timer has a first timing value; The configuring the interconnection port according to the second preset configuration parameter includes: After the first timer times out, the computing chip configures its own interconnection port according to the second preset configuration parameters.

4. The method for establishing a data transmission link according to claim 3, characterized in that: After configuring the interconnection port of the processing chip according to the second preset configuration parameter, the method further includes: Starting a second timer of the processing chip, wherein the second timer has a second timing value, and the second timing value is greater than the first timing value; After the second timer times out, the device information of the computing chip is read according to the second data transmission link.

5. The method for establishing a data transmission link according to claim 1, characterized in that: The processing chip and the computing chip are connected via a PCIe bus.

6. The method for establishing a data transmission link according to claim 1, characterized in that: It also includes a bus switching chip, and the computing chip is multiple; The processing chip is connected to the bus switching chip via a chip interconnect bus; The bus switching chip and the plurality of computing chips are connected via the chip interconnection bus.

7. The method for establishing a data transmission link according to claim 1, characterized in that: The processing chip includes a first low-speed interconnection port and a first high-speed interconnection port, and the computing chip includes a second low-speed interconnection port and a second high-speed interconnection port; The first low-speed interconnection port is connected to the second low-speed interconnection port via a PCIe bus, and the first high-speed interconnection port is connected to the second high-speed interconnection port via a high-speed interconnection bus; The step of respectively configuring the interconnection ports of the processing chip and the computing chip according to the first preset configuration parameter includes: respectively configuring the first low-speed interconnection port and the second low-speed interconnection port according to the first preset configuration parameters; The configuring the interconnection port according to the second preset configuration parameter includes: The second high-speed interconnect port is configured according to the second preset configuration parameters.

8. The method for establishing a data transmission link according to claim 1, characterized in that: It also includes a bus switching chip, the computing chip is multiple; the processing chip includes a first low-speed interconnection port and a first high-speed interconnection port, and the computing chip includes a second low-speed interconnection port and a second high-speed interconnection port; The first low-speed interconnection port and the plurality of the second low-speed interconnection ports are all connected via a PCIe bus; The first high-speed interconnection port is connected to the bus switching chip via a chip interconnection bus, and the bus switching chip is connected to each of the second high-speed interconnection ports via the chip interconnection bus.

9. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory is used to store instructions, and the processor is used to call the instructions in the memory, so that the electronic device executes the method according to any one of claims 1 to 8.

10. A chip coupled to a memory in an electronic device, characterized in that: The chip is used to control the electronic device to execute the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The method comprises computer instructions, which, when executed on an electronic device, cause the electronic device to execute the method according to any one of claims 1 to 8.

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