Data transmission method and device, equipment and storage medium

Abstract

The embodiment of the invention provides a data transmission method and device, equipment and a storage medium, and the method comprises the steps: determining the number of initial period time blocks corresponding to a preset clock signal, determining a target proportion according to the preset clock signal, and transmitting the target proportion to a server; the target proportion is used for representing the proportion of the number of to-be-delayed first time blocks of the preset clock signal to the number of initial period time blocks, and sending the data signal according to the target proportion. According to the method, the stability of data transmission is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of data processing, and specifically relates to a data transmission method, device, equipment and storage medium. Background Art

[0002] Secure Digital Input Output (SDIO) is an interface specification developed based on the secure digital standard. The SDIO interface can be set in the host device to expand the functions of the host device. For example, the host device can communicate with slave devices such as Bluetooth modules and wireless network cards through the SDIO interface.

[0003] During the SDIO data transmission process, the controller of the host device or the controller of the slave device can collect or send SDIO data according to the timing required by the specification. The chip where the controller is located may cause timing instability due to external factors such as voltage and temperature, resulting in signal offset. When the offset is within a reasonable range, the data transmission of both parties is not affected.

[0004] In the above data transmission process, when the influence of external factors is large, the signal offset exceeds a reasonable range, resulting in low stability of data transmission. Summary of the invention

[0005] The embodiments of the present application relate to a data transmission method, apparatus, device and storage medium, which are used to solve the defect in the prior art that when the influence of external factors is large, the signal offset exceeds a reasonable range, resulting in low stability of data transmission.

[0006] In a first aspect, an embodiment of the present application provides a data transmission method, including:

[0007] Determine the number of initial cycle time blocks corresponding to the preset clock signal;

[0008] Determine a target ratio according to the preset clock signal, where the target ratio is used to represent the ratio of the number of first time blocks to be delayed by the preset clock signal to the number of time blocks of the initial cycle;

[0009] A data signal is sent according to the target proportion.

[0010] In a possible implementation manner, determining a target proportion according to the preset clock signal includes:

[0011] Determine the type of device that sends the data signal, where the device type includes a host type and a slave type;

[0012] Determining the first time block quantity according to the preset clock signal and the device type;

[0013] The ratio of the first time block number to the initial cycle time block number is determined as the target ratio.

[0014] In a possible implementation manner, the device type is a host type, and determining the first number of time blocks according to the preset clock signal and the device type includes:

[0015] Determine a sampling time corresponding to the preset clock signal;

[0016] Determining a transmission time period corresponding to the data signal through link training;

[0017] Determine the effective time corresponding to the transmission time period;

[0018] The number of time blocks between the clock time block corresponding to the sampling time and the central time block corresponding to the effective time is determined as the first number of time blocks.

[0019] In a possible implementation manner, determining the transmission time period corresponding to the data signal through link training includes:

[0020] Acquire multiple sampling information through a host device;

[0021] Determine whether there are multiple sampling information with similarities less than a threshold value among the multiple sampling information;

[0022] If so, the sampling moments corresponding to the plurality of sampling information whose similarities are less than the threshold are determined, and the time periods in which the plurality of sampling moments are located are determined as the transmission time period corresponding to the data signal.

[0023] In a possible implementation, obtaining a plurality of sampling information through a host device includes:

[0024] Sending an i-th request information to the slave device through the host device;

[0025] Determine, by the host device, an i-th sampling time, wherein the i-th sampling time is a sampling time corresponding to delaying the preset clock signal by i time blocks;

[0026] Sampling, by the host device, the i-th response information sent by the slave device at the i-th sampling time to obtain i-th sampling information;

[0027] Herein, the i is 1, ..., n in sequence, and n is the number of the initial periodic time blocks.

[0028] In a possible implementation manner, the device type is a slave type, and determining the first number of time blocks according to the preset clock signal and the device type includes:

[0029] Get the delay parameters in the transport protocol;

[0030] The first time block quantity is determined according to the delay parameter and the preset clock signal.

[0031] In a possible implementation manner, sending a data signal according to the target proportion includes:

[0032] Determine the number of current cycle time blocks corresponding to the preset clock signal;

[0033] Determine the target number of time blocks according to the target proportion and the number of time blocks in the current cycle;

[0034] According to the target time block number, delaying the preset clock signal to obtain a target clock signal;

[0035] The target clock signal and the data signal are sent simultaneously.

[0036] In a second aspect, an embodiment of the present application provides a data transmission device, including:

[0037] A first determining module, used to determine the number of initial cycle time blocks corresponding to a preset clock signal;

[0038] A second determination module is used to determine a target ratio according to the preset clock signal, where the target ratio is used to represent the ratio of the number of first time blocks to be delayed of the preset clock signal to the number of initial cycle time blocks;

[0039] The transmission module is used to send a data signal according to the target proportion.

[0040] In a possible implementation manner, the second determining module is specifically configured to:

[0041] Determine the type of device that sends the data signal, where the device type includes a host type and a slave type;

[0042] Determining the first time block quantity according to the preset clock signal and the device type;

[0043] The ratio of the first time block number to the initial cycle time block number is determined as the target ratio.

[0044] In a possible implementation manner, the device type is a host type, and the second determining module is specifically configured to:

[0045] Determine a sampling time corresponding to the preset clock signal;

[0046] Determining a transmission time period corresponding to the data signal through link training;

[0047] Determine the effective time corresponding to the transmission time period;

[0048] The number of time blocks between the clock time block corresponding to the sampling time and the central time block corresponding to the effective time is determined as the first number of time blocks.

[0049] In a possible implementation manner, the second determining module is specifically configured to:

[0050] Acquire multiple sampling information through a host device;

[0051] Determine whether there are multiple sampling information with similarities less than a threshold value among the multiple sampling information;

[0052] If so, the sampling moments corresponding to the plurality of sampling information whose similarities are less than the threshold are determined, and the time periods in which the plurality of sampling moments are located are determined as the transmission time period corresponding to the data signal.

[0053] In a possible implementation manner, the second determining module is specifically configured to:

[0054] Sending an i-th request information to the slave device through the host device;

[0055] Determine, by the host device, an i-th sampling time, wherein the i-th sampling time is a sampling time corresponding to delaying the preset clock signal by i time blocks;

[0056] Sampling, by the host device, the i-th response information sent by the slave device at the i-th sampling time to obtain i-th sampling information;

[0057] Herein, the i is 1, ..., n in sequence, and n is the number of the initial periodic time blocks.

[0058] In a possible implementation manner, the device type is a slave type, and the second determining module is specifically configured to:

[0059] Get the delay parameters in the transport protocol;

[0060] The first time block quantity is determined according to the delay parameter and the preset clock signal.

[0061] In a possible implementation manner, the transmission module is specifically used to:

[0062] Determine the number of current cycle time blocks corresponding to the preset clock signal;

[0063] Determine the target number of time blocks according to the target proportion and the number of time blocks in the current cycle;

[0064] According to the target time block number, delaying the preset clock signal to obtain a target clock signal;

[0065] The target clock signal and the data signal are sent simultaneously.

[0066] In a third aspect, the present application provides a chip having a computer program stored thereon, wherein when the computer program is executed by the chip, the data transmission method as described in any one of the first aspects is implemented.

[0067] In a fourth aspect, the present application provides a chip module having a computer program stored thereon, and when the computer program is executed by the chip module, the data transmission method as described in any one of the first aspects is implemented.

[0068] In a fifth aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor, and a transceiver;

[0069] The memory stores computer-executable instructions;

[0070] The processor executes the computer-executable instructions stored in the memory to implement the data transmission method as described in any one of the first aspects.

[0071] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer execution instructions, and when the computer execution instructions are executed by a processor, they are used to implement the data transmission method described in any one of the first aspects.

[0072] In a seventh aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the data transmission method described in any one of the first aspects.

[0073] The embodiment of the present application provides a data transmission method, device, equipment and storage medium, in which the method determines the number of initial cycle time blocks corresponding to a preset clock signal, determines a target ratio according to the preset clock signal, and the target ratio is used to represent the ratio of the number of first time blocks to be delayed by the preset clock signal to the number of initial cycle time blocks, and sends a data signal according to the target ratio. In this way, the communication parties maintain a fixed ratio for transmission to ensure that both parties can correctly sample valid data, thereby improving the stability of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] In order to more clearly illustrate the technical solutions in the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0075] Figure 1 A schematic diagram of an application scenario provided for an embodiment of the present application;

[0076] Figure 2 A timing diagram of a controller output signal provided in an embodiment of the present application;

[0077] Figure 3 A timing diagram of another controller output signal provided in an embodiment of the present application;

[0078] Figure 4 A timing diagram of another controller output signal provided in an embodiment of the present application;

[0079] Figure 5 A flowchart of a data transmission method provided in an embodiment of the present application;

[0080] Figure 6 A flowchart of another data transmission method provided in an embodiment of the present application;

[0081] Figure 7 A timing diagram of another controller output signal provided in an embodiment of the present application;

[0082] Figure 8 A timing diagram of another controller output signal provided in an embodiment of the present application;

[0083] Fig. 9 A flowchart of another data transmission method provided in an embodiment of the present application;

[0084] Fig.10 A schematic diagram of the structure of a data transmission device provided in an embodiment of the present application;

[0085] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0086] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0087] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0088] It should be noted that, although the terms "first", "second", etc. are used to describe various information in the embodiments of the present application, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. Optionally, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information.

[0089] It should be understood that the terms "comprises" and "includes" indicate the presence of the previously mentioned features, steps, operations, but do not exclude the presence, occurrence or addition of one or at least one other feature, step, operation. The terms "and / or" and the like used in this application may be interpreted as inclusive, or mean any one or any combination. Optionally, "A and / or B" means "any of the following: A; B; A and B". In addition, the character " / " in this article generally indicates that the objects associated before and after are in an "or" relationship.

[0090] In the related art, Secure Digital Input Output (SDIO) is an interface specification developed on the basis of the secure digital standard. An SDIO interface can be set in a host device to expand the functions of the host device. For example, the host device can communicate with slave devices such as Bluetooth modules and wireless network cards through the SDIO interface.

[0091] During the transmission of SDIO data, the controller of the host device or the controller of the slave device can collect or send the SDIO data according to the timing required by the specification.

[0092] Next, combine Figure 1 , an example is given to illustrate the application scenario of transmitting SDIO data.

[0093] Figure 1 This is a schematic diagram of an application scenario provided by the embodiment of this application. Figure 1 , Figure 1It may include a main controller 101 corresponding to the host device and a slave controller 102 corresponding to the slave device. SDIO data may be transmitted between the main controller 101 and the slave controller 102. In SDIO data transmission, three transmission lines may be included between the main controller 101 and the slave controller 102, namely CLK, CMD, and DAT[7:0].

[0094] The master controller 101 may perform an initialization operation after detecting the slave device. The initialization operation may include sending multiple commands and parameters through CMD to identify the type, function and operation mode supported by the slave device.

[0095] The slave controller 102 may respond to the initialization request of the host device by sending the relevant information of the slave device to the host device via CMD. The relevant information may include the device's identity, version number, supported command set, etc.

[0096] The master controller 101 may send multiple commands to the slave device via CMD, and the commands may be used to control data transmission, configure device parameters, request status information, etc.

[0097] The slave controller 102 may execute corresponding operations after receiving a command through CMD, and return response information to the host device through CMD. The response information may be used to indicate the execution result of the command or to provide the requested data.

[0098] The master controller 101 may send a read command and a write command to the slave device via CMD.

[0099] The read command can be used to indicate the address and length of the data to be read, so that the slave device reads the data from the specified address and transmits it to the host device bit by bit or byte by byte through DAT[7:0].

[0100] The write command may be used to indicate the address of data to be written and to provide the data to be written so that the data is transferred from the host device to the slave device through DAT[7:0] and the data is stored at the specified address.

[0101] During the data transmission process, the main controller 101 can provide a clock signal through CLK, and the clock signal can synchronize the data transmission between the host and the device to ensure the accuracy and integrity of the data.

[0102] Next, combine Figure 2 , the data transmission process is further illustrated with examples.

[0103] Figure 2 A timing diagram of a controller output signal provided in an embodiment of the present application. Figure 2 , Figure 2It may include a clock signal corresponding to CLK and a signal corresponding to CMD or DAT[7:0].

[0104] There is a sampling bit on each rising edge of the clock signal corresponding to CLK, and the sampling bit is used to indicate the time point of sampling the data on CMD or DAT[7:0].

[0105] There are multiple valid windows in the signal corresponding to CMD or DAT[7:0]. The valid windows can be based on the low input voltage (Low Input Voltage, V iL ) and High Input Voltage (V IH ), and other parameters. When the sampling bit is within the valid window, the level state of the data can be accurately identified and interpreted as the corresponding logical value, ensuring the accuracy of data transmission. When the sampling bit is not within the valid window, it may cause a read error, affecting the reliability of the entire data transmission.

[0106] In order to ensure that the sampling bit is located in the valid window, link training can be performed before data transmission to determine the number of delay time blocks of the CLK signal and delay the CLK signal according to the number of delay time blocks.

[0107] Next, combine Figure 3 , the process of delaying the CLK signal is further illustrated by examples.

[0108] Figure 3 This is another timing diagram of the controller output signal provided in the embodiment of the present application. Figure 3 , Figure 3 It may include a clock signal corresponding to CLK and a signal corresponding to CMD or DAT[7:0].

[0109] In the initial state, it is assumed that the clock signal has 2 delay time blocks. After link training, it is determined that if the sampling bit is located at the optimal position in the valid window, 3 more delay time blocks need to be added.

[0110] After delaying the clock signal, the sampled bit is located at the optimal position within the valid window.

[0111] In actual work, the chip where the controller is located may be unstable in timing due to external factors such as voltage and temperature, resulting in signal offset. When the offset is within a reasonable range, the data transmission between the two parties is not affected.

[0112] Next, combine Figure 4 , giving examples of timing instability caused by external factors such as voltage and temperature.

[0113] Figure 4A timing diagram of another controller output signal provided in an embodiment of the present application. Figure 4 , Figure 4 It may include a clock signal corresponding to CLK and a signal corresponding to CMD or DAT[7:0].

[0114] Under normal conditions, assuming that three delay time blocks are added, the sampling bit is located at the optimal position within the effective window.

[0115] If the chip where the controller is located is affected by external factors such as voltage and temperature, the delay time block generated by the delay device becomes smaller, causing the sampling point to drift to the edge area again.

[0116] In the above data transmission process, when the influence of external factors is large, the signal offset exceeds a reasonable range, resulting in low stability of data transmission.

[0117] In order to solve the above technical problems, the embodiment of the present application provides a data transmission method, by determining a target ratio, the target ratio is used to represent the ratio of the number of first time blocks to be delayed by the preset clock signal to the number of initial cycle time blocks, and sending a data signal according to the target ratio. In this way, the communication parties maintain a fixed ratio for transmission to ensure that both parties can correctly sample valid data, thereby improving the stability of data transmission.

[0118] The technical solution shown in the present application is described in detail below through specific embodiments. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or similar contents will not be described repeatedly in different embodiments.

[0119] Figure 5 This is a flow chart of a data transmission method provided by an embodiment of the present application. The execution subject of the embodiment of the present application may be a controller. Figure 5 , the method comprising:

[0120] S501: Determine the number of initial cycle time blocks corresponding to a preset clock signal.

[0121] The preset clock signal may be a clock signal corresponding to CLK.

[0122] The number of initial cycle time blocks may be used to indicate the number of delay time blocks corresponding to one cycle of the clock signal in the initial state.

[0123] Optionally, the number of initial cycle time blocks corresponding to the preset clock signal may be determined according to the cycle delay tracking module.

[0124] Optionally, the number of initial periodic time blocks corresponding to the preset clock signal may be determined according to a time block number prediction model.

[0125] It should be noted that the number of initial cycle time blocks corresponding to the preset clock signal can be determined according to any feasible implementation method, and the embodiments of the present application are not limited to this.

[0126] S502: Determine a target proportion according to a preset clock signal.

[0127] The target ratio is used to indicate the ratio of the number of first time blocks to be delayed of the preset clock signal to the number of initial cycle time blocks.

[0128] The first time block number may be the time block number corresponding to the sampling point of the preset clock signal and the effective time. The effective time may be the best sampled time in the effective window of the signal corresponding to CMD or DAT[7:0].

[0129] Optionally, the number of first time blocks for which the preset clock signal is to be delayed may be determined according to the preset clock signal, and the target proportion may be determined according to the number of initial cycle time blocks and the number of first time blocks.

[0130] Optionally, determine the type of device that sends the data signal; determine the number of first time blocks based on a preset clock signal and the device type; and determine the ratio of the first time block number to the initial cycle time block number as the target ratio.

[0131] Optionally, a preset clock signal may be input into a target proportion prediction model to determine the target proportion.

[0132] It should be noted that the target proportion can be determined according to any feasible implementation method and based on a preset clock signal, and the embodiments of the present application are not limited to this.

[0133] S503: Send a data signal according to the target proportion.

[0134] The data signal can be a signal corresponding to CMD or DAT[7:0].

[0135] Optionally, a delay model may be set according to a target ratio, and according to the delay model, a preset clock signal may be delayed to obtain a target clock signal, and the target clock signal and a data signal may be sent simultaneously.

[0136] The delay model can be used to determine the delay parameter. The delay parameter can be used to delay the preset clock signal.

[0137] Optionally, the target number of time blocks may be determined according to the target proportion, and the preset clock signal may be delayed according to the target number of time blocks to obtain the target clock signal, and the target clock signal and the data signal may be sent simultaneously.

[0138] It should be noted that the data signal can be sent according to any feasible implementation method and according to the target proportion, and the embodiments of the present application are not limited to this.

[0139] The data transmission method provided in this embodiment determines the number of initial cycle time blocks corresponding to the preset clock signal, determines the target ratio according to the preset clock signal, and the target ratio is used to represent the ratio of the number of first time blocks to be delayed by the preset clock signal to the number of initial cycle time blocks, and sends the data signal according to the target ratio. In this way, the communication parties maintain a fixed ratio for transmission to ensure that both parties can correctly sample valid data, thereby improving the stability of data transmission.

[0140] Next, combine Figure 6 , the process (S503) of sending a data signal according to the target proportion is explained.

[0141] Figure 6 A flowchart of another data transmission method provided by an embodiment of the present application. Based on the above embodiment, see Figure 6 , the method comprising:

[0142] S601: Determine the number of current cycle time blocks corresponding to a preset clock signal.

[0143] The preset clock signal may be affected by external factors such as voltage and temperature, and there may be different numbers of cycle time blocks.

[0144] The current cycle time block quantity may be used to indicate the number of delay time blocks corresponding to one cycle of the clock signal in the current state.

[0145] Optionally, the number of current cycle time blocks corresponding to the preset clock signal may be determined according to the cycle delay tracking module.

[0146] Optionally, the number of time blocks of the current cycle corresponding to the preset clock signal may be determined according to a time block number prediction model.

[0147] It should be noted that the number of current cycle time blocks corresponding to the preset clock signal can be determined according to any feasible implementation method, and the embodiments of the present application are not limited to this.

[0148] S602: Determine the target number of time blocks according to the target proportion and the number of time blocks in the current cycle.

[0149] The target time block number may be the time block number required for delaying the preset clock signal.

[0150] The target time block number can be determined by multiplying the target ratio by the number of time blocks in the current cycle.

[0151] S603: Delay the preset clock signal according to the target time block quantity to obtain a target clock signal.

[0152] For example, assuming that the target time block number is 5, the preset clock signal is delayed by 5 time blocks to obtain the target clock signal.

[0153] For example, assuming that the target time block number is 10, the preset clock signal is delayed by 10 time blocks to obtain the target clock signal.

[0154] S604: Send a target clock signal and a data signal simultaneously.

[0155] If the controller is a master controller, a target clock signal and a data signal may be sent to the slave controller simultaneously through the master controller.

[0156] If the controller is a slave controller, the target clock signal and the data signal can be sent to the master controller simultaneously through the slave controller.

[0157] Next, combine Figure 7 and Figure 8 , the above-mentioned process of S601-S604 is illustrated by examples.

[0158] Figure 7 This is another timing diagram of the controller output signal provided in the embodiment of the present application. Figure 7 , Figure 7 It may include a clock signal corresponding to CLK and a signal corresponding to DAT.

[0159] Assuming that the target ratio is 1 / 4, it is determined that the number of current cycle time blocks corresponding to the preset clock signal is 20.

[0160] The target number of time blocks is determined to be 5, a preset clock signal is delayed to obtain a target clock signal, and the target clock signal and a data signal are sent simultaneously.

[0161] Figure 8 A timing diagram of another controller output signal provided in an embodiment of the present application. Figure 8 , Figure 8 It may include a clock signal corresponding to CLK and a signal corresponding to DAT.

[0162] Assuming that the target ratio is 1 / 4, it is determined that the number of current cycle time blocks corresponding to the preset clock signal is 40.

[0163] It is determined that the number of target time blocks is 10, a preset clock signal is delayed to obtain a target clock signal, and the target clock signal and a data signal are sent simultaneously.

[0164] The implementation content of each step in the embodiment of the present application can refer to the description of the corresponding steps or operations in the above method embodiment, and repeated content will not be repeated.

[0165] The data transmission method provided in this embodiment determines the number of current cycle time blocks corresponding to the preset clock signal, determines the target time block number according to the target ratio and the current cycle time block number, delays the preset clock signal according to the target time block number to obtain the target clock signal, and sends the target clock signal and the data signal at the same time. In this way, the communication parties maintain a fixed ratio for transmission to ensure that both parties can correctly sample valid data, thereby improving the stability of data transmission.

[0166] Next, combine Fig. 9 , the process (S502) of determining the target proportion according to the preset clock signal is explained.

[0167] Fig. 9 A flowchart of another data transmission method provided in an embodiment of the present application. Based on the above embodiment, see Fig. 9 , the method comprising:

[0168] S901. Determine the type of device that sends a data signal.

[0169] If the device type is a host type, execute S902;

[0170] If the device type is a slave type, execute S906.

[0171] The device information can be obtained, and the type of the device sending the data signal can be determined based on the device information.

[0172] The device type may include a master type and a slave type.

[0173] For example, mobile phones, tablet computers, laptops, etc. can be host types, and WiFi modules, GPS receivers, TV cards, etc. can be slave types.

[0174] S902: Determine a sampling time corresponding to a preset clock signal.

[0175] The sampling time may be the time at which data sampling is performed.

[0176] A preset voltage value may be obtained, and a sampling time corresponding to the preset clock signal may be determined according to a rising edge of the preset clock signal and the preset voltage value.

[0177] S903: Determine a transmission time period corresponding to the data signal through link training.

[0178] The transmission time period may be a time period corresponding to the valid window.

[0179] Optionally, multiple test signals may be sent to obtain response signals respectively corresponding to the multiple test signals, and the transmission time period corresponding to the data signal may be determined according to the multiple response signals.

[0180] Optionally, the transmission time period corresponding to the data signal can be determined through link training in the following manner: obtain multiple sampling information through the host device; determine whether there are multiple sampling information with similarities less than a threshold among the multiple sampling information; if so, determine the sampling moments corresponding to the multiple sampling information with similarities less than the threshold, and determine the time period in which the multiple sampling moments are located as the transmission time period corresponding to the data signal.

[0181] The sampling information may be an analysis result of a receiving end corresponding to the host device.

[0182] The similarity may be determined by the bit error rate or by the degree of similarity, which is not limited here.

[0183] The time period in which the multiple sampling moments are located can be obtained by continuously processing the multiple sampling moments to obtain a target time period.

[0184] Optionally, multiple sampling information can be obtained through the host device in the following manner: the host device sends the i-th request information to the slave device, obtains the i-th response information sent by the slave device, determines the (i+1)-th request information based on the i-th response information, repeats the above steps until a preset number of response information is determined, and determines the preset number of response information as sampling information.

[0185] Optionally, multiple sampling information can be obtained through the host device in the following manner: the host device sends the i-th request information to the slave device; the host device determines the i-th sampling moment, the i-th sampling moment is the sampling moment corresponding to the delay of the preset clock signal by i time blocks; the host device samples the i-th response information sent by the slave device at the i-th sampling moment to obtain the i-th sampling information; wherein i is 1, ..., n in sequence, and n is the number of initial cycle time blocks.

[0186] It should be noted that multiple sampling information can be obtained through the host device according to any feasible implementation method, and the embodiments of the present application are not limited to this.

[0187] S904: Determine the effective time corresponding to the transmission time period.

[0188] The effective time can be determined according to the transmission parameters.

[0189] The effective time can be used to indicate the best time to sample the data signal to ensure the stability of data transmission.

[0190] S905: Determine the number of time blocks between the clock time block corresponding to the sampling time and the central time block corresponding to the effective time as the first number of time blocks.

[0191] After S905 , S908 is executed.

[0192] It can be determined whether there is a delay in the preset clock signal. If so, determine the initial number of time blocks corresponding to the delay of the preset clock signal, subtract the initial number of time blocks from the clock time block corresponding to the sampling moment to obtain a second time block, and determine the number of time blocks between the second time block and the central time block corresponding to the effective moment as the first number of time blocks; if not, determine the number of time blocks between the clock time block corresponding to the sampling moment and the central time block corresponding to the effective moment as the first number of time blocks.

[0193] When it is determined that there is no delay in the preset clock signal, the number of time blocks between the clock time block corresponding to the sampling time and the center time block corresponding to the effective time may be determined as the first number of time blocks.

[0194] S906: Obtain a delay parameter in the transmission protocol.

[0195] Delay parameters may include clock frequency, setup and hold time, data transfer rate, etc.

[0196] The delay parameter may be determined according to the transmission protocol, the host device information, and the slave device information.

[0197] S907: Determine the number of first time blocks according to the delay parameter and the preset clock signal.

[0198] The delay duration may be determined according to the delay parameter and the preset clock signal, and the number of first time blocks may be determined according to the delay duration.

[0199] S908: Determine the ratio of the first time block number to the initial period time block number as the target ratio.

[0200] For example, assuming that the number of first time blocks is 5, the number of initial cycle time blocks is 20, and the target proportion is determined to be 1 / 4.

[0201] The implementation content of each step in the embodiment of the present application can refer to the description of the corresponding steps or operations in the above method embodiment, and repeated content will not be repeated.

[0202] The data transmission method provided in this embodiment determines the type of device that sends the data signal. If the device type is a host type, the sampling time corresponding to the preset clock signal is determined, the transmission time period corresponding to the data signal is determined through link training, the effective time corresponding to the transmission time period is determined, and the number of time blocks between the clock time block corresponding to the sampling time and the central time block corresponding to the effective time is determined as the first time block number. If the device type is a slave type, the delay parameter in the transmission protocol is obtained, and the first time block number is determined according to the delay parameter and the preset clock signal, and the ratio of the first time block number to the initial cycle time block number is determined as the target ratio. In this way, the communication parties maintain a fixed ratio for transmission to ensure that both parties can correctly sample valid data, thereby improving the stability of data transmission.

[0203] Fig.10 This is a structural diagram of a data transmission device provided in an embodiment of the present application. Fig.10 The device 1000 includes a first determination module 1001, a second determination module 1002 and a transmission module 1003, wherein:

[0204] A first determining module 1001 is used to determine the number of initial cycle time blocks corresponding to a preset clock signal;

[0205] A second determination module 1002 is used to determine a target ratio according to the preset clock signal, where the target ratio is used to represent the ratio of the number of first time blocks to be delayed of the preset clock signal to the number of time blocks of the initial cycle;

[0206] The transmission module 1003 is used to send a data signal according to the target proportion.

[0207] In a possible implementation manner, the second determining module 1002 is specifically configured to:

[0208] Determine the type of device that sends the data signal, where the device type includes a host type and a slave type;

[0209] Determining the first time block quantity according to the preset clock signal and the device type;

[0210] The ratio of the first time block number to the initial cycle time block number is determined as the target ratio.

[0211] In a possible implementation manner, the device type is a host type, and the second determining module 1002 is specifically configured to:

[0212] Determine a sampling time corresponding to the preset clock signal;

[0213] Determining a transmission time period corresponding to the data signal through link training;

[0214] Determine the effective time corresponding to the transmission time period;

[0215] The number of time blocks between the clock time block corresponding to the sampling time and the central time block corresponding to the effective time is determined as the first number of time blocks.

[0216] In a possible implementation manner, the second determining module 1002 is specifically configured to:

[0217] Acquire multiple sampling information through a host device;

[0218] Determine whether there are multiple sampling information with similarities less than a threshold value among the multiple sampling information;

[0219] If so, the sampling moments corresponding to the plurality of sampling information whose similarities are less than the threshold are determined, and the time periods in which the plurality of sampling moments are located are determined as the transmission time period corresponding to the data signal.

[0220] In a possible implementation manner, the second determining module 1002 is specifically configured to:

[0221] Sending an i-th request information to the slave device through the host device;

[0222] Determine, by the host device, an i-th sampling time, wherein the i-th sampling time is a sampling time corresponding to delaying the preset clock signal by i time blocks;

[0223] Sampling, by the host device, the i-th response information sent by the slave device at the i-th sampling time to obtain i-th sampling information;

[0224] Herein, the i is 1, ..., n in sequence, and n is the number of the initial periodic time blocks.

[0225] In a possible implementation manner, the device type is a slave type, and the second determining module 1002 is specifically configured to:

[0226] Get the delay parameters in the transport protocol;

[0227] The first time block quantity is determined according to the delay parameter and the preset clock signal.

[0228] In a possible implementation manner, the transmission module 1003 is specifically configured to:

[0229] Determine the number of current cycle time blocks corresponding to the preset clock signal;

[0230] Determine the target number of time blocks according to the target proportion and the number of time blocks in the current cycle;

[0231] According to the target time block number, delaying the preset clock signal to obtain a target clock signal;

[0232] The target clock signal and the data signal are sent simultaneously.

[0233] Fig.11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Fig.11 , the electronic device 1100 may include: a memory 1101 , a processor 1102 , and a transceiver 1103 .

[0234] The memory 1101 is used to store program instructions;

[0235] The processor 1102 is used to execute the program instructions stored in the memory, so as to enable the electronic device 1100 to execute any of the above-mentioned data transmission methods.

[0236] The transceiver 1103 may include: a transmitter and / or a receiver. The transmitter may also be referred to as a transmitter, a transmitter, a transmission port, a transmission interface, or similar descriptions, and the receiver may also be referred to as a receiver, a reception port, a reception interface, or similar descriptions. Exemplarily, the memory 1101, the processor 1102, and the transceiver 1103 are interconnected via a bus 1104.

[0237] The present application also provides a chip having a computer program stored thereon. When the computer program is executed by the chip, the above-mentioned data transmission method is implemented. The corresponding content and effects can be referred to in the method embodiment part, which will not be described in detail.

[0238] The present application also provides a chip module, on which a computer program is stored. When the computer program is executed by the chip module, the above-mentioned data transmission method is implemented. The corresponding content and effects can be referred to the method embodiment part, which will not be described in detail.

[0239] The embodiment of the present application also provides a computer program product, which can be executed by a processor. When the computer program product is executed, the above-mentioned data transmission method can be implemented.

[0240] The data transmission device, electronic device, computer-readable storage medium and computer program product of the embodiments of the present application can execute the technical solutions shown in the above-mentioned data transmission method embodiments. Their implementation principles and beneficial effects are similar and will not be repeated here.

[0241] All or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned memory (storage medium) includes: read-only memory (ROM), random access memory (RAM), flash memory, hard disk, solid state drive, magnetic tape, floppy disk, optical disc and any combination thereof.

[0242] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer-executable instructions. These computer-executable instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0243] These computer executable instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0244] These computer executable instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0245] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data transmission method, characterized in that: include: Determine the number of initial cycle time blocks corresponding to the preset clock signal; Determine a target ratio according to the preset clock signal, where the target ratio is used to represent the ratio of the number of first time blocks to be delayed by the preset clock signal to the number of time blocks of the initial cycle; A data signal is sent according to the target proportion.

2. The method according to claim 1, characterized in that Determining a target proportion according to the preset clock signal includes: Determine the type of device that sends the data signal, where the device type includes a host type and a slave type; Determining the first time block quantity according to the preset clock signal and the device type; The ratio of the first time block number to the initial cycle time block number is determined as the target ratio.

3. The method according to claim 2, characterized in that The device type is a host type, and determining the first time block quantity according to the preset clock signal and the device type includes: Determine a sampling time corresponding to the preset clock signal; Determining a transmission time period corresponding to the data signal through link training; Determine the effective time corresponding to the transmission time period; The number of time blocks between the clock time block corresponding to the sampling time and the central time block corresponding to the effective time is determined as the first number of time blocks.

4. The method according to claim 3, characterized in that Determining a transmission time period corresponding to the data signal through link training includes: Acquire multiple sampling information through a host device; Determine whether there are multiple sampling information with similarities less than a threshold value among the multiple sampling information; If so, the sampling moments corresponding to the plurality of sampling information with similarities less than the threshold are determined, and the time periods in which the plurality of sampling moments are located are determined as the transmission time period corresponding to the data signal.

5. The method according to claim 4, characterized in that Obtain multiple sampling information through the host device, including: Sending an i-th request information to the slave device through the host device; Determine, by the host device, an i-th sampling time, wherein the i-th sampling time is a sampling time corresponding to delaying the preset clock signal by i time blocks; Sampling, by the host device, the i-th response information sent by the slave device at the i-th sampling time to obtain i-th sampling information; Herein, the i is 1, ..., n in sequence, and n is the number of the initial periodic time blocks.

6. The method according to claim 2, characterized in that The device type is a slave type, and determining the first time block quantity according to the preset clock signal and the device type includes: Get the delay parameters in the transport protocol; The first time block quantity is determined according to the delay parameter and the preset clock signal.

7. The method according to any one of claims 1 to 6, characterized in that: According to the target proportion, a data signal is sent, including: Determine the number of current cycle time blocks corresponding to the preset clock signal; Determine the target number of time blocks according to the target proportion and the number of time blocks in the current cycle; According to the target time block number, delaying the preset clock signal to obtain a target clock signal; The target clock signal and the data signal are sent simultaneously.

8. A data transmission device, characterized in that: The device comprises: A first determining module, used to determine the number of initial cycle time blocks corresponding to a preset clock signal; A second determination module is used to determine a target ratio according to the preset clock signal, where the target ratio is used to represent the ratio of the number of first time blocks to be delayed of the preset clock signal to the number of initial cycle time blocks; The transmission module is used to send a data signal according to the target proportion.

9. An electronic device, characterized in that: include: memory, processors, and transceivers; Wherein, the memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 7 when executed by a processor.

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