Display panel, driving chip and display device

Abstract

The invention discloses a display panel, a driving chip and a display device. The display panel comprises a gate drive circuit, the gate drive circuit comprises a plurality of cascaded shift registers, each shift register comprises a first transistor, and the first transistor is connected to a power supply voltage through a resistor structure. According to the embodiment of the invention, the problem that the transistor is easy to damage can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a driving chip and a display device. Background Art

[0002] The display panel generally includes pixels and a gate driving circuit. The gate driving circuit is used to provide a gate control signal to the pixel to control the pixel to write a data signal, etc.

[0003] With the development of display technology, the requirements for the reliability of display panels are increasing. If the transistors in the gate drive circuit are easily damaged, it will affect the normal operation of the gate drive circuit and further affect the reliability of the display panel. Summary of the invention

[0004] The embodiments of the present application provide a display panel, a driver chip and a display device, which can improve the problem that transistors are easily damaged.

[0005] In a first aspect, an embodiment of the present application provides a display panel, including: a gate driving circuit, the gate driving circuit includes a plurality of cascaded shift registers, the shift register includes a first transistor, and the first transistor is connected to a power supply voltage through a resistance structure.

[0006] Based on the same inventive concept, in the second aspect, an embodiment of the present application provides a driving chip for providing a power supply voltage to a gate driving circuit in a display panel, the power supply voltage provided by the driving chip is a first level in the first stage, a second level in the second stage, and a third level in the third stage, the third stage is between the first stage and the second stage, the third level is between the first level and the second level, and at the first level, the first transistor in the gate driving circuit is turned on.

[0007] Based on the same inventive concept, in the third aspect, an embodiment of the present application provides a driving chip, including: a signal generating circuit and a signal delay structure, the signal generating circuit is used to generate a power supply voltage, one end of the signal delay structure is electrically connected to the output end of the signal generating circuit, and the other end of the signal delay structure is used to electrically connect to the gate driving circuit in the display panel.

[0008] Based on the same inventive concept, in a fourth aspect, an embodiment of the present application provides a display device, comprising: a display panel as described in the embodiment of the first aspect, and / or a driving chip as described in the embodiment of the second aspect or the third aspect.

[0009] When the power supply voltage changes, an instantaneous current I will be generated on the transmission path of the power supply voltage. For example, when the power supply voltage changes from a low potential vgl to a high potential vgh, an instantaneous current I will be generated on the transmission path of the power supply voltage. If the first transistor is directly connected to the power supply voltage without passing through a resistor structure, the first transistor receives the high potential vgh, the source-drain voltage difference Vds of the first transistor is large, and the current passing through the first transistor is large, which can easily damage the first transistor. In the embodiment of the present application, the first transistor is connected to the power supply voltage through the resistance structure 30. When the power supply voltage changes from a low potential vgl to a high potential vgh, the instantaneous current generated on the transmission path of the power supply voltage will generate a voltage drop ΔV on the resistance structure. The resistance of the resistance structure 30 is denoted as R, ΔV=I*R, and the potential received by the first transistor is reduced to vgh-ΔV, and the current passing through the first transistor is reduced accordingly. In this way, the large current impact on the first transistor due to the instantaneous change of the connected power supply voltage can be reduced. In other words, the voltage change of the power supply voltage is avoided from directly impacting the first transistor, so that the instantaneous current passing through the first transistor decreases, thereby improving the problem of easy damage to the first transistor and improving the reliability of the gate drive circuit and the display panel.

[0010] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0012] Figure 1 A schematic diagram of a top view structure of a display panel provided in an embodiment of the present application is shown;

[0013] Figure 2 Another schematic diagram of a top view structure of a display panel provided in an embodiment of the present application is shown;

[0014] Figure 3 A schematic diagram showing a circuit structure of a shift register in a display panel provided in an embodiment of the present application is shown;

[0015] Figure 4 Show Figure 3 A corresponding timing diagram;

[0016] Figure 5 A schematic diagram showing a circuit structure of a shift register in a display panel provided in an embodiment of the present application is shown;

[0017] Figure 6 Another circuit structure schematic diagram of a shift register in a display panel provided by an embodiment of the present application is shown;

[0018] Figure 7 A schematic diagram showing another circuit structure of a shift register in a display panel provided in an embodiment of the present application is shown;

[0019] Figure 8 Some structural schematic diagrams showing the resistor structure in the display panel provided by the embodiments of the present application;

[0020] Fig. 9 A schematic diagram showing a structure of wiring in a display panel provided in an embodiment of the present application;

[0021] Fig.10 Another schematic diagram showing the structure of wiring in a display panel provided in an embodiment of the present application;

[0022] Fig.11 A schematic diagram showing a cross-sectional structure of a display panel provided in an embodiment of the present application is shown;

[0023] Fig.12 Another schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present application is shown;

[0024] Fig.13 A schematic diagram showing another cross-sectional structure of a display panel provided in an embodiment of the present application is shown;

[0025] Fig.14 A schematic diagram showing another cross-sectional structure of a display panel provided in an embodiment of the present application is shown;

[0026] Fig.15 A schematic diagram showing another cross-sectional structure of a display panel provided in an embodiment of the present application is shown;

[0027] Fig.16 Another structural schematic diagram showing wiring in a display panel provided in an embodiment of the present application is shown;

[0028] Fig.17 Another structural schematic diagram showing wiring in a display panel provided in an embodiment of the present application is shown;

[0029] Fig.18 A schematic diagram showing a connection of wiring and circuits in a display panel provided by an embodiment of the present application;

[0030] Fig.19 Another connection schematic diagram of wiring and circuits in a display panel provided by an embodiment of the present application is shown;

[0031] Fig. 20Another schematic diagram showing the connection of wiring and circuits in a display panel provided by an embodiment of the present application;

[0032] Fig.21 A schematic diagram showing a connection between a resistor structure and a first transistor in a display panel provided by an embodiment of the present application is shown;

[0033] Fig. 22 Another connection diagram of the resistance structure and the first transistor in the display panel provided by the embodiment of the present application is shown;

[0034] Fig.23 A timing diagram showing a power supply voltage provided in an embodiment of the present application;

[0035] Fig.24 A timing diagram showing a power supply voltage output by a driver chip provided in an embodiment of the present application;

[0036] Fig.25 Another timing diagram showing the power supply voltage output by the driver chip provided in an embodiment of the present application;

[0037] Fig.26 Another timing diagram showing the power supply voltage output by the driver chip provided in the embodiment of the present application;

[0038] Fig. 27 Another timing diagram showing the power supply voltage output by the driver chip provided in the embodiment of the present application;

[0039] Fig.28 A schematic diagram showing the structure of a driver chip provided in an embodiment of the present application is shown;

[0040] Fig.29 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0041] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0042] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0043] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0044] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0045] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0046] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0047] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the relevant technical issues:

[0048] The inventors of the present application have found that, especially when the display panel is in a high-temperature operating environment, transistor devices with high bias voltage in the gate drive circuit and that are turned on for a long time are easily damaged.

[0049] For transistors that need to be connected to the power supply voltage (VDD signal), when the VDD signal changes from the cut-off level to the on-level (here, the cut-off level refers to the level that controls the transistor to be cut off, and the on-level refers to the level that controls the transistor to be turned on), the transistor controlled by the VDD signal will be directly impacted by the high level and large current. If the transistor is turned on for a long time, the transistor is easily damaged. When the transistor is damaged, it cannot control the corresponding node in the gate drive circuit, so that the gate drive circuit loses its corresponding function, resulting in abnormal operation of the gate drive circuit, and then causing abnormal display of the display panel (such as horizontal stripes on the display).

[0050] In view of the above research findings of the inventors, the embodiments of the present application consider changing the power supply voltage actually received by the transistor, so as to prevent the transistor from actually receiving an instantaneous excessively high potential and being impacted by an instantaneous large current when the power supply voltage undergoes a potential conversion, thereby reducing the instantaneous current passing through the transistor, thereby improving the problem of easy damage to the transistor and improving the reliability of the gate drive circuit and the display panel.

[0051] The display panel, the driving chip and the display device provided in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0052] like Figure 1 or Figure 2 As shown, the display panel 100 provided in the embodiment of the present application includes a gate driving circuit 10, and the gate driving circuit 10 includes a plurality of cascaded shift registers 11. In the figure, the output signal of the previous stage shift register 11 is used as a trigger signal of the next stage shift register 11 as an example, but the cascade relationship between the shift registers 11 is not limited thereto, and the output signal of the current stage shift register can be used as a trigger signal of the shift registers after several stages.

[0053] Exemplarily, the display panel 100 includes a display area AA and a non-display area NA surrounding the display area AA. The gate driving circuit 10 is located in the non-display area NA. The display area AA includes a plurality of pixels 20. The output end of the shift register 11 is electrically connected to the pixel 20, and the signal output by the shift register 11 is used to drive the pixel 20.

[0054] The signal output by the shift register 11 may include a scan signal, a light emitting control signal, and the like.

[0055] When the display panel is a liquid crystal display panel, the pixel 20 may include a switch tube, and the signal output by the shift register 11 controls the switch tube to be turned on, so that the data line provides a data voltage to the pixel electrode through the switch tube.

[0056] The shift register 11 includes a first transistor 111, and the first transistor 111 is connected to a power supply voltage VDD through a resistor structure 30. The power supply voltage VDD is provided by a driving circuit, such as a driving chip 200. It is understandable that the power supply voltage VDD passes through the resistor structure 30 on the path from the output end of the driving chip 200 to the first transistor 111.

[0057] Exemplarily, the gate of the first transistor 111 is connected to the power supply voltage VDD through the resistor structure 30. The power supply voltage VDD is used to control the state of the first transistor 111. For example, when the power supply voltage VDD is at a first level, the first transistor 111 is turned on; when the power supply voltage VDD is at a second level, the first transistor 111 is turned off. When the first transistor 111 is an N-type transistor, the second level is lower than the first level, the first level is a high level vgh, and the second level is a low level vgl. Correspondingly, when the first transistor is a P-type transistor, the first level is a low level vgl, and the second level is a high level vgh.

[0058] Exemplarily, the display panel 100 further includes a power line 41 for transmitting a power voltage VDD. The driver chip 200 is used to provide the power voltage VDD. The power voltage VDD output by the driver chip 200 is transmitted to the first transistor 111 through the power line 41 and the resistor structure 30 .

[0059] As an example, Figure 1 As shown, the resistor structure 30 is connected between the shift register 11 and the power line 41. In this case, the power supply voltage VDD output by the driver chip 200 is first transmitted to the power line 41, then transmitted to the resistor structure 30, and then transmitted to the first transistor 111.

[0060] As another example, Figure 2 As shown, the resistor structure 30 is connected between the driver chip 200 and the power supply line 41. In this case, the power supply voltage VDD output by the driver chip 200 is first transmitted to the resistor structure 30, then to the power supply line 41, and then to the first transistor 111.

[0061] The following is an exemplary introduction to some structures of shift registers.

[0062] Exemplarily, the circuit architecture of the shift register 11 includes but is not limited to Figure 3 The circuit architecture is shown in Figure 1. Figure 3As shown, the circuit architecture of the shift register 11 may include a pull-up control module 1, a pull-up module 2, a main pull-down module 3, a pull-down maintenance module 4, and a bootstrap capacitor 5. Among them, the pull-up control module 1 is used to pre-charge and open the shift register, the pull-up module 2 is used to drive the pixels in the display area, the main pull-down module 3 is used to pull down the node Gn and the node netA, the pull-down maintenance module 4 is used to maintain the PD point potential stable, and the bootstrap capacitor 5 is used to raise the node netA potential. Here, the node netA and the PU point can be understood as nodes with the same potential.

[0063] Exemplarily, the shift register 11 may be designed to include other functional modules 6 according to other requirements.

[0064] like Figure 4 As shown, the working process of the shift register 11 can generally be divided into four stages.

[0065] In stage ①, the pull-up control module 1 controls the trigger signal STV to enter, the PU point is raised for the first time, and the PD point is pulled down;

[0066] In stage ②, the bootstrap capacitor 5 takes effect and the PU point is lifted for the second time;

[0067] In stage ③, the main pull-down module 3 works, the reset signal RESET enters, pulls down the PU point, and the PD point starts to rise;

[0068] In stage ④, the pull-down holding module 4 works, the PD point maintains a high potential, and the circuit charge is continuously cleared until the next time the PU point rises and pulls it down.

[0069] The power supply voltage VDD is used to provide the potential of the PD point. The change frequency of the power supply voltage VDD may not be high. For example, when the transistor controlled by the power supply voltage VDD is an N-type transistor, the power supply voltage VDD can maintain a high potential for a long time.

[0070] In some optional examples, the specific circuit structure of the shift register 11 can be as follows: Figure 5 As shown, the transistor M16 and the transistor M17 need to be connected to the power supply voltage VDD. For the sake of distinction, the transistor M16 is connected to the first power supply voltage VDD1, and the transistor M17 is connected to the second power supply voltage VDD2. Here, the first transistor 111 includes the transistor M16 and the transistor M17. The transistor M16 and the transistor M17 can be connected to the first power supply voltage VDD1 and the second power supply voltage VDD2 respectively through different resistor structures 30.

[0071] In some other optional examples, the specific circuit structure of the shift register 11 can be as follows: Figure 6As shown, the transistor T4 needs to be connected to the power supply voltage VDD. Here, the first transistor 111 includes the transistor T4, and the transistor T4 is connected to the power supply voltage VDD through the resistance structure 30.

[0072] In some other optional examples, the specific circuit structure of the shift register 11 can be as follows: Figure 7 As shown, the transistor M05 needs to be connected to the power supply voltage VDD. Here, the first transistor 111 includes the transistor M05, and the transistor M05 is connected to the power supply voltage VDD through the resistor structure 30.

[0073] It should be noted that the technical concept of the present application has general applicability and does not require a specific structure of the shift register. Figures 3 to 7 The structures and timings shown are only examples and are not intended to limit the present application. Figures 5 to 7 The circuit structures of the illustrated shift registers are 19T1C, 11T1C, and 9T1C, respectively. The structures of the shift registers include but are not limited to 19T1C, 11T1C, 9T1C, 9T2C, 12T1C, 17T1C, 21T1C, etc. Here, "19T1C" means that the shift register has 19 transistors and 1 capacitor. The same is true for the others, and they are not explained one by one.

[0074] When the power supply voltage changes, an instantaneous current I will be generated on the transmission path of the power supply voltage. For example, when the power supply voltage changes from a low potential vgl to a high potential vgh, an instantaneous current I will be generated on the transmission path of the power supply voltage. If the first transistor is directly connected to the power supply voltage without passing through a resistor structure, the first transistor receives the high potential vgh, the source-drain voltage difference Vds of the first transistor is large, and the current passing through the first transistor is large, which can easily damage the first transistor. In the embodiment of the present application, the first transistor is connected to the power supply voltage VDD through the resistance structure 30. When the power supply voltage VDD changes from a low potential vgl to a high potential vgh, the instantaneous current generated on the transmission path of the power supply voltage VDD will generate a voltage drop ΔV on the resistance structure. The resistance of the resistance structure 30 is denoted as R, ΔV=I*R, and the potential received by the first transistor is reduced to vgh-ΔV, and the current passing through the first transistor is reduced accordingly. In this way, the large current impact on the first transistor due to the instantaneous change of the connected power supply voltage VDD can be reduced. In other words, the voltage change of the power supply voltage VDD is avoided from directly impacting the first transistor, so that the instantaneous current passing through the first transistor decreases, thereby improving the problem of easy damage to the first transistor and improving the reliability of the gate drive circuit and the display panel.

[0075] It is understandable that only when the power supply voltage VDD changes, an instantaneous current will be generated on the transmission path of the power supply voltage VDD. Therefore, the resistance structure 30 only plays a role in reducing the voltage when the power supply voltage VDD changes. When the power supply voltage VDD no longer changes, almost no current passes through the transmission path of the power supply voltage VDD, and the resistance structure will no longer play a role in reducing the voltage. Therefore, the resistance structure is equivalent to adding a delay when the signal changes sharply, playing a buffering effect, and will not affect the normal working potential of the device, so it will not affect the normal working of the shift register.

[0076] For example, the first transistor is an N-type transistor. When the voltage difference Vgs between its gate and source is greater than its threshold voltage Vth, the first transistor is turned on and current flows through. When the power supply voltage VDD changes from a low potential vgl to a high potential vgh, the resistance structure has a delay effect. When the power supply voltage VDD changes from a high potential vgh to a low potential vgl, the N-type first transistor is turned off and no current flows through.

[0077] For another example, the first transistor is a P-type transistor. When the voltage difference Vgs between the gate and the source is less than the threshold voltage Vth, the first transistor is turned on and current flows through. When the power supply voltage VDD changes from a high potential vgh to a low potential vgl, the resistance structure has a delay effect. When the power supply voltage VDD changes from a low potential vgl to a high potential vgh, the P-type first transistor is turned off and no current flows through.

[0078] Some structural examples of resistor structures are introduced below.

[0079] In some embodiments, Figure 1 or Figure 2 As shown, the display panel includes a power supply line 41 for transmitting a power supply voltage VDD, and the resistor structure 30 includes a first line 301. The first line 301 can be connected between the power supply line 41 and the first transistor 111, or the first line 301 is connected to the first transistor 111 through the power supply line 41.

[0080] As an example, the impedance per unit length of at least part of the line segments of the first line 301 is greater than the impedance per unit length of the power line 41. Here, it can be designed that: the impedance of the first line 301 is uniform, that is, the impedance per unit length of the line segments at different positions of the first line 301 is the same. Alternatively, it can also be designed that: the impedance per unit length of a part of the line segments of the first line 301 is greater than the impedance per unit length of the power line 41, and the impedance per unit length of another part of the line segments of the first line 301 may not be required.

[0081] It is understandable that the first line 301 and the power line 41 are both used to transmit the power supply voltage VDD. Within the same length, the impedance of the first line 301 is greater than the impedance of the power line 41. Exemplarily, the total impedance of the first line 301 is greater than the total impedance of the power line 41.

[0082] In order to reduce the impact of signal voltage drop on display performance, the total impedance of the power supply line 41 is usually set to be relatively small, and even the total impedance of the power supply line 41 can be ignored. In the embodiment of the present application, the resistance structure includes a first line, that is, the resistance structure is designed as a line structure, so that the first line can be directly prepared using the existing line preparation process, which is relatively easy to implement; in addition, the impedance of the first line per unit length is relatively large, which is more conducive to reducing the impact on the first transistor when the power supply voltage VDD changes, thereby protecting the first transistor from damage.

[0083] In some embodiments, Figure 1 or Figure 2 As shown, the display panel includes a power supply line 41, and the power supply line 41 is used to transmit the power supply voltage VDD. The resistance structure 30 includes a first line 301. The line width of the first line 301 is smaller than the line width of the power supply line 41. Under the same material, the smaller the line width, the greater the impedance of the line. In the embodiment of the present application, by designing the line width of the first line to be relatively small, the impedance on the transmission path from the power supply voltage VDD to the first transistor can be increased, and the impact on the first transistor when the power supply voltage VDD changes can be reduced, thereby protecting the first transistor from being damaged.

[0084] In other embodiments, the transmission path for the power supply voltage VDD to be output from the driver chip 200 to the first transistor may be increased. For example, the length of the wiring at some positions on the transmission path (such as the position where the first wiring 301 is located) may be increased.

[0085] As an example, Figure 8 As shown, the resistance structure includes a first wiring 301, and the first wiring 301 includes a meander line. The first wiring is designed to extend in a meandering form, so that the total length of the first wiring can be increased within a limited space, thereby increasing the impedance on the transmission path from the power supply voltage VDD to the first transistor, reducing the impact on the first transistor when the power supply voltage VDD changes, and thus protecting the first transistor from being damaged.

[0086] In some examples, such as Figure 8 As shown, the bending form of the first wiring 301 may include but is not limited to any one of square wave, sawtooth, and serpentine.

[0087] As an example, when the total length of the transmission path from the power supply voltage VDD output from the driver chip 200 to the first transistor remains unchanged, only the wiring at some positions on the transmission path (such as the position where the first wiring 301 is located) is designed to reduce the line width.

[0088] As another example, the total length of the transmission path from the power supply voltage VDD to the first transistor may be increased (for example, the length of the first wiring may be increased) while the line width of the transmission path of the power supply voltage VDD remains unchanged.

[0089] As another example, not only the line width of some locations on the transmission path (such as the location of the first routing 301) can be reduced, but also the total length of the transmission path from the power supply voltage VDD to the first transistor can be increased (for example, the length of the first routing can be increased).

[0090] It is understandable that when the line width of the first line 301 is smaller than the line width of the power line 41, it can be achieved that: the impedance per unit length of the first line 301 is greater than the impedance per unit length of the power line 41. In other examples, different materials can be selected to prepare the first line 301 and the power line 41 respectively, and the impedance of the material used for the first line 301 is greater, so as to meet: the impedance per unit length of the first line 301 is greater than the impedance per unit length of the power line 41.

[0091] In some embodiments, Figure 1 or Figure 2 As shown, the display panel includes a power supply line 41, and the power supply line 41 is used to transmit the power supply voltage VDD. Fig. 9 The resistor structure 30 at least includes a first line segment 30 a , and the first line segment 30 a and the power line 41 are located in different film layers.

[0092] Fig. 9 Different fillings are used to indicate the lines located in different film layers. When the first line segment 30a and the power line 41 are located in different film layers, the two can be connected through a via h1. One end of the via h1 overlaps the power line 41, and the other end overlaps the first line segment 30a.

[0093] Since the first line segment 30a and the power line 41 are located in different film layers, the first line segment 30a is not constrained by the power line 41, and the design freedom of the structural characteristics and / or material characteristics of the first line segment 30a can be greater, facilitating a more flexible design of the first line segment 30a.

[0094] Exemplarily, the material of the first line segment 30 a includes a transparent conductive material or a semiconductor material.

[0095] As an example, the transparent conductive material includes indium tin oxide (ITO). The material of the power trace 41 generally includes a metal single substance or alloy such as copper, aluminum, molybdenum, titanium, etc., and the impedance of the metal single substance or alloy is relatively low. The impedance of ITO is much higher, and generally the impedance of ITO is 500 times or more than that of metals such as copper and aluminum.

[0096] The power supply line 41 is a conductor. When the first line segment 30a includes a semiconductor material, the first line segment 30a is a semiconductor. Compared with the conductor, the resistance of the semiconductor is greater, and the conductivity of the semiconductor is lower than that of the conductor.

[0097] As an example, the semiconductor material included in the first line segment 30a can be the same as the semiconductor material included in the transistor in the gate drive circuit. For example, the first line segment 30a includes doped A-Si. Here, the first line segment 30a can refer to a semiconductor trace that has been doped and made conductive. It is understandable that the doped semiconductor trace does not directly make the trace conductive. It can pass current, but its resistance is relatively large, and the current passing through it will be relatively small.

[0098] In some embodiments, Fig.10 As shown, the resistor structure 30 further includes a second line segment 30 b , which is electrically connected to the first line segment 30 a , and the second line segment 30 b and the first line segment 30 a are located in different layers.

[0099] For example, the resistor structure 30 may include a plurality of first line segments 30a and second line segments 30b. The first line segments 30a and the second line segments 30b are alternately arranged, and the first line segments 30a and the second line segments 30b are connected through vias h2.

[0100] As an example, the second line segment 30b and the power supply line 41 are located in the same film layer. When the two are located in the same film layer, the materials of the two can be the same, so that the second line segment 30b and the power supply line 41 can be prepared at the same time.

[0101] As another example, the second line segment 30b and the power supply line 41 are located in different film layers. In this case, the second line segment 30b, the first line segment 30a, and the power supply line 41 are located in different film layers.

[0102] In the embodiment of the present application, the resistance structure 30 is configured to include a first line segment 30a and a second line segment 30b located in different film layers, which is beneficial for lengthening the routing design of the resistance structure within the same area, thereby facilitating improving the total impedance of the resistance structure, thereby increasing the impedance on the transmission path from the power supply voltage VDD to the first transistor, reducing the impact on the first transistor when the power supply voltage VDD changes, and thereby protecting the first transistor from damage.

[0103] In some embodiments, Figures 11 to 14 As shown in any of the drawings, the display panel further includes a pixel electrode 51 and a common electrode 52 .

[0104] The display panel can be used as a display panel of a liquid crystal display (LCD), and the display panel includes liquid crystal molecules 53. The pixel electrodes 51 and the common electrodes 52 provide an electric field for controlling the rotation of the liquid crystal molecules.

[0105] The pixel of the display panel includes a pixel circuit, and the pixel electrode is connected to the transistor in the pixel circuit and is used to receive the data voltage transmitted by the transistor in the pixel circuit. The common electrode is used to receive the common voltage. Exemplarily, the pixel includes sub-pixels, and the common electrodes in multiple sub-pixels can be electrically connected to each other.

[0106] Please refer to Figure 1 and Figures 11 to 14 In any of the figures, the resistor structure 30 at least includes a first line segment 30a, the first line segment 30a and the power line 41 are located in different film layers, the first line segment and the pixel electrode 51 are located in the same layer, and / or the first line segment 30a and the common electrode 52 are located in the same layer.

[0107] Exemplarily, the display panel further includes a substrate 54 , and the pixel electrode 51 and the common electrode 52 are located on one side of the substrate 54 .

[0108] As an example, Fig.11 As shown, the pixel electrode 51 and the common electrode 52 are located in the same layer. Here, the first line segment, the pixel electrode 51 and the common electrode 52 may be located in the same layer.

[0109] As another example, Fig.12 or Fig.13 As shown, the film layer where the pixel electrode 51 is located is located between the film layer where the common electrode 52 is located and the substrate 54 .

[0110] For example, the display panel further includes an opposing plate 55, the liquid crystal molecules 53 are located between the substrate 54 and the opposing plate 55, the pixel electrodes 51 are located on the side of the substrate 54 facing the liquid crystal molecules 53, and the common electrodes 52 are located on the side of the opposing plate 55 facing the liquid crystal molecules 53. Fig.13 As shown, the pixel electrode 51 and the common electrode 52 are both located on the side of the substrate 54 facing the liquid crystal molecules 53, and in the thickness direction of the display panel, the film layer where the pixel electrode 51 is located is located between the film layer where the common electrode 52 is located and the substrate 54, and the pixel electrode 51 and the common electrode 52 are separated by an insulating layer 01. Here, the film layer where the pixel electrode 51 is located may be provided with a first line segment, and / or the film layer where the common electrode 52 is located may be provided with a first line segment.

[0111] As another example, Fig.14 As shown, the film layer where the common electrode 52 is located is located between the film layer where the pixel electrode 51 is located and the substrate 54. For example, the pixel electrode 51 and the common electrode 52 are both located on the side of the substrate 54 facing the liquid crystal molecules 53, and in the thickness direction of the display panel, the film layer where the common electrode 52 is located is located between the film layer where the pixel electrode 51 is located and the substrate 54. Here, the film layer where the pixel electrode 51 is located may be provided with a first line segment, and / or, the film layer where the common electrode 52 is located may be provided with a first line segment.

[0112] In an embodiment of the present application, the first line segment of the resistance structure is designed to be located in the same film layer as the pixel electrode and / or the common electrode, and the first line segment can be prepared at the same time as the pixel electrode and / or the common electrode. In this way, no additional preparation process will be added when the first line segment is additionally provided.

[0113] It is understandable that when the pixel electrode and / or the common electrode is a metal electrode and the first line segment is in the same layer as the pixel electrode and / or the common electrode, the first line segment is a metal trace. In another embodiment, the material of the pixel electrode and / or the common electrode is ITO and the material of the first line segment is ITO in the same layer as the pixel electrode and / or the common electrode.

[0114] In some other embodiments, the first line segment is a semiconductor trace. For example, the first transistor includes an active layer, and the first line segment and the active layer of the first transistor are located in the same film layer. In this case, the first line segment and the active layer of the first transistor are made of the same material, and the first line segment can be prepared while preparing the active layer of the first transistor, so that no additional preparation process is added when the first line segment is additionally provided.

[0115] As an example, Fig.15 As shown, the display panel includes a substrate 56, and a gate metal layer Gate, a semiconductor layer B, a source and drain metal layer S / D, and a transparent conductive layer 57 are stacked on one side of the substrate 56. In addition, 02 and 03 represent insulating layers. Exemplarily, the material of the semiconductor layer B includes A-Si, the material of the transparent conductive layer 57 includes ITO, and the materials of the gate metal layer Gate and the source and drain metal layer S / D include metals such as copper, aluminum, and molybdenum. The material impedances of the source and drain metal layer S / D, the gate metal layer Gate, the transparent conductive layer 57, and the semiconductor layer B increase in sequence. Any one or more of these film layers may be provided with a first line segment of a resistor structure, and the wiring to be connected may be connected through vias.

[0116] Exemplarily, the active layer of the first transistor is located in the semiconductor layer B, and the power supply line is located in the gate metal layer Gate. For example, the semiconductor layer B and / or the transparent conductive layer 57 with relatively large material impedance may be provided with a first line segment of a resistance structure.

[0117] In some embodiments, Fig.16 As shown, the display panel includes a plurality of transmission signal lines 40, which are electrically connected to the gate drive circuit. The transmission signal lines 40 include a power line 41, which is used to transmit the power supply voltage VDD. Other transmission signal lines 40 can be used to transmit clock signals (CK), trigger signals (STV), reset signals (TRSET), low levels (LVGL), etc.

[0118] In a direction perpendicular to the plane where the display panel is located, the first line segment 30a overlaps the transmission signal line 40 adjacent to the power line 41. Here, the direction perpendicular to the plane where the display panel is located can be understood as: the thickness direction of the display panel.

[0119] For example, a plurality of transmission signal lines 40 extend along the first direction X and are arranged in the second direction Y. At least one transmission signal line 40 is provided on both sides of the power line 41 in the second direction Y. The first line segment 30a overlaps with the transmission signal lines 40 on both sides of the power line 41, or the first line segment 30a overlaps with the transmission signal lines 40 on at least one side of the power line 41. In this solution, there is no need to provide an additional area for setting the first line segment, so as to prevent an increase in the area of ​​the circuit layout.

[0120] The first line segment 30a overlaps with the transmission signal line 40 outside the power line 41, and at least the overlapping part can constitute an overlapping capacitor. The overlapping capacitor can also increase the delay effect, thereby avoiding the voltage change of the power supply voltage directly impacting the first transistor and improving the problem of easy damage to the first transistor.

[0121] It should be noted that Fig.16 The number of the transmission signal traces 40 and the shape of the first line segment 30 a shown are not intended to limit the present application.

[0122] In other examples, such as Fig.17 As shown, the first line segment 30a and the power supply line 41 can also be arranged in the same layer. In the case where the two are arranged in the same layer, the first line segment 30a can also be designed as a square wave, sawtooth, serpentine or other shaped bending line to increase the length of the first line segment 30a. In this case, along the direction perpendicular to the plane where the display panel is located, the first line segment 30a and the transmission signal line 40 do not overlap.

[0123] In some other embodiments, Fig.18As shown, the display panel includes a plurality of transmission signal lines 40, the transmission signal lines 40 are electrically connected to the gate drive circuit 10, and the transmission signal lines 40 include power lines 41. The plurality of shift registers 11 of the gate drive circuit 10 are arranged along a first direction X. The display panel includes a wiring area Q1, a circuit area Q3, and a resistor area Q2, the transmission signal lines 40 are located in the wiring area Q1, the gate drive circuit 10 is located in the circuit area Q3, the resistor structure 30 is located in the resistor area Q2, and along the second direction Y, the resistor area Q2 is located between the wiring area Q1 and the circuit area Q3, and the second direction Y intersects with the first direction X.

[0124] In the routing area Q1 , a plurality of transmission signal routing lines 40 extend along a first direction X and are distributed in a second direction Y. As shown in FIG.

[0125] Exemplarily, when different shift registers 11 are connected to different resistance structures 30 , a plurality of resistance structures 30 may be arranged along the first direction X in the resistance region Q2 .

[0126] Exemplarily, in the second direction Y, when the resistance region Q2 is located in the middle, the connection lines between other transmission signal lines 40 other than the power line 41 and the gate driving circuit 10 may pass through the resistance region Q2.

[0127] In this embodiment, the routing area Q1 is used to set the transmission signal routing 40, the circuit area Q3 is used to set the gate drive circuit, and the resistance area Q2 is used to set the resistance structure 30. The partitioning facilitates flexible design of the structure in each area.

[0128] Of course, in other examples, it can also be set as follows: in the second direction Y, the routing area Q1 is located in the middle, and the resistor area Q2 and the circuit area Q3 are located on both sides of the routing area Q1. Alternatively, the relative position relationship of the routing area Q1, the circuit area Q3 and the resistor area Q2 can be designed according to other position relationships.

[0129] In some embodiments, Figure 1 As shown, the resistance structure 30 is connected between the shift register 11 and the power line 41. As an example, the display panel includes the power line 41 and the connection line 42, the power line 41 is used to transmit the power supply voltage VDD, the multiple shift registers 11 of the gate driving circuit 10 are arranged along the first direction X, the power line 41 extends along the first direction X, and the connection line 42 is connected between the power line 41 and the first transistor 111; the connection line 42 includes the resistance structure 30.

[0130] Exemplarily, the impedance of the connection line 42 is greater than the impedance of the power line 41 .

[0131] For example, at least part of the line segments of the connection line 42 may be configured as a bending line in a square wave shape, a sawtooth shape, a serpentine shape, or other shapes.

[0132] like Figure 1 As shown, each shift register 11 is electrically connected to the power supply line 41 through a connection line 42, and each connection line 42 includes a resistor structure 30. In this example, it is ensured that the first transistor of each shift register is connected to the power supply voltage VDD through the resistor structure, thereby protecting the first transistor in each shift register from being easily damaged.

[0133] As another example, Fig.19 As shown, when the resistance structure 30 is connected between the shift register 11 and the power supply line 41, one resistance structure 30 can be connected to the first transistors 111 of multiple shift registers 11. For example, one resistance structure 30 can be connected to the first transistors 111 of two shift registers 11. In this embodiment, one resistance structure 30 is shared by multiple shift registers 11.

[0134] In other embodiments, Figure 2 As shown, the resistance structure 30 is connected between the driving chip 200 and the power supply line 41. Specifically, the display panel includes a power supply line 41, which is used to transmit the power supply voltage VDD. The power supply line 41 is electrically connected to at least two stages of shift registers 11, and the power supply line 41 is connected between the resistance structure 30 and the first transistor 111. The driving chip 200 is used to provide the power supply voltage VDD. The power supply voltage VDD output by the driving chip 200 is first transmitted to the resistance structure 30, then transmitted to the power supply line 41, and then transmitted to each first transistor 111. It can be understood that in this embodiment, the resistance structure 30 is shared by multiple shift registers, so that while reducing the total number of resistance structures, the protection of the first transistors in multiple shift registers can also be taken into account.

[0135] Exemplarily, in the case where the resistance structure is connected between the power line and the first transistor, or in the case where the power line is connected between the resistance structure and the first transistor, the line shape of the resistance structure includes but is not limited to square waveform, sawtooth shape, serpentine shape, etc., and the film layer position of the resistance structure includes but is not limited to: at least part of the line segments of the resistance structure and the power line are located in different film layers, at least part of the line segments of the resistance structure and the active layer of the first transistor are located in the same film layer, at least part of the line segments of the resistance structure are located in the transparent conductive layer, at least part of the line segments of the resistance structure and the pixel electrodes and / or common electrodes of the display panel are located in the same film layer, etc.

[0136] In some embodiments, considering the influence of the impedance of the power supply line 41 itself on each level of the shift register, the resistance of the resistance structure connected to at least two different shift registers may be designed to be different.

[0137] For example, Fig. 20As shown, the multiple shift registers 11 include a first shift register 11-1 and a second shift register 11-2, and the resistance structure includes a first sub-resistance structure 30-1 and a second sub-resistance structure 30-2. The first sub-resistance structure 30-1 is connected between the power supply line 41 and the first shift register 11-1, and the second sub-resistance structure 30-2 is connected between the power supply line 41 and the second shift register 11-2. The transmission path length of the power supply voltage VDD connected to the first shift register 11-1 in the power supply line 41 is shorter than the transmission path length of the power supply voltage VDD connected to the second shift register 11-2 in the power supply line 41, and the resistance of the first sub-resistance structure 30-1 is greater than the resistance of the second sub-resistance structure 30-2.

[0138] For example, in the first direction X and in the direction away from the driver chip 200, the first shift register 11(1) to the nth shift register 11(n) are arranged respectively, and the first shift register 11(1) to the nth shift register 11(n) are connected to the power line 41 through the first resistance structure 30(1) to the nth resistance structure 30(n) respectively. The first shift register can be the i-th shift register, the second shift register can be the j-th shift register, and 1≤i<j≤n, i and j are integers.

[0139] Exemplarily, the transmission path lengths of the power supply voltage VDD connected to the first shift register 11 (1) to the nth shift register 11 (n) in the power line 41 increase successively, and the resistances of the first resistance structure 30 (1) to the nth resistance structure 30 (n) may decrease successively.

[0140] It is understandable that the embodiments of the present application can balance the impedance of the transmission paths through which the power supply voltages received by different shift registers pass, thereby facilitating the improvement of display uniformity while protecting the first transistors in the shift registers.

[0141] In some embodiments, the impedance of the resistive structure may be fixed.

[0142] In some other embodiments, the impedance of the resistance structure is variable. For example, the impedance of the resistance structure is different under different working conditions of the display panel. In this way, different protection requirements for the first transistor in the shift register under different working conditions can be met.

[0143] The inventors have found that the higher the temperature, the greater the conductivity of the active layer in the transistor, the greater the current passing through the transistor, and the greater the degree of damage to the first transistor caused by the change in the power supply voltage. As an example, as the temperature rises, the impedance of the resistance structure increases. This improves the problem that the first transistor is easily damaged at high temperatures.

[0144] In some embodiments, Figures 5 to 7As shown, the gate of the first transistor 111 and its first electrode both need to be connected to the power supply voltage VDD, and at least the gate of the first transistor 111 is connected to the power supply voltage VDD through the resistor structure 30. Whether the first transistor is turned on is mainly affected by its gate potential, so its gate is connected to the power input signal through the resistor structure, which can reduce the large current impact on the gate of the first transistor due to the large instantaneous change of the connected power supply voltage, that is, avoid the voltage change of the power supply voltage directly impacting the gate of the first transistor, thereby improving the problem of easy damage to the first transistor.

[0145] In other examples, such as Fig.21 and Fig. 22 As shown, the gate electrode and the first electrode of the first transistor 111 are both connected to the power supply voltage VDD through the resistor structure 30. Fig.21 As shown, the gate electrode and the first electrode of the first transistor 111 are connected to the power supply voltage VDD through the same resistor structure 30. Fig. 22 As shown, the gate and the first electrode of the first transistor 111 are connected to the power supply voltage VDD through different resistance structures 30 .

[0146] In some embodiments, the working stage of the display panel includes a first stage, in which the power supply voltage VDD is at a first level, and the first level controls the first transistor 111 to be turned on. For example, the first transistor 111 is an N-type transistor, and the first level is a high potential vgh. Alternatively, the first transistor 111 is a P-type transistor, and the first level is a low potential vgl. Here, the high potential vgh may be approximately about 30V, and the low potential vgl may be approximately about -10V.

[0147] Exemplarily, when the working stage of the display panel includes a first stage, such as Figure 6 or Figure 7 As shown, the shift register may include only one first transistor.

[0148] In some embodiments, Figure 5 As shown, the shift register includes two first transistors, which are transistor M16 and transistor M17 respectively, the resistance structure 30 includes a first resistance structure 31 and a second resistance structure 32, the power supply voltage VDD includes a first power supply voltage VDD1 and a second power supply voltage VDD2, one of the first transistors (such as transistor M16) is connected to the first power supply voltage VDD1 through the first resistance structure 31, and the other first transistor (such as transistor M17) is connected to the second power supply voltage VDD2 through the second resistance structure 32.

[0149] Figure 5The shift register shown includes two pull-down maintaining modules, and the first power supply voltage VDD1 and the second power supply voltage VDD2 are respectively responsible for controlling one pull-down maintaining module.

[0150] For example, Fig.23 As shown, the first power supply voltage VDD1 and the second power supply voltage VDD2 are signals with high and low levels interlaced. Specifically, the working stage of the display panel includes a first stage p1 and a second stage p2 that are alternately set. In the first stage p1, the first power supply voltage VDD1 is a first level, and the second power supply voltage VDD2 is a second level. In the second stage p2, the first power supply voltage VDD1 is a second level, and the second power supply voltage VDD2 is a first level; the second level is lower than the first level, and the first level controls the first transistor to be turned on, and the second level controls the first transistor to be turned off. In this embodiment, the first transistor is an N-type transistor for example. It can be understood that the same is applicable to the P-type first transistor. When the first transistor is a P-type transistor, the first level is less than the second level.

[0151] The first power supply voltage VDD1 and the second power supply voltage VDD2 are high and low level alternating signals, so that when one pull-down maintenance module is working, the other pull-down maintenance module is resting, so that the two pull-down maintenance modules are resting half of the time, thereby increasing the reliability of the shift register.

[0152] The first power supply voltage VDD1 and the second power supply voltage VDD2 are signals with different timing sequences and can be transmitted using different routing lines. Figure 5 As shown, the display panel further includes a power supply line 41 , which includes a first power supply line 411 and a second power supply line 412 . The first power supply line 411 is used to transmit a first power supply voltage VDD1 , and the second power supply line 412 is used to transmit a second power supply voltage VDD2 .

[0153] Exemplarily, the first resistance structure 31 may be connected between the first power supply line 411 and one of the first transistors, or the first power supply line 411 may be connected between the first resistance structure 31 and one of the first transistors.

[0154] The second resistance structure 32 may be connected between the second power supply line 412 and another first transistor, or the second power supply line 412 may be connected between the second resistance structure 32 and another first transistor.

[0155] The shape characteristics, material characteristics, film layers, etc. of the first resistor structure 31 and / or the second resistor structure 32 may be the same as those described for the resistor structure 30 in the above embodiment, and will not be described in detail here.

[0156] In some embodiments, please refer to Fig.23The working stage of the display panel also includes a third stage p3. In the third stage p3, the first power supply voltage VDD1 undergoes a level conversion, and the second power supply voltage VDD2 undergoes a level conversion. The third stage p3 is located between the first stage p1 and the second stage p2. The first stage p1 and the second stage p2 both include a frame stage. The third stage p3 includes a blanking stage, and the blanking stage is located between two adjacent frame stages. The blanking stage can be called a blank stage.

[0157] In the frame stage, the shift registers at each level of the gate drive circuit output valid pulse signals one by one, thereby realizing row-by-row scanning of pixels, writing the data voltage into the corresponding pixels, and the display panel displays normally. In the blanking stage, the gate drive circuit does not output a valid pulse signal, and no longer writes the data voltage. Therefore, the first power supply voltage VDD1 and the second power supply voltage VDD2 are set to perform level conversion in the blanking stage, which will not affect the normal display of the display panel.

[0158] Exemplarily, the duration of the first stage p1 is longer than the duration of the third stage p3, and the duration of the second stage p2 is longer than the duration of the third stage p3.

[0159] Exemplarily, the duration of the first stage p1 and the second stage p2 are equal.

[0160] The above embodiment introduces that a resistor structure is added to the display panel to prolong the voltage change process of the power supply voltage actually received by the first transistor, so as to reduce the large current impact on the first transistor caused by the excessive instantaneous change of the connected power supply voltage.

[0161] Based on the same inventive concept, the power supply voltage output by the driver chip can also be directly changed. For example, the delay in the change of the power supply voltage output by the driver chip can be increased, that is, the time taken for the power supply voltage level switching output by the driver chip can be increased. This can directly avoid the impact on the first transistor when the power supply voltage jumps directly in a short time, thereby protecting the first transistor from damage.

[0162] Specifically, the present application also provides a driver chip, such as Figure 24 to Figure 27 As shown, the driving chip is used to provide a power supply voltage VDD to the gate driving circuit in the display panel. The power supply voltage VDD provided by the driving chip is a first level in the first stage p1, a second level in the second stage p2, and a third level in the third stage p3. The third stage p3 is between the first stage p1 and the second stage p2, and the third level is between the first level and the second level. At the first level, the first transistor in the gate driving circuit is turned on.

[0163] It should be noted that in the timing diagram of the present application, the first level is a high potential, the second level is a low potential, and the first transistor is an N-type transistor for illustration, but this is not used to limit the present application. The same applies to the P-type first transistor. When the first transistor is a P-type transistor, the first level is a low potential and the second level is a high potential.

[0164] The third stage p3 is the switching stage of the power supply voltage VDD between the first level and the second level, that is, the embodiment of the present application directly changes the power supply voltage output by the driver chip, which increases the time taken for switching the power supply voltage level output by the driver chip, and can directly avoid the impact on the first transistor when the power supply voltage directly jumps in a short time, thereby protecting the first transistor from being damaged.

[0165] In some embodiments, the gate drive circuit is also connected to a clock signal, the time required for the clock signal to jump from the first level to the second level is t2, the time required for the third stage p3 is t1, and t1>t2. In other words, the time required for the power supply voltage VDD output by the driver chip to switch levels is longer than the time required for the clock signal to switch levels.

[0166] In other examples, the specific duration of the third stage can be set according to needs.

[0167] In some embodiments, the display panel includes a blanking phase between adjacent frames, the third phase is subordinate to the blanking phase, the duration of the third phase p3 is t1, and the duration of the blanking phase is t blank , t1≤t blank .

[0168] In the frame stage, the shift registers at each level of the gate drive circuit output valid pulse signals one by one, thereby realizing line-by-line scanning of pixels, controlling the pixel light emission, and the display panel displays normally. In the blanking stage, the gate drive circuit does not output a valid pulse signal. Therefore, the power supply voltage VDD is set to perform level conversion in the blanking stage, which will not affect the normal display of the display panel.

[0169] In some embodiments, the third level is a gradually changing level. That is, the power supply voltage VDD gradually transitions from the first level to the second level, and the smaller the change in the power supply voltage VDD is, the smaller the current on its transmission path is, which is more conducive to protecting the first transistor.

[0170] As an example, Fig.24 As shown, the third level of the power supply voltage VDD in the third stage p3 changes in a step-like manner.

[0171] Specifically, when the third level of the power supply voltage VDD in the third stage p3 changes in a step-like manner, the amount of change of the third level each time may be the same. For example, ΔV1 = ΔV2 = ΔV3.

[0172] This embodiment can ensure that each time the power supply voltage VDD changes, the Vgs of the first transistor is the same, that is, the impact on the first transistor is the same, thereby avoiding a greater impact on the first transistor.

[0173] As another example, Fig.25 As shown, the third level of the power supply voltage VDD in the third stage p3 changes in an oblique manner.

[0174] As another example, Fig.26 or Fig. 27 As shown, the third level of the power supply voltage VDD in the third phase p3 changes in a curve.

[0175] Optional, such as Fig.26 As shown, the slope of the variation curve of the third level of the power supply voltage VDD in the third stage p3 gradually decreases.

[0176] It should be noted that the variation of the third level of the power supply voltage VDD in the third stage p3 includes but is not limited to: Figure 24 to Figure 26 Variations shown.

[0177] Based on the same inventive concept, a signal delay structure can also be added to the driver chip. For example, the signal delay structure includes a resistance structure to prolong the voltage change process of the power supply voltage actually received by the first transistor, so as to reduce the large current impact on the first transistor due to the excessive instantaneous change of the connected power supply voltage.

[0178] Specifically, Fig.28 As shown, the driving chip 200 includes a signal generating circuit 201 and a signal delay structure 202. The signal generating circuit 201 is used to generate a power supply voltage VDD. One end of the signal delay structure 202 is electrically connected to the output end of the signal generating circuit 201, and the other end of the signal delay structure 202 is used to electrically connect to the gate driving circuit in the display panel.

[0179] The signal delay structure 202 can prolong the voltage change process of the power supply voltage actually received by the first transistor, so as to reduce the large current impact on the first transistor caused by the excessive instantaneous change of the connected power supply voltage.

[0180] For example, the signal delay structure 202 includes a resistance structure.

[0181] The present application also provides a display device, including the display panel provided by the present application, and / or, including the driver chip provided by the embodiment of the present application. Fig.29 , Fig.29 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.29The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application, and / or the driving chip 200 provided by any of the above embodiments of the present application. Fig.29 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0182] It should be noted that the transistor in the embodiment of the present application can be an N-type transistor or a P-type transistor. For an N-type transistor, the on-level is a high level and the off-level is a low level. That is, when the gate potential of the N-type transistor is a high level, the first pole and the second pole are connected, and when the gate potential of the N-type transistor is a low level, the first pole and the second pole are disconnected. For a P-type transistor, the on-level is a low level and the off-level is a high level. That is, when the gate potential of the P-type transistor is a low level, the first pole and the second pole are connected, and when the gate potential of the P-type transistor is a high level, the first pole and the second pole are disconnected.

[0183] In a specific implementation, the gate of each of the above-mentioned transistors serves as its control electrode, and, according to the signal of the gate of each transistor and its type, its first electrode can be used as the source and the second electrode as the drain, or its first electrode can be used as the drain and the second electrode as the source, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present application are general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / shut down the transistor.

[0184] It should be noted that in the embodiments shown in the above figures, the resistor is represented by a single resistor, and the capacitor is represented by a single capacitor. In other embodiments, the resistor may be an integration of series, parallel or mixed resistors, and the capacitor may be an integration of series, parallel or mixed capacitors. The specific parameters of each device can be set according to actual needs, and this application does not limit this.

[0185] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: include: A gate driving circuit includes a plurality of cascaded shift registers, wherein the shift register includes a first transistor, and the first transistor is connected to a power supply voltage through a resistance structure.

2. The display panel according to claim 1, characterized in that: The display panel includes a power supply line for transmitting the power supply voltage. The resistance structure includes a first line. The impedance per unit length of at least a portion of the first line segment is greater than the impedance per unit length of the power supply line.

3. The display panel according to claim 1, characterized in that: The display panel includes a power supply line, and the power supply line is used to transmit the power supply voltage. The resistance structure includes a first line, and the line width of the first line is smaller than the line width of the power supply line.

4. The display panel according to claim 1, characterized in that: The resistor structure includes a first wiring line, and the first wiring line includes a meander line.

5. The display panel according to claim 4, characterized in that: The bending line is in any one of a square wave shape, a sawtooth shape, and a serpentine shape.

6. The display panel according to claim 1, characterized in that: The display panel includes a power supply line, and the power supply line is used to transmit the power supply voltage. The resistance structure includes at least a first line segment, and the first line segment and the power supply line are located in different layers.

7. The display panel according to claim 6, characterized in that: The first line segment includes a transparent conductive material or a semiconductor material.

8. The display panel according to claim 6, characterized in that: The display panel further includes a pixel electrode and a common electrode, and the first line segment and the pixel electrode are located in the same layer, and / or the first line segment and the common electrode are located in the same layer.

9. The display panel according to claim 8, characterized in that: The display panel further includes a substrate; The pixel electrode and the common electrode are located on one side of the substrate; The pixel electrode and the common electrode are located in the same layer, or the film layer where the pixel electrode is located is located between the film layer where the common electrode is located and the substrate, or the film layer where the common electrode is located is located between the film layer where the pixel electrode is located and the substrate.

10. The display panel according to claim 6, characterized in that: The first transistor includes an active layer, and the first line segment and the active layer of the first transistor are located in the same layer.

11. The display panel according to claim 6, characterized in that: The display panel comprises a plurality of transmission signal lines, the transmission signal lines are electrically connected to the gate drive circuit, and the transmission signal lines include the power supply lines; Along a direction perpendicular to the plane where the display panel is located, the first line segment overlaps with a transmission signal line adjacent to the power line.

12. The display panel according to claim 6, characterized in that: The resistor structure further includes a second line segment, which is electrically connected to the first line segment and is located in a different layer from the first line segment.

13. The display panel according to claim 1, characterized in that: The display panel includes a power supply line and a connecting line, the power supply line is used to transmit the power supply voltage, the plurality of shift registers of the gate driving circuit are arranged along a first direction, the power supply line extends along the first direction, and the connecting line is connected between the power supply line and the first transistor; The connecting line includes the resistance structure.

14. The display panel according to claim 1, characterized in that: The display panel comprises a plurality of transmission signal lines, the transmission signal lines are electrically connected to the gate drive circuit, and the transmission signal lines include the power supply lines; The plurality of shift registers of the gate driving circuit are arranged along a first direction; The display panel includes a routing area, a circuit area and a resistance area, the transmission signal routing is located in the routing area, the gate drive circuit is located in the circuit area, the resistance structure is located in the resistance area, and along a second direction, the resistance area is located between the routing area and the circuit area, and the second direction intersects with the first direction.

15. The display panel according to claim 1, characterized in that: The resistance structure may have a variable impedance.

16. The display panel according to claim 15, characterized in that: As the temperature increases, the impedance of the resistive structure increases.

17. The display panel according to claim 1, characterized in that: The multiple shift registers include a first shift register and a second shift register, the resistance structure includes a first sub-resistance structure and a second sub-resistance structure, the first sub-resistance structure is connected between the power supply line and the first shift register, the second sub-resistance structure is connected between the power supply line and the second shift register, the transmission path length of the power supply voltage connected to the first shift register in the power supply line is shorter than the transmission path length of the power supply voltage connected to the second shift register in the power supply line, and the resistance of the first sub-resistance structure is greater than the resistance of the second sub-resistance structure.

18. The display panel according to claim 1, characterized in that: The display panel includes a power supply line, the power supply line is used to transmit the power supply voltage, the power supply line is electrically connected to at least two stages of shift registers, and the power supply line is connected between the resistance structure and the first transistor.

19. The display panel according to claim 1, characterized in that: The gate electrode and the first electrode of the first transistor are connected to the power supply voltage, and at least the gate electrode of the first transistor is connected to the power supply voltage through the resistance structure.

20. The display panel according to claim 1, characterized in that: The working phase of the display panel includes a first phase. In the first phase, the power supply voltage is at a first level, and the first level controls the first transistor to be turned on.

21. The display panel according to claim 1, characterized in that: The resistance structure includes a first resistance structure and a second resistance structure, the shift register includes two first transistors, the power supply voltage includes a first power supply voltage and a second power supply voltage, one of the first transistors is connected to the first power supply voltage through the first resistance structure, and the other first transistor is connected to the second power supply voltage through the second resistance structure; The display panel further includes power lines, and the power lines include a first power line and a second power line. The first power line is used to transmit the first power voltage, and the second power line is used to transmit the second power voltage.

22. The display panel according to claim 21, characterized in that: The working phase of the display panel includes a first phase and a second phase which are alternately arranged, in which the first power supply voltage is at a first level and the second power supply voltage is at a second level, and in which the first power supply voltage is at a second level and the second power supply voltage is at a first level. The second level is lower than the first level, and the first level controls the first transistor to be turned on, and the second level controls the first transistor to be turned off.

23. The display panel according to claim 22, characterized in that: The working stage of the display panel also includes a third stage. In the third stage, the first power supply voltage undergoes a level conversion, and the second power supply voltage undergoes a level conversion. The third stage is located between the first stage and the second stage. The first stage and the second stage both include a frame stage. The third stage includes a blanking stage, and the blanking stage is located between two adjacent frame stages.

24. A driver chip, characterized in that: Used to provide a power supply voltage to a gate driving circuit in a display panel, the power supply voltage provided by the driving chip is a first level in the first stage, a second level in the second stage, and a third level in the third stage, the third stage is between the first stage and the second stage, the third level is between the first level and the second level, and at the first level, the first transistor in the gate driving circuit is turned on.

25. The driving chip according to claim 24, characterized in that: The third level is a gradually changing level.

26. The driver chip according to claim 25, characterized in that: The third level changes in a step-like manner.

27. The driving chip according to claim 26, characterized in that: The change amount of the third level is the same each time.

28. The driving chip according to claim 25, characterized in that: The third level changes in an oblique manner.

29. The driving chip according to claim 25, characterized in that: The third level changes in a curve.

30. The driving chip according to claim 29, characterized in that: The slope of the variation curve of the third level gradually decreases.

31. The driving chip according to claim 24, characterized in that: The display panel includes a blanking phase between adjacent frames, and the blanking phase includes the third phase, the duration of the third phase is t1, and the duration of the blanking phase is t blank , t1≤t blank .

32. The driver chip according to claim 25, characterized in that: The gate driving circuit is also connected to a clock signal. The time required for the clock signal to jump from the first level to the second level is t2. The time length of the third stage is t1, and t1>t2.

33. A driver chip, characterized in that: include: A signal generating circuit and a signal delay structure, wherein the signal generating circuit is used to generate a power supply voltage, one end of the signal delay structure is electrically connected to the output end of the signal generating circuit, and the other end of the signal delay structure is used to electrically connect to a gate driving circuit in a display panel.

34. A display device, characterized in that: include: A display panel according to any one of claims 1 to 23, and / or a driver chip according to any one of claims 24 to 33.

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