Semiconductor structure and preparation method thereof

Abstract

The preparation method of the semiconductor structure comprises the steps that a substrate is provided, an active region is arranged in the substrate, and the active region is provided with a first groove; forming a high dielectric constant material layer on the side wall of the first groove and the surface of the substrate; the high-dielectric-constant material layer on the surface of the substrate is removed, the high-dielectric-constant material layer on the side wall of the first groove is reserved to serve as a high-dielectric-constant dielectric layer, and the surface of the high-dielectric-constant dielectric layer is flush with or lower than the surface of the substrate in the direction perpendicular to the surface of the substrate; a conductive layer is formed, the conductive layer covers the high-dielectric-constant dielectric layer and fills the first groove, and the conductive layer and the high-dielectric-constant dielectric layer jointly serve as a high-dielectric-constant metal gate. According to the preparation method, short circuit or parasitic capacitance generation between the high-dielectric-constant dielectric layer and the conductive plug can be avoided, and the reliability of the semiconductor structure is greatly improved; and meanwhile, the uniformity of the high-dielectric-constant dielectric layer can be improved, so that the stability of the gate threshold voltage of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] As the critical dimensions of semiconductors shrink, transistors will experience short-channel effects, which include the reduction of the threshold voltage of transistors as the channel length decreases, the reduction of drain-induced barriers, etc. Currently, the industry uses buried gates in semiconductor structures to increase the channel length and reduce the short-channel effects.

[0003] At the same time, as the critical dimensions of semiconductors continue to shrink, High K Metal Gate (HKMG) technology has almost become a must-have technology for processes below 45nm. The transistor structure manufactured using HKMG technology is the same as the original planar transistor structure, except that the traditional SiO2 oxide layer is replaced by a High-K insulating layer, and the original silicon gate is replaced by a metal gate. Its advantage is that it can increase the switching speed of the transistor and reduce the gate leakage current.

[0004] However, the novel buried high-k metal gate that combines the buried gate and HKMG has problems of shorting between the conductive plug (PC) and the high-k metal gate or generating parasitic capacitance. Therefore, how to solve these problems has become the focus of current research. Summary of the invention

[0005] The technical problem to be solved by the embodiments of the present disclosure is to provide a semiconductor structure and a preparation method thereof, which can avoid short circuit between a high dielectric constant metal gate and a conductive plug or generation of parasitic capacitance, thereby improving the reliability of the semiconductor structure.

[0006] In order to solve the above technical problems, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, the preparation method comprising: providing a substrate, an active area being arranged in the substrate, and the active area having a first groove; forming a high dielectric constant material layer on the sidewall of the first groove and the surface of the substrate; removing the high dielectric constant material layer on the surface of the substrate, retaining the high dielectric constant material layer on the sidewall of the first groove as a high dielectric constant dielectric layer, in a direction perpendicular to the surface of the substrate, the surface of the high dielectric constant dielectric layer is flush with the surface of the substrate, or lower than the surface of the substrate; forming a conductive layer, the conductive layer covers the high dielectric constant dielectric layer and fills the first groove, the conductive layer and the high dielectric constant dielectric layer together serve as a high dielectric constant metal gate.

[0007] In one embodiment, the step of removing the high dielectric constant material layer on the surface of the substrate and retaining the high dielectric constant material layer on the sidewall of the first trench includes: forming a first mask layer in the first trench, the first mask layer covering the surface of the high dielectric constant material layer; using the first mask layer as a shield to remove the high dielectric constant material layer on the surface of the substrate.

[0008] In one embodiment, the step of forming a first mask layer in the first groove includes: forming a first mask material layer, the first mask material layer fills the first groove and covers the surface of the high dielectric constant material layer on the substrate; removing the first mask material layer on the surface of the high dielectric constant material layer on the substrate, the high dielectric constant material layer serves as an etching stop layer, and retaining the first mask material layer located in the first groove as the first mask layer.

[0009] In one embodiment, the step of removing the first mask material layer on the surface of the substrate includes: over-etching the first mask material layer to remove a portion of the first mask material layer in the first groove, and in a direction perpendicular to the surface of the substrate, the surface of the first mask layer is lower than the surface of the high dielectric constant material layer.

[0010] In one embodiment, in a direction perpendicular to the substrate surface, the surface of the first mask layer is lower than the substrate surface.

[0011] In one embodiment, a height difference between a surface of the first mask layer and a surface of the high dielectric constant material layer is 1 / 2 to 1 times the thickness of the high dielectric constant material layer.

[0012] In one embodiment, before the step of removing the first mask material layer on the surface of the substrate, the step further includes: performing a planarization process on the surface of the first mask material layer.

[0013] In one embodiment, in the step of removing the high dielectric constant material layer on the surface of the substrate using the first mask layer as a shield, an etching process is used to remove the high dielectric constant material layer on the surface of the substrate, and the etching rate of the etching material on the high dielectric constant material layer is greater than the etching rate on the first mask layer.

[0014] In one embodiment, the step of forming a conductive layer includes: forming a conductive material layer on the surface of the substrate and in the first groove; removing a portion of the conductive material layer, and using the remaining conductive material layer as the conductive layer, the high dielectric constant metal gate includes a first region arranged in the first groove and a second region higher than the surface of the substrate, the conductive layer is located in the first region and the second region, and in the first region, the conductive layer covers the high dielectric constant dielectric layer and fills the first groove.

[0015] The method for preparing a semiconductor structure provided by an embodiment of the present disclosure comprises the following steps: forming a high dielectric constant dielectric layer before forming a conductive layer, wherein the surface of the high dielectric constant dielectric layer is flush with the surface of the substrate or lower than the surface of the substrate in a direction perpendicular to the surface of the substrate; after forming the conductive layer, the conductive layer can cover all surfaces of the high dielectric constant dielectric layer that are not in contact with the substrate, thereby preventing the high dielectric constant dielectric layer from having a surface that is not covered by the substrate or the conductive layer, thereby preventing the high dielectric constant dielectric layer from being short-circuited with a conductive plug or generating parasitic capacitance, that is, preventing the high dielectric constant metal gate from being short-circuited with a conductive plug or generating parasitic capacitance, thereby greatly improving the reliability of the semiconductor structure; and at the same time, since a portion of the high dielectric constant material layer is removed before forming the conductive layer to form the high dielectric constant dielectric layer, the uniformity of the high dielectric constant dielectric layer can be improved, thereby improving the stability of the gate threshold voltage of the semiconductor structure.

[0016] The presently disclosed embodiment also provides a semiconductor structure prepared by the above-mentioned preparation method, comprising: a substrate, an active area is arranged in the substrate, and the active area has a first groove; a high dielectric constant metal gate, comprising a first region arranged in the first groove and a second region higher than the surface of the substrate, the high dielectric constant metal gate comprising a high dielectric constant dielectric layer and a conductive layer, the high dielectric constant dielectric layer is arranged in the first region and located on the side wall of the first groove, the conductive layer is located in the first region and the second region, and in the first region, the conductive layer covers the high dielectric constant dielectric layer and fills the first groove. In the direction perpendicular to the surface of the substrate, the surface of the high dielectric constant dielectric layer is flush with the surface of the substrate, or lower than the surface of the substrate.

[0017] In one embodiment, when the surface of the high dielectric constant dielectric layer is flush with the surface of the substrate, the conductive layer located in the second region also covers the surface of the high dielectric constant dielectric layer; when the surface of the high dielectric constant dielectric layer is lower than the surface of the substrate, the conductive layer located in the first region also covers the surface of the high dielectric constant dielectric layer.

[0018] In one embodiment, the conductive layer includes a polysilicon layer, a metal barrier layer, a metal layer and an insulating cap layer, the polysilicon layer is located in the first region and the second region, and in the first region, the polysilicon layer covers the high dielectric constant dielectric layer and fills the first trench, the metal barrier layer is located in the second region and covers the polysilicon layer, the metal layer is located in the second region and covers the metal barrier layer, and the insulating cap layer is located in the second region and covers the metal layer.

[0019] In the semiconductor structure provided by the embodiment of the present disclosure, the high dielectric constant dielectric layer is covered by the substrate and the conductive layer, thereby avoiding short circuit or parasitic capacitance between the high dielectric constant dielectric layer and the conductive plug, that is, avoiding short circuit or parasitic capacitance between the high dielectric constant metal gate and the conductive plug, thereby greatly improving the reliability of the semiconductor structure; at the same time, the high dielectric constant dielectric layer has good uniformity, thereby improving the stability of the gate threshold voltage of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A It is a schematic diagram of a semiconductor structure;

[0021] Figure 1B It is a schematic diagram of another semiconductor structure;

[0022] Figure 2 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0023] Figure 3A to Figure 3I It is a schematic diagram of a semiconductor structure formed by the main steps of the preparation method provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In some methods for preparing semiconductor structures, a high dielectric constant dielectric layer is usually formed simultaneously with a conductive layer. For example, a method for preparing a semiconductor structure includes: forming a high dielectric constant dielectric material layer and a conductive material layer on the surface of a substrate 100 and in a groove inside the substrate 100; patterning the high dielectric constant dielectric material layer and the conductive material layer to form a high dielectric constant dielectric layer 110 and a conductive layer 120. The semiconductor structure formed by this preparation method is as follows: Figure 1A and Figure 1B As shown, in the semiconductor structure, the high dielectric constant dielectric layer 110 is higher than the surface of the substrate 100, and there is an area that is not covered by the substrate 100 and the conductive layer 120, such as Figure 1A and Figure 1B The area circled by the dotted box A.

[0025] Since the high-k dielectric material layer is thick and difficult to etch, there is a residual portion of the high-k dielectric layer 110 that is higher than the surface of the substrate 100. If the residual portion is large, it may be connected to the conductive plug 130 adjacent to the high-k dielectric layer, causing the conductive plug 130 to be short-circuited with the high-k dielectric layer, and then causing the high-k metal gate to be connected to the conductive plug 130. Please refer to Figure 1A .

[0026] In addition, if no residual portion is generated or the residual portion is not connected to the conductive plug 130, since the area of ​​the high dielectric constant dielectric layer 110 higher than the surface of the substrate 100 is not completely covered by the conductive layer, for example, Figure 1B As shown, in the area circled by the dotted box A, the sidewalls of the high dielectric constant dielectric layer 110 are not covered by the conductive layer 120 and the substrate 200, and are affected by the conductive plug 130. Parasitic capacitance is generated between the high dielectric constant dielectric layer 110 and the conductive plug 130, affecting the performance of the semiconductor structure.

[0027] In view of this, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, which can avoid the high dielectric constant dielectric layer having a surface that is not covered by the substrate or the conductive layer, thereby avoiding short circuit between the high dielectric constant dielectric layer and the conductive plug or generation of parasitic capacitance.

[0028] The semiconductor structure and the manufacturing method thereof provided by the present invention are described in detail below in conjunction with the accompanying drawings. The semiconductor structure includes but is not limited to a dynamic random access memory (DRAM).

[0029] Figure 2 is a schematic diagram of the steps of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure, please refer to Figure 2 The preparation method comprises: step S20, providing a substrate, wherein an active area is arranged in the substrate, and the active area has a first groove; step S21, forming a high dielectric constant material layer on the sidewall of the first groove and the surface of the substrate; step S22, removing the high dielectric constant material layer on the surface of the substrate, retaining the high dielectric constant material layer on the sidewall of the first groove as a high dielectric constant dielectric layer, in the direction perpendicular to the surface of the substrate, the surface of the high dielectric constant dielectric layer is flush with the surface of the substrate, or lower than the surface of the substrate; step S23, forming a conductive layer, the conductive layer covers the high dielectric constant dielectric layer and fills the first groove, and the conductive layer and the high dielectric constant dielectric layer together serve as a high dielectric constant metal gate.

[0030] The preparation method provided by the embodiment of the present disclosure first forms a high dielectric constant dielectric layer before forming a conductive layer. In the direction perpendicular to the surface of the substrate, the surface of the high dielectric constant dielectric layer is flush with the surface of the substrate, or lower than the surface of the substrate; after the conductive layer is formed, the conductive layer can cover all surfaces of the high dielectric constant dielectric layer that are not in contact with the substrate, which can avoid the existence of a surface of the high dielectric constant dielectric layer that is not covered by the substrate or the conductive layer, thereby avoiding short circuit between the high dielectric constant dielectric layer and the conductive plug or generation of parasitic capacitance, thereby greatly improving the reliability of the semiconductor structure.

[0031] Figure 3A to Figure 3I It is a schematic diagram of a semiconductor structure formed by the main steps of the preparation method provided in one embodiment of the present disclosure.

[0032] Please refer to Figure 1 and Figure 3A , step S20 , providing a substrate 300 , wherein an active region 302 is disposed in the substrate 300 , and the active region 302 has a first trench 303 .

[0033] The substrate 300 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, an SOI substrate or a GOI (Germanium-on-Insulator) substrate, etc.; the substrate 300 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide or silicon carbide, etc., and the substrate 300 may also be a stacked structure, such as a silicon / silicon germanium stack, etc.; in addition, the substrate 300 may be an ion-doped substrate, which may be P-type doped or N-type doped; a plurality of peripheral devices may also be formed in the substrate 300, such as field effect transistors, capacitors, inductors and / or diodes, etc. In this embodiment, the substrate 300 is a silicon substrate, and other device structures may also be included therein, such as a transistor structure, a metal wiring structure, etc., but they are not shown because they are irrelevant to the embodiments of the present disclosure.

[0034] In some embodiments, a shallow trench isolation (STI) 301 is provided in the substrate 300, and the shallow trench isolation 301 divides the substrate 300 into a plurality of active areas 302. The shallow trench isolation 301 includes but is not limited to an oxide isolation structure or a composite isolation structure of an oxide layer and a nitride. For example, in this embodiment, the shallow trench isolation 301 is a composite isolation structure of oxide, nitride, and oxide (ONO).

[0035] In some embodiments, the surface of the substrate 300 is further covered with an oxide layer (not shown in the drawings) for protecting the substrate 300 . The oxide layer includes but is not limited to a silicon oxide layer.

[0036] The first trench 303 extends into the active area 302 along a direction perpendicular to the surface of the substrate 300 (Z direction in the figure). The depth of the first trench 303 extending into the active area 302 can be determined according to the height of the subsequently formed high-k metal gate 370 that needs to be buried in the active area 302.

[0037] In some embodiments, one active area 302 has one first groove 303. In other embodiments, the same active area 302 has two first grooves 303, and the two first grooves 303 are arranged in a direction parallel to the surface of the substrate 300. In this embodiment, an example is taken in which one active area 302 has one first groove 303.

[0038] In some embodiments, the method for forming the first groove 303 in the active area 302 includes: forming a patterned mask layer on the surface of the substrate 300, wherein the patterned mask layer exposes a portion of the active area 302; using the patterned mask layer as a shield, etching the exposed area of ​​the active area 302 to form the first groove 303.

[0039] Please refer to Figure 1 and Figure 3B Step S21: forming a high dielectric constant material layer 310 on the sidewalls of the first trench 303 and the surface of the substrate 300. The high dielectric constant layer only covers the sidewalls of the first trench 303 and the surface of the substrate 300, but does not fill the first trench 303.

[0040] The high dielectric constant material layer 310 may be a single layer structure or a multi-layer composite structure. For example, in some embodiments, the high dielectric constant material layer 310 is a multi-layer composite structure, which is composed of OX, HfSixOx, TiN, AlOx, TiN, LaO, and TiN stacked on the sidewall of the first trench 303, wherein OX is an oxide.

[0041] In this step, a deposition process is used to form the high dielectric constant material layer 310. The deposition process may include, but is not limited to, a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), a high density plasma deposition process (HDP), a plasma enhanced chemical vapor deposition process (PECVD), and a spin-on dielectric layer (SOD) process or a combination thereof.

[0042] Please refer to Figure 1 and Figure 3F, step S22, removing the high dielectric constant material layer 310 on the surface of the substrate 300, retaining the high dielectric constant material layer 310 on the side wall of the first groove 303 to serve as a high dielectric constant dielectric layer 340, in the direction perpendicular to the surface of the substrate 300 (such as the Z direction in the figure), the surface of the high dielectric constant dielectric layer 340 is flush with the surface of the substrate 300, or lower than the surface of the substrate 300.

[0043] In this embodiment, the surface of the high dielectric constant dielectric layer 340 is flush with the surface of the substrate 300. In other embodiments, affected by process parameters such as etching time, the surface of the high dielectric constant dielectric layer 340 is lower than the surface of the substrate 300.

[0044] The inventors further discovered that due to the different silicon crystal phases of the sidewall of the first trench 303 and the surface of the substrate 300, the uniformity control capability of the deposited film layer in the step of depositing the high dielectric constant material layer 310 on the sidewall of the first trench 303 and the surface of the substrate 300 is poor, resulting in different film uniformity of the high dielectric constant material layer 310 on the sidewall of the first trench 303 and the high dielectric constant material layer 310 on the surface of the substrate 300, which will affect the stability of the gate threshold voltage of the semiconductor structure. In this step, the portion of the high dielectric constant material layer 310 located on the surface of the substrate 300 is removed, and the portion located on the sidewall of the first trench 303 is retained, that is, this step forms a uniform high dielectric constant dielectric layer 340, thereby improving the stability of the gate threshold voltage of the semiconductor structure.

[0045] In one embodiment, the step of removing the high dielectric constant material layer 310 on the surface of the substrate 300 and retaining the high dielectric constant material layer 310 on the sidewall of the first trench 303 includes:

[0046] See also Figure 3D , a first mask layer 330 is formed in the first trench 303 , and the first mask layer 330 covers the surface of the high dielectric constant material layer 310 .

[0047] As an example, this embodiment provides a method for forming a first mask layer 330 in the first trench 303. The method includes:

[0048] See also Figure 3C, forming a first mask material layer 320, the first mask material layer 320 fills the first groove 303 and covers the surface of the high dielectric constant material layer 310 on the substrate 300. The first mask material layer 320 includes but is not limited to an organic carbon mask, which can be formed by a spin coating process to ensure that the first groove 303 is filled. In this embodiment, the first mask material layer 320 not only fills the first groove 303, but also covers the surface of the high dielectric constant material layer 310 on the substrate 300. In other embodiments, the first mask material layer 320 may only fill the first groove 303 without covering the surface of the high dielectric constant material layer 310 on the substrate 300, and the top surface of the first mask material layer 320 is flush with the top surface of the high dielectric constant material layer 310.

[0049] See also Figure 3D , remove the first mask material layer 320 on the surface of the high dielectric constant material layer 310 on the substrate 300, the high dielectric constant material layer 310 serves as an etching stop layer, and retain the first mask material layer 320 located in the first trench 303 to serve as the first mask layer 330.

[0050] In this step, it also includes: over-etching the first mask material layer 320 to remove part of the first mask material layer 320 in the first groove 303, and in the direction perpendicular to the surface of the substrate 300 (such as the Z direction in the figure), the surface of the first mask layer 330 is lower than the surface of the high dielectric constant material layer 310, so as to further ensure that the high dielectric constant material layer 310 located on the substrate 300 is completely removed, and when etching the first mask material layer 320, self-alignment can be achieved with the first groove 303 as a limit. In some embodiments, the height difference H between the surface of the first mask layer 330 and the surface of the high dielectric constant material layer 310 is 1 / 2 to 1 times the thickness of the high dielectric constant material layer 310, which can further ensure that the high dielectric constant material layer 310 located on the substrate 300 is completely removed, and can also prevent the high dielectric constant material layer 310 on the side wall of the first groove 303 from being excessively removed to affect the performance of the high dielectric constant metal gate 370.

[0051] In this embodiment, the surface of the first mask layer 330 formed in this step is flush with the surface of the substrate 300, so that the surface of the subsequently formed high dielectric constant dielectric layer 340 is flush with the surface of the substrate 300. In other embodiments, in the direction perpendicular to the surface of the substrate 300, the surface of the first mask layer 330 is lower than the surface of the substrate 300, so that the surface of the subsequently formed high dielectric constant dielectric layer 340 is lower than the surface of the substrate 300.

[0052] In some embodiments, before the step of removing the first mask material layer 320 on the surface of the substrate 300, the step also includes: flattening the surface of the first mask material layer 320 to reduce the etching error in different areas, further ensuring that the first mask material layer 320 on the surface of the high dielectric constant material layer 310 on the substrate 300 is completely removed, thereby further ensuring that the high dielectric constant material layer 310 on the surface of the substrate 300 can be completely removed.

[0053] See also Figure 3E , using the first mask layer 330 as a shield, the high dielectric constant material layer 310 on the surface of the substrate 300 is removed to form a high dielectric constant dielectric layer 340 .

[0054] In this step, an etching process may be used to remove the high dielectric constant material layer 310 on the surface of the substrate 300, and the etching rate of the etching material on the high dielectric constant material layer 310 is greater than the etching rate on the first mask layer 330. For example, in some embodiments, the high dielectric constant material layer 310 may be etched by using a HBr / Cl2 / Ar mixed gas, and the etching rate of the HBr / Cl2 / Ar mixed gas on the high dielectric constant material layer 310 is greater than the etching rate on the first mask layer 330, so that the high dielectric constant material layer 310 can be removed. It can be understood that the HBr / Cl2 / Ar mixed gas will also etch the first mask layer 330, and after this step, the first mask layer 330 is thinned.

[0055] After the etching process is completed, the high dielectric constant material layer 310 located on the sidewall of the first trench 303 is blocked by the first mask layer 330 and is not removed. The high dielectric constant material layer 310 retained on the sidewall of the first trench 303 serves as the high dielectric constant dielectric layer 340 .

[0056] See also Figure 3F In some embodiments, after forming the high dielectric constant dielectric layer 340 , the first mask layer 330 is removed. For example, the semiconductor structure may be cleaned with an acid solution to remove the first mask layer 330 .

[0057] Please refer to Figure 1 and Figure 3H , step S23, forming a conductive layer 360, the conductive layer 360 covers the high dielectric constant dielectric layer 340 and fills the first trench 303, the conductive layer 360 and the high dielectric constant dielectric layer 340 together serve as a high dielectric constant metal gate 370.

[0058] The high-k metal gate 370 includes a first region 360A disposed in the first trench 303 and a second region 360B higher than the surface of the substrate 300. The conductive layer 360 is located in the first region 360A and the second region 360B, that is, the conductive layer 360 extends from the first region 360A to the second region 360B. In the first region 360A, the conductive layer 360 covers the high-k dielectric layer 340 and fills the first trench 303, and the high-k dielectric layer 340 is only located in the first region 360A.

[0059] As an example, the embodiment of the present disclosure further provides a method for forming the conductive layer 360, the method comprising:

[0060] See also Figure 3G , a conductive material layer 350 is formed on the surface of the substrate 300 and in the first groove 303. The conductive material layer 350 not only fills the first groove 303, but also covers the surface of the substrate 300. In this embodiment, the conductive material layer 350 includes a polysilicon material layer 351, a metal barrier material layer 352, a metal material layer 353 and an insulating material layer 354 which are sequentially arranged along a direction perpendicular to the surface of the substrate 300 (such as the Z direction in the figure), the polysilicon material layer 351 fills the first groove 303 and covers the surface of the substrate 300, the metal barrier material layer 352 covers the surface of the polysilicon material layer 351, the metal material layer 353 covers the surface of the metal barrier material layer 352, and the insulating material layer 354 covers the surface of the metal material layer 353.

[0061] See also Figure 3H , remove part of the conductive material layer 350, and the remaining conductive material layer 350 is used as the conductive layer 360. In this step, a patterned mask layer is formed on the surface of the insulating material layer 354 by photolithography and etching processes; and then the insulating material layer 354, the metal material layer 353, the metal barrier material layer 352 and the polysilicon material layer 351 are etched using the mask layer as a shield to form the insulating cap layer 364, the metal layer 363, the metal barrier layer 362 and the polysilicon layer 361.

[0062] In this embodiment, the surface of the high dielectric constant dielectric layer 340 is flush with the surface of the substrate 300, or the surface of the high dielectric constant dielectric layer 340 is lower than the surface of the substrate 300, then the polysilicon layer 361 not only covers the sidewalls of the high dielectric constant dielectric layer 340, but also covers the surface of the high dielectric constant dielectric layer 340.

[0063] See also Fig. 3IAfter forming the high-k metal gate 370 , ion implantation is performed on the active region 302 to form a source region 380 and a drain region 381 , and a conductive plug 390 connected to the source region 380 and the drain region 381 is formed.

[0064] The preparation method provided by the embodiment of the present disclosure can form a high dielectric constant dielectric layer 340 covered by the substrate 300 and the conductive layer 360, thereby avoiding short circuit or parasitic capacitance between the high dielectric constant dielectric layer 340 and the conductive plug 390, thereby avoiding short circuit or parasitic capacitance between the high dielectric constant metal gate 370 and the conductive plug 390, and greatly improving the reliability of the semiconductor structure. At the same time, since a portion of the high dielectric constant material layer 310 is removed before forming the conductive layer 360 to form the high dielectric constant dielectric layer 340, the uniformity of the high dielectric constant dielectric layer 340 can be improved, and the stability of the gate threshold voltage of the semiconductor structure is improved.

[0065] An embodiment of the present disclosure also provides a semiconductor structure formed by the above-mentioned preparation method. Figure 3H and Fig. 3I The semiconductor structure includes: a substrate 300, an active area 302 is arranged in the substrate 300, and the active area 302 has a first trench 303; a high dielectric constant metal gate 370, including a first region 360A arranged in the first trench 303 and a second region 360B higher than the surface of the substrate 300, the high dielectric constant metal gate 370 includes a high dielectric constant dielectric layer 340 and a conductive layer 360, the high dielectric constant dielectric layer 340 is arranged in the first region 360A and is located on the sidewall of the first trench 303, the conductive layer 360 is located in the first region 360A and the second region 360B, and in the first region 360A, the conductive layer 360 covers the high dielectric constant dielectric layer 340 and fills the first trench 303.

[0066] In the semiconductor structure provided by the embodiment of the present disclosure, the high dielectric constant dielectric layer 340 is covered by the substrate 300 and the conductive layer 360, thereby avoiding short circuit or parasitic capacitance between the high dielectric constant dielectric layer 340 and the conductive plug 390, and greatly improving the reliability of the semiconductor structure. At the same time, the high dielectric constant dielectric layer 340 has good uniformity, which improves the stability of the gate threshold voltage of the semiconductor structure.

[0067] In some embodiments, in a direction perpendicular to the surface of the substrate 300, the surface of the high dielectric constant dielectric layer 340 is flush with the surface of the substrate 300, or is lower than the surface of the substrate 300. In this embodiment, the surface of the high dielectric constant dielectric layer 340 is flush with the surface of the substrate 300 as an example for description.

[0068] In some embodiments, the first region 360A and the second region 360B of the high dielectric constant metal gate 370 are divided by the plane where the surface of the substrate 300 is located as a dividing line, and the region located below the plane where the surface of the substrate 300 is located is the first region 360A, and the region located on the plane where the surface of the substrate 300 is located is the second region 360B. In some embodiments, when the surface of the high dielectric constant dielectric layer 340 is flush with the surface of the substrate 300, the conductive layer 360 located in the second region 360B also covers the surface of the high dielectric constant dielectric layer 340; when the surface of the high dielectric constant dielectric layer 340 is lower than the surface of the substrate 300, the conductive layer 360 located in the first region 360A also covers the surface of the high dielectric constant dielectric layer 340.

[0069] In some embodiments, the conductive layer 360 includes a polysilicon layer 361, a metal barrier layer 362, a metal layer 363 and an insulating cap layer 364, the polysilicon layer 361 is located in the first region 360A and the second region 360B, and in the first region 360A, the polysilicon layer 361 covers the high dielectric constant dielectric layer 340 and fills the first trench 303, the metal barrier layer 362 is located in the second region 360B and covers the polysilicon layer 361, the metal layer 363 is located in the second region 360B and covers the metal barrier layer 362, and the insulating cap layer 364 is located in the second region 360B and covers the metal layer 363.

[0070] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preparing a semiconductor structure, It is characterized in that include: Providing a substrate, wherein an active region is disposed in the substrate, and the active region has a first trench; forming a high dielectric constant material layer on the sidewalls of the first trench and the surface of the substrate; Removing the high dielectric constant material layer on the surface of the substrate, retaining the high dielectric constant material layer on the sidewall of the first trench to serve as a high dielectric constant dielectric layer, wherein in a direction perpendicular to the surface of the substrate, the surface of the high dielectric constant dielectric layer is flush with the surface of the substrate, or lower than the surface of the substrate; A conductive layer is formed, the conductive layer covers the high dielectric constant dielectric layer and fills the first trench, and the conductive layer and the high dielectric constant dielectric layer together serve as a high dielectric constant metal gate.

2. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The step of removing the high dielectric constant material layer on the surface of the substrate and retaining the high dielectric constant material layer on the sidewall of the first trench comprises: forming a first mask layer in the first trench, wherein the first mask layer covers a surface of the high dielectric constant material layer; The high dielectric constant material layer on the surface of the substrate is removed using the first mask layer as a shield.

3. The method for preparing a semiconductor structure according to claim 2, It is characterized in that The step of forming a first mask layer in the first trench comprises: forming a first mask material layer, wherein the first mask material layer fills the first trench and covers a surface of the high dielectric constant material layer on the substrate; The first mask material layer on the surface of the high dielectric constant material layer on the substrate is removed, the high dielectric constant material layer is used as an etching stop layer, and the first mask material layer located in the first trench is retained as the first mask layer.

4. The method for preparing a semiconductor structure according to claim 3, It is characterized in that The step of removing the first mask material layer on the surface of the substrate includes: over-etching the first mask material layer to remove a portion of the first mask material layer in the first groove, and in a direction perpendicular to the surface of the substrate, the surface of the first mask layer is lower than the surface of the high dielectric constant material layer.

5. The method for preparing a semiconductor structure according to claim 4, It is characterized in that In a direction perpendicular to the substrate surface, the surface of the first mask layer is lower than the substrate surface.

6. The method for preparing a semiconductor structure according to claim 4, It is characterized in that The height difference between the surface of the first mask layer and the surface of the high dielectric constant material layer is 1 / 2 to 1 times the thickness of the high dielectric constant material layer.

7. The method for preparing a semiconductor structure according to claim 3, It is characterized in that Before the step of removing the first mask material layer on the surface of the substrate, the method further includes: performing a planarization process on the surface of the first mask material layer.

8. The method for preparing a semiconductor structure according to any one of claims 2 to 7, It is characterized in that In the step of removing the high dielectric constant material layer on the surface of the substrate using the first mask layer as a shield, an etching process is used to remove the high dielectric constant material layer on the surface of the substrate, and the etching rate of the etching material on the high dielectric constant material layer is greater than the etching rate on the first mask layer.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 7, It is characterized in that The steps of forming the conductive layer include: forming a conductive material layer on the surface of the substrate and in the first trench; A portion of the conductive material layer is removed, and the remaining conductive material layer serves as the conductive layer. The high dielectric constant metal gate includes a first region arranged in the first groove and a second region higher than the surface of the substrate. The conductive layer is located in the first region and the second region, and in the first region, the conductive layer covers the high dielectric constant dielectric layer and fills the first groove.

10. A semiconductor structure prepared by the preparation method according to any one of claims 1 to 9, It is characterized in that include: A substrate, wherein an active region is disposed in the substrate, and the active region has a first trench; A high dielectric constant metal gate comprises a first region arranged in the first groove and a second region higher than the surface of the substrate, the high dielectric constant metal gate comprises a high dielectric constant dielectric layer and a conductive layer, the high dielectric constant dielectric layer is arranged in the first region and located on the sidewall of the first groove, the conductive layer is located in the first region and the second region, and in the first region, the conductive layer covers the high dielectric constant dielectric layer and fills the first groove; in a direction perpendicular to the surface of the substrate, the surface of the high dielectric constant dielectric layer is flush with the surface of the substrate, or is lower than the surface of the substrate.

11. The semiconductor structure according to claim 10, It is characterized in that When the surface of the high dielectric constant dielectric layer is flush with the surface of the substrate, the conductive layer located in the second region also covers the surface of the high dielectric constant dielectric layer; when the surface of the high dielectric constant dielectric layer is lower than the surface of the substrate, the conductive layer located in the first region also covers the surface of the high dielectric constant dielectric layer.

12. The semiconductor structure according to claim 10 or 11, It is characterized in that The conductive layer includes a polysilicon layer, a metal barrier layer, a metal layer and an insulating cap layer, the polysilicon layer is located in the first region and the second region, and in the first region, the polysilicon layer covers the high dielectric constant dielectric layer and fills the first trench, the metal barrier layer is located in the second region and covers the polysilicon layer, the metal layer is located in the second region and covers the metal barrier layer, and the insulating cap layer is located in the second region and covers the metal layer.

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