BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integration method based on standard bipolar device

Abstract

The invention discloses a BiCMOS (Bipolar Complementary Metal-Oxide-Semiconductor Transistor) integration method based on a standard bipolar device. The method comprises the following steps of: 1) forming A buried layer regions and a plurality of isolation regions on a substrate; and 2) forming a field region. And 3) forming a first base region and a second base region. And 4) etching the first gate oxide layer by using the mask pattern, and oxidizing and growing a second gate oxide layer and a third gate oxide layer again to form thick and thin gate oxides. And 5) forming gate oxide polycrystal of the MOS tube. And 6) forming a first emitter region, a first base electrode heavy contact region, a first CMOS source-drain region and a second DMOS source-drain region. And 7) forming a second emitter region, a second base electrode heavy contact, a second CMOS source-drain region and a third DMOS source-drain region. And 8) forming a first dielectric layer. And 9) etching the CT hole by using the mask. And carrying out metal deposition, and etching a metal end by using the mask pattern to form BJT, CMOS and DMOS devices. Under the condition that a photoetching layer is not added, the complementary bipolar process is realized, the selectable types of devices are enriched, and the application technical field with wider and higher requirements is met.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, in particular to a BiCMOS integration method based on standard bipolar devices. Background Art

[0002] Bipolar process and CMOS process are the mainstream silicon integrated circuit processes today. Bipolar process has the advantages of large driving capability and high cutoff frequency, while CMOS process has the advantages of low power consumption and high integration. BiCMOS (bipolar gate circuit and complementary metal oxide semiconductor) integrates the two processes into one set of processes, making the device performance and adaptability exceed that of a single process.

[0003] The complementary bipolar process can integrate high-performance vertical NPN tubes and vertical PNP tubes into a chip. Conventional lateral PNP tubes have low characteristic frequencies and driving capabilities, and their usage scenarios are limited. The use of vertical PNP tubes in the complementary bipolar process enables many analog integrated circuits to work normally without sacrificing key parameters, expanding the scope of application.

[0004] The current BiCMOS process is mainly based on the CMOS process. In order to achieve higher speed for MOS devices, the width of the epitaxial layer and the base region of this type of BiCMOS is limited. The breakdown and gain of the transistors produced are mostly not comparable to those produced by the standard bipolar process.

[0005] The standard bipolar process mainly includes the use of buried layers to reduce collector resistance, epitaxial growth, the use of deep N+ collector regions to increase speed and reduce saturation voltage drop, the formation of field regions through LOCOS process, and the base and emitter regions through injection and annealing to form two PN junctions of the triode. The main parameters of the triode, such as cutoff frequency and breakdown, are determined by the epitaxial thickness, and the gain is mainly determined by the base width and base doping concentration. The CMOS-based BiCMOS process cannot freely select the epitaxial thickness and base width. When it comes to analog system components that require high voltage and large gain, it is difficult to use such a process. Therefore, it is necessary to study a BiCMOS that can achieve the standard bipolar process level while maintaining the MOS function. Summary of the invention

[0006] The object of the present invention is to provide a BiCMOS integration method based on standard bipolar devices, comprising the following steps:

[0007] 1) A buried layer region and a plurality of isolation regions are formed on a substrate. The A buried layer region includes B first buried layer regions, C second buried layer regions, D third buried layer regions and E fourth buried layer regions, A=B+C+D+E. Each buried layer region includes an N-type heavily doped buried layer and a P-type heavily doped buried layer arranged on the left and right; the isolation region is a P-type heavily doped region.

[0008] 2) epitaxially and oxidatively grow a sacrificial oxide layer on the substrate including the buried layer region and the isolation region to form B first deep collector contact regions, C second deep collector contact regions and P-type WELL well regions, D first CMOS substrate well regions, E first DMOS source and drain regions and E first DMOS substrate well regions, and at the same time form multiple PN junction isolations.

[0009] 3) Perform LOCOS oxidation isolation to form a field region.

[0010] 4) Etching the sacrificial oxide layer, oxidizing and growing the first gate oxide layer, and forming the first base region and the second base region.

[0011] 5) Adjust the channels of the CMOS area and the DMOS area through mask patterns.

[0012] 6) The first gate oxide layer is etched using the mask pattern, and the second gate oxide layer and the third gate oxide layer are oxidized again to form thick and thin gate oxides.

[0013] 7) Perform polycrystalline deposition, use a mask to inject and etch to form gate polycrystalline, perform SPACER oxidation etching on the polycrystalline to form gate oxide polycrystalline of the MOS tube.

[0014] 8) Using the mask pattern and the polycrystalline gate for self-alignment, ion implantation is performed to simultaneously form a first emitter region, a first base heavy contact region, a first CMOS source and drain region, and a second DMOS source and drain region.

[0015] 9) Using the mask pattern and the polycrystalline gate for self-alignment, ion implantation is performed to simultaneously form a second emitter region, a second base heavy contact, a second CMOS source and drain region, and a third DMOS source and drain region.

[0016] 10) Forming a first dielectric layer.

[0017] 11) Use the mask to etch out the CT hole. Perform metal deposition and use the mask pattern to etch out the metal terminal to form BJT, CMOS, and DMOS devices.

[0018] Furthermore, the method of forming A buried regions and a plurality of isolation regions includes: using a mask pattern, forming them by ion implantation and annealing.

[0019] The method of forming B first deep collector contact regions, C second deep collector contact regions and P-type WELL well regions, D first CMOS substrate well regions, E first DMOS source and drain regions and E first DMOS substrate well regions includes: using a mask pattern, forming by ion implantation and annealing.

[0020] The method of forming the first base region and the second base region is: using a mask pattern, forming them by ion implantation and annealing.

[0021] Furthermore, the first buried layer region is an N-type Bipolar buried layer, the second buried layer region is a P-type Bipolar buried layer, the third buried layer region is a CMOS buried layer, and the fourth buried layer region is a DMOS buried layer.

[0022] Furthermore, the B first deep collector contact regions are of N type and are connected to the first buried layer region through a mask pattern, ion implantation, annealing or diffusion.

[0023] The C second deep collector contact regions 25 are of P type and are connected to the fourth buried layer region through ion implantation annealing via a mask pattern.

[0024] The implantation recipe conditions of the second deep collector contact region and the isolation region are consistent with the implantation recipe conditions of the isolation region.

[0025] The conditions for P-type WELL injection and NMOS well region injection are the same.

[0026] When the MOS types are consistent, the injection menu conditions of the first DMOS source and drain regions and the first DMOS substrate well region are the same.

[0027] Furthermore, the D first CMOS substrate well regions, E first DMOS source and drain regions, E first DMOS substrate well regions and P-type WELL well regions are formed by mask pattern ion implantation annealing, and the implanted ion type is related to the device type.

[0028] If the BiCMOS device is an N-type CMOS, the doping type of the first CMOS substrate well region is a P-type.

[0029] If the BiCMOS device is a P-type CMOS, the doping type of the first CMOS substrate well region is N-type.

[0030] The doping energy injected into the well region of the first CMOS substrate is determined according to the thickness of the epitaxial layer, and the doping depth after annealing is 70% of the thickness of the epitaxial layer.

[0031] Furthermore, the isolation region is doped with high concentration BORON.

[0032] To prevent the parasitic PNP tube from punching through and improve breakdown, the minimum distance between the isolation region and the first deep collector contact region is 1.2 times the epitaxial thickness, and the minimum distance between the isolation region and the second deep collector contact region is 1.5 times the epitaxial thickness.

[0033] Further, the thickness range of the first gate oxide layer is between the thickness of the second gate oxide layer and the thickness of the third gate oxide layer. The second gate oxide layer is a thin gate oxide region, and the thickness is determined according to the CMOS gate breakdown, and the third gate oxide layer is a thick gate oxide region. The second gate oxide layer includes a CMOS region and a low threshold DMOS device region, and the third gate oxide layer includes a region other than the region included in the second gate oxide layer.

[0034] Further, the first emitter region is an N-type Bipolar emitter region, the first base heavy contact region is a P-type Bipolar base heavy contact region, the first CMOS source and drain region is an N-type CMOS source and drain region, and the second DMOS source and drain region is an N-type DMOS source and drain region. The first emitter region, the first base heavy contact region, the first CMOS source and drain region, and the second DMOS source and drain region are formed simultaneously by arsenic ion implantation and annealing.

[0035] Further, the second emitter region is a P-type Bipolar emitter region, the second base heavy contact region is an N-type Bipolar base heavy contact region, the second CMOS source and drain region is a P-type CMOS source and drain region, and the third DMOS source and drain region is a P-type DMOS source and drain region.

[0036] The second emitter region, the second base heavy contact region, the second CMOS source and drain region, and the third DMOS source and drain region are all formed simultaneously by injecting BF2 and annealing.

[0037] Furthermore, when the BiCMOS device is a VPNP high breakdown device, a P-type WELL well region in the MOS region is formed by doping and implantation, and the P-type WELL well region is connected to the fourth buried layer region.

[0038] When the BiCMOS device is used as a VPNP high-speed device, a P-type WELL well region of the MOS region is formed by undoped annealing implantation, and the P-type WELL well region is not connected to the fourth buried layer region.

[0039] The technical effect of the present invention is undoubted, and the beneficial effects of the present invention are as follows:

[0040] Without adding photolithography layers, a complementary bipolar process is realized. By using N-type MOS well injection and P-type buried layer flipping, the VPNP device is changed from the original N-type epitaxy to P-type epitaxy, which improves the gain of the VPNP tube. Optionally, if the high-voltage standard bipolar device requirements are to be met, the PWELL layer can be deleted in the layout to widen the VPNP base width. In this way, high-voltage and high-speed VPNP devices can be made in the same process without increasing the process budget.

[0041] The present invention uses BF2 for ion doping when forming a P-type Bipolar emitter region and an N-type Bipolar base. The diffusion depth of BF2 is slower than that of Boron injection. The use of BF2 can better control the emitter junction depth of VPNP and the lateral diffusion of the source and drain regions of P-type MOS. The present invention is different from the traditional BiCMOS. The NPN emitter region and the heavily doped base region are completed by one annealing. In the present invention, N-type annealing is first performed to complete the N-type doping diffusion of the Bipolar region and the MOS region, and then P-type annealing is performed to complete the N-type doping diffusion of the Bipolar region and the MOS region. By using BF2 for ion doping and segmented annealing, the VPNP gain is controlled and the short channel effect is avoided.

[0042] The present invention adopts a scheme of first growing a first gate oxide layer as a sacrificial oxide layer for base region injection, then selectively etching the first gate oxide layer through a mask pattern, and then oxidizing to generate thick and thin gate oxides. The advantage of this scheme is that the thickness of the first gate oxide layer can be very close to the thickness of the sacrificial oxide layer in the standard bipolar process, thereby improving the quality of the electron channel during base region injection under the traditional BiCMOS, and being closer to the base region injection situation during the standard bipolar process.

[0043] In summary, the manufacturing method of the present invention can produce high-performance high-voltage VPNP transistors and high-speed VPNP transistors without increasing the cost on the basis of traditional BICMOS, and can manufacture a set of Bipolar devices to match the Bicmos process integration technology of standard bipolar devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a schematic diagram of the steps of the BiCMOS integration method based on standard bipolar devices.

[0045] Figure 2-Figure 11 It is a process flow chart of the BiCMOS integration method based on standard bipolar devices.

[0046] Figure 12-13 This is an actual parameter diagram of the device manufactured based on the BiCMOS integration method of standard bipolar devices.

[0047] Description of Figure Numbers:

[0048] 10——first buried region, 11——second buried region, 12——isolation region, 13——third isolation region, 14——fourth buried region, 20——first deep collector contact region, 21——isolation region, 22——first CMOS substrate well region, 23——first DMOS source and drain region, 24——first DMOS substrate well region, 25——second deep collector contact region, 26——P-type WELL region, 30——LOCOS oxidation isolation, 40——first base region, 41——second base region, 50——first gate oxide layer, 51——MOS trench adjustment, 60——second gate oxide layer, 61——third gate oxide layer, 70——gate oxide polycrystalline, 80——first emitter region, 81——second base heavy contact region, 82——CMOS source and drain region, 83——DMOS source and drain region, 84——first base heavy contact region, 85——second emitter region, 91——metal port. DETAILED DESCRIPTION

[0049] The present invention is further described below in conjunction with the embodiments, but it should not be understood that the above subject matter of the present invention is limited to the following embodiments. Without departing from the above technical ideas of the present invention, various substitutions and changes are made according to the common technical knowledge and customary means in the art, which should all be included in the protection scope of the present invention.

[0050] Embodiment 1:

[0051] See also Figures 1 to 13 , a BiCMOS integration method based on standard bipolar devices, comprising the following steps:

[0052] 1) A buried layer region and a plurality of isolation regions 12 are formed on a substrate. The A buried layer region includes B first buried layer regions 10, C second buried layer regions 11, D third buried layer regions 13 and E fourth buried layer regions 14, A=B+C+D+E. Each buried layer region includes an N-type heavily doped buried layer and a P-type heavily doped buried layer arranged on the left and right. The isolation region 12 is a P-type heavily doped region.

[0053] 2) A sacrificial oxide layer is grown epitaxially and oxidized on the substrate including the buried layer region and the isolation region 12 to form B first deep collector contact regions 20, C second deep collector contact regions 25 and P-type WELL well regions 26, D first CMOS substrate well regions 22, E first DMOS source and drain regions 23 and E first DMOS substrate well regions 24, and a plurality of PN junction isolations are formed at the same time.

[0054] 3) Perform LOCOS oxidation isolation 30 to form a field region.

[0055] 4) Etching the sacrificial oxide layer, oxidizing and growing the first gate oxide layer 50 , and forming the first base region 40 and the second base region 41 .

[0056] 5) The channels of the CMOS region and the DMOS region are adjusted 51 through the mask pattern.

[0057] 6) The first gate oxide layer 50 is etched using the mask pattern, and the second gate oxide layer 60 and the third gate oxide layer 61 are oxidized and grown again to form thick and thin gate oxides.

[0058] 7) Perform polycrystalline deposition, use a mask to implant and etch to form gate polycrystalline, perform SPACER oxidation etching on the polycrystalline to form gate oxide polycrystalline 70 of the MOS tube.

[0059] 8) Using the mask pattern and the polycrystalline gate self-alignment, ion implantation is performed to simultaneously form the first emitter region 80, the first base heavy contact region 84, the first CMOS source and drain region 82, and the second DMOS source and drain region 83.

[0060] 9) Using the mask pattern and the polycrystalline gate self-alignment, ion implantation is performed to simultaneously form the second emitter region 85, the second base heavy contact 81, the second CMOS source and drain region 82, and the third DMOS source and drain region 83.

[0061] 10) Forming a first dielectric layer.

[0062] 11) Use the mask to etch out the CT hole. Perform metal deposition and use the mask pattern to etch out the metal terminal 91 to form BJT, CMOS, and DMOS devices.

[0063] The method of forming A buried layer regions and a plurality of isolation regions includes: using a mask pattern, forming by ion implantation and annealing.

[0064] The method of forming B first deep collector contact regions 20, C second deep collector contact regions 25 and P-type WELL well regions 26, D first CMOS substrate well regions 22, E first DMOS source and drain regions 23 and E first DMOS substrate well regions 24 includes: using a mask pattern, forming by ion implantation and annealing.

[0065] The method of forming the first base region 40 and the second base region 41 is: using a mask pattern, ion implantation and annealing.

[0066] The first buried layer region is an N-type Bipolar buried layer, the second buried layer region is a P-type Bipolar buried layer, the third buried layer region is a CMOS buried layer, and the fourth buried layer region is a DMOS buried layer.

[0067] The B first deep collector contact regions are N-type and are connected to the first buried layer region through a mask pattern, ion implantation, annealing or diffusion.

[0068] The C second deep collector contact regions 25 are of P type and are connected to the fourth buried layer region through ion implantation annealing via a mask pattern.

[0069] The implantation recipe conditions of the second deep collector contact region and the isolation region are consistent with the implantation recipe conditions of the isolation region.

[0070] The conditions for P-type WELL injection and NMOS well region injection are the same.

[0071] When the MOS types are consistent, the injection menu conditions of the first DMOS source and drain regions and the first DMOS substrate well region are the same.

[0072] The D first CMOS substrate well regions, E first DMOS source and drain regions, E first DMOS substrate well regions and P-type WELL well regions are formed by mask pattern ion implantation annealing, and the implanted ion type is related to the device type.

[0073] If the BiCMOS device is an N-type CMOS, the doping type of the first CMOS substrate well region is a P-type.

[0074] If the BiCMOS device is a P-type CMOS, the doping type of the first CMOS substrate well region is N-type.

[0075] The doping energy injected into the well region of the first CMOS substrate is determined according to the thickness of the epitaxial layer, and the doping depth after annealing is 70% of the thickness of the epitaxial layer.

[0076] The isolation region is doped with high concentration of BORON.

[0077] To prevent the parasitic PNP tube from punching through and improve breakdown, the minimum distance between the isolation region and the first deep collector contact region is 1.2 times the epitaxial thickness, and the minimum distance between the isolation region and the second deep collector contact region is 1.5 times the epitaxial thickness.

[0078] The thickness range of the first gate oxide layer is between the thickness of the second gate oxide layer and the thickness of the third gate oxide layer. The second gate oxide layer is a thin gate oxide region, and the thickness is determined according to the CMOS gate breakdown, and the third gate oxide layer is a thick gate oxide region. The second gate oxide layer includes a CMOS region and a low threshold DMOS device region, and the third gate oxide layer includes a region other than the region included in the second gate oxide layer.

[0079] The first emitter region is an N-type Bipolar emitter region, the first base heavy contact region is a P-type Bipolar base heavy contact region, the first CMOS source and drain region is an N-type CMOS source and drain region, and the second DMOS source and drain region is an N-type DMOS source and drain region. The first emitter region, the first base heavy contact region, the first CMOS source and drain region, and the second DMOS source and drain region are formed simultaneously by arsenic ion implantation and annealing.

[0080] The second emitter region is a P-type Bipolar emitter region, the second base heavy contact region is an N-type Bipolar base heavy contact region, the second CMOS source and drain region is a P-type CMOS source and drain region, and the third DMOS source and drain region is a P-type DMOS source and drain region.

[0081] The second emitter region, the second base heavy contact region, the second CMOS source and drain region, and the third DMOS source and drain region are all formed simultaneously by injecting BF2 and annealing.

[0082] When the BiCMOS device is a VPNP high breakdown device, the P-type WELL well region 26 of the MOS region is formed by doping and implantation, and the P-type WELL well region 26 is connected to the fourth buried layer region 14 .

[0083] When the BiCMOS device is used as a VPNP high-speed device, a P-type WELL well region 26 of the MOS region is formed by undoped annealing implantation, and the P-type WELL well region 26 is not connected to the fourth buried layer region 14 .

[0084] Embodiment 2:

[0085] A BiCMOS integration method based on standard bipolar devices comprises the following steps:

[0086] A buried layer region and a plurality of isolation regions 12 are formed on a substrate. The A buried layer region includes B first buried layer regions 10, C second buried layer regions 11, D third buried layer regions 13 and E fourth buried layer regions 14, A=B+C+D+E. Each buried layer region includes an N-type heavily doped buried layer and a P-type heavily doped buried layer. The isolation region 12 is a P-type heavily doped region.

[0087] A sacrificial oxide layer is grown epitaxially and oxidized on the substrate including the buried layer region and the isolation region 12 to form B first deep collector contact regions 20, C second deep collector contact regions 25 and P-type WELL well regions 26, D first CMOS substrate well regions 22, E first DMOS source and drain regions 23 and E first DMOS substrate well regions 24, and a plurality of PN junction isolations are formed at the same time.

[0088] 3 Perform LOCOS oxidation isolation 30 to form a field region.

[0089] 4. The sacrificial oxide layer is etched, and the first gate oxide layer 50 is grown by oxidation to form the first base region 40 and the second base region 41.

[0090] 5 The channels of the CMOS region and the DMOS region are adjusted 51 through the mask pattern.

[0091] 6 The first gate oxide layer 50 is etched using the mask pattern, and the second gate oxide layer 60 and the third gate oxide layer 61 are oxidized again to form thick and thin gate oxides.

[0092] 7 performs polycrystalline deposition, uses a mask to implant and etch to form gate polycrystalline, performs SPACER oxidation etching on the polycrystalline to form gate oxide polycrystalline 70 of the MOS tube.

[0093] 8 ion implantation is performed by using the mask pattern and the polycrystalline gate self-alignment to simultaneously form the first emitter region 80, the first base heavy contact region 84, the first CMOS source and drain region 82, and the second DMOS source and drain region 83.

[0094] 9 ion implantation is performed by using the mask pattern and the polycrystalline gate self-alignment to simultaneously form the second emitter region 85, the second base heavy contact 81, the second CMOS source and drain region 82, and the third DMOS source and drain region 83.

[0095] 10. Forming a first dielectric layer.

[0096] 11) Use the mask to etch out the CT hole. Perform metal deposition and use the mask pattern to etch out the metal terminal 91 to form BJT, CMOS, and DMOS devices.

[0097] Embodiment 3:

[0098] A BiCMOS integration method based on a standard bipolar device, the technical content is the same as that of Example 2, and further, a method for forming A buried layer regions and a plurality of isolation regions includes: using a mask pattern, forming by ion implantation and annealing.

[0099] The method of forming B first deep collector contact regions 20, C second deep collector contact regions 25 and P-type WELL well regions 26, D first CMOS substrate well regions 22, E first DMOS source and drain regions 23 and E first DMOS substrate well regions 24 includes: using a mask pattern, forming by ion implantation and annealing.

[0100] The method of forming the first base region 40 and the second base region 41 is: using a mask pattern, ion implantation and annealing.

[0101] Embodiment 4:

[0102] A BiCMOS integration method based on standard bipolar devices, the technical content of which is the same as any one of Examples 2-3, further, the first buried layer region is an N-type Bipolar buried layer, the second buried layer region is a P-type Bipolar buried layer, the third buried layer region is a CMOS buried layer, and the fourth buried layer region is a DMOS buried layer.

[0103] Embodiment 5:

[0104] A BiCMOS integration method based on standard bipolar devices, the technical content of which is the same as any one of embodiments 2-4, further, the B first deep collector contact regions are N-type, and are connected to the first buried layer region through a mask pattern, ion implantation annealing or diffusion.

[0105] The C second deep collector contact regions 25 are of P type and are connected to the fourth buried layer region through ion implantation annealing via a mask pattern.

[0106] The implantation recipe conditions of the second deep collector contact region and the isolation region are consistent with the implantation recipe conditions of the isolation region.

[0107] The conditions for P-type WELL injection and NMOS well region injection are the same.

[0108] When the MOS types are consistent, the injection menu conditions of the first DMOS source and drain regions and the first DMOS substrate well region are the same.

[0109] Embodiment 6:

[0110] A BiCMOS integration method based on standard bipolar devices, the technical content of which is the same as any one of Examples 2-5, further, the D first CMOS substrate well regions, E first DMOS source and drain regions and E first DMOS substrate well regions and P-type WELL well regions are formed by mask pattern ion implantation annealing, and the implanted ion type is related to the device type.

[0111] If the BiCMOS device is an N-type CMOS, the doping type of the first CMOS substrate well region is a P-type.

[0112] If the BiCMOS device is a P-type CMOS, the doping type of the first CMOS substrate well region is N-type.

[0113] The doping energy injected into the well region of the first CMOS substrate is determined according to the thickness of the epitaxial layer, and the doping depth after annealing is 70% of the thickness of the epitaxial layer.

[0114] Embodiment 7:

[0115] A BiCMOS integration method based on standard bipolar devices, the technical content of which is the same as any one of Embodiments 2-6, and further, the isolation region is doped with high concentration BORON.

[0116] To prevent the parasitic PNP tube from punching through and improve breakdown, the minimum distance between the isolation region and the first deep collector contact region is 1.2 times the epitaxial thickness, and the minimum distance between the isolation region and the second deep collector contact region is 1.5 times the epitaxial thickness.

[0117] Embodiment 8:

[0118] A BiCMOS integration method based on a standard bipolar device, the technical content is the same as any one of embodiments 2-7, further, the thickness range of the first gate oxide layer is between the thickness of the second gate oxide layer and the thickness of the third gate oxide layer. The second gate oxide layer is a thin gate oxide region, the thickness of which is determined according to the breakdown of the CMOS gate, and the third gate oxide layer is a thick gate oxide region. The second gate oxide layer includes a CMOS region and a low threshold DMOS device region, and the third gate oxide layer includes a region other than the region included in the second gate oxide layer.

[0119] Embodiment 9:

[0120] A BiCMOS integration method based on a standard bipolar device, the technical content is the same as any one of embodiments 2-8, further, the first emitter region is an N-type Bipolar emitter region, the first base heavy contact region is a P-type Bipolar base heavy contact region, the first CMOS source and drain region is an N-type CMOS source and drain region, and the second DMOS source and drain region is an N-type DMOS source and drain region. The first emitter region, the first base heavy contact region, the first CMOS source and drain region, and the second DMOS source and drain region are formed simultaneously by arsenic ion implantation annealing.

[0121] Embodiment 10:

[0122] A BiCMOS integration method based on standard bipolar devices, the technical content of which is the same as any one of Examples 2-9, further, the second emitter region is a P-type Bipolar emitter region, the second base heavy contact region is an N-type Bipolar base heavy contact region, the second CMOS source and drain region is a P-type CMOS source and drain region, and the third DMOS source and drain region is a P-type DMOS source and drain region.

[0123] The second emitter region, the second base heavy contact region, the second CMOS source and drain region, and the third DMOS source and drain region are all formed simultaneously by injecting BF2 and annealing.

[0124] Embodiment 11:

[0125] A BiCMOS integration method based on a standard bipolar device, the technical content of which is the same as any one of Examples 2-10. Furthermore, when the BiCMOS device is a VPNP high breakdown device, a P-type WELL well region 26 in the MOS region is formed by doping injection, and the P-type WELL well region 26 is connected to the fourth buried layer region 14.

[0126] When the BiCMOS device is used as a VPNP high-speed device, a P-type WELL well region 26 of the MOS region is formed by undoped annealing implantation, and the P-type WELL well region 26 is not connected to the fourth buried layer region 14 .

[0127] Embodiment 12:

[0128] A BiCMOS integration method based on standard bipolar devices, comprising the following steps:

[0129] 1) If Figure 2 As shown, a P-type silicon substrate is provided, and a mask pattern is used to perform ion implantation and annealing to form A buried layer regions and multiple isolation regions. The A buried layer regions include B first buried layer regions 10, C second buried layer regions 11, D third buried layer regions 12, and E fourth buried layer regions 14, where A=B+C+D+E. The buried layer regions include N-type heavily doped buried layers and P-type heavily doped buried layers, and the isolation region 12 is P-type heavily doped.

[0130] 2) If Figure 3 As shown, epitaxial and oxidative growth of a sacrificial oxide layer is performed on a substrate including a buried layer and isolation. Using a mask pattern, ion implantation and annealing are performed to form B first deep collector contact regions 20, C second deep collector contact regions 25 and P-type WELL well regions 26, D first CMOS substrate well regions 22, E first DMOS source and drain regions 23 and E first DMOS substrate well regions 24, and multiple PN junction isolations are formed at the same time, and the injection menu conditions of the second deep collector contact region 2 and the isolation region 21 are consistent. Optionally, the P-type WELL injection and the well region injection conditions of the NMOS region are the same. According to the required P-type Bipolar requirements, the VPNP can be made to achieve high breakdown or high speed VPNP by adding or not adding PWELL doping in the MOS region. When PWELL doping is used, its PWELL should be connected to the upturned fourth buried layer region, Figure 3 The high-speed VPNP tube is shown;

[0131] 3) If Figure 4 As shown, LOCOS oxidation isolation 30 is performed to form a field region;

[0132] 4) If Figure 5 As shown, the sacrificial oxide layer is etched, and the first gate oxide layer 50 is grown by oxidation. Ion implantation is performed using a mask pattern and annealing is performed to form a first base region 40 and a second base region 41;

[0133] 5) If Figure 6 As shown, the channels of the CMOS region and the DMOS region are adjusted 51 through a mask pattern;

[0134] 6) If Figure 7 As shown, the first gate oxide layer is etched using a mask pattern, and then the second gate oxide layer 60 and the third gate oxide layer 61 are oxidized and grown again to form thick and thin gate oxides;

[0135] 7) If Figure 8 As shown, polycrystalline deposition is performed, a mask is used to implant and etch to form gate polycrystalline, and SPACER oxidation etching is performed on the polycrystalline to form gate oxide polycrystalline 70 of the MOS tube;

[0136] 8) If Fig. 9 As shown, ion implantation is performed by using a mask pattern and polycrystalline gate self-alignment to simultaneously form a first emitter region 80, a first base heavy contact region 84, a first CMOS source and drain region 82, and a second DMOS source and drain region 83;

[0137] 9) If Fig. 9 As shown, the mask pattern and the polycrystalline gate are used for self-alignment to perform ion implantation to simultaneously form the second emitter region 85, the second base heavy contact 81, the second CMOS source and drain region 82, and the third DMOS source and drain region 83;

[0138] 10) Fig.10 As shown, a first dielectric layer is formed;

[0139] 11) If Fig.11 CT holes are etched out using a mask plate; metal deposition is performed, and a metal terminal 91 is etched out using a mask pattern to form a BJT, CMOS, or DMOS device;

[0140] Embodiment 13:

[0141] The manufacturing method of BiCMOS based on standard bipolar devices has the same technical content as Example 12. Furthermore, the first buried layer area is an N-type Bipolar buried layer, the second buried layer area is a P-type Bipolar buried layer, the third buried layer area is a CMOS buried layer, and the fourth buried layer area is a DMOS buried layer. The type of the buried layer in the MOS area is determined according to the type of MOS. If it is PMOS, the buried layer type is N-type.

[0142] Embodiment 14:

[0143] A method for manufacturing BiCMOS based on a standard bipolar device, the technical content is the same as any one of embodiments 12-13, further, the B first deep collector contact regions are N-type, connected to the first buried layer region through a mask pattern through ion implantation annealing or diffusion, the C second deep collector contact regions 25 are P-type, connected to the fourth buried layer region through a mask pattern through ion implantation annealing, and the injection menu conditions of the second deep collector contact region and the isolation region are consistent with the injection menu conditions of the isolation region;

[0144] Embodiment 15:

[0145] The manufacturing method of BiCMOS based on standard bipolar devices has the same technical content as any one of Examples 12-14. Furthermore, the D first CMOS substrate well regions, E first DMOS source and drain regions, E first DMOS substrate well regions and P-type WELL well regions are formed by mask pattern ion implantation annealing, and the implanted ion type is related to the device type itself. If it is N-type CMOS, the doping type of the first CMOS substrate well region is P-type. The doping energy of the well region is determined according to the epitaxial thickness. The doping depth after annealing is 70% of the epitaxial layer thickness. The P-type WELL implantation and the well region implantation menu of the NMOS region are the same. The first CMOS substrate well region, the first DMOS source and drain region, and the first DMOS substrate well region have the same implantation menu of N-type implantation and P-type implantation. When the above three well regions are implanted in the same MOS type (such as N-type CMOS and N-type DMOS), the implantation menu conditions are consistent.

[0146] Embodiment 16:

[0147] A method for manufacturing BiCMOS based on a standard bipolar device, the technical content is the same as any one of embodiments 12-15, further, the present invention uses PN junction isolation, and its isolation region is doped with high concentration BORON. To prevent the parasitic PNP tube from punching through and improve the breakdown, the minimum distance between the isolation region and the first deep collector contact region should be 1.2 times the epitaxial thickness, and the minimum distance between the isolation region and the second deep collector contact region should be 1.5 times the epitaxial thickness;

[0148] Embodiment 17:

[0149] A manufacturing method of BiCMOS based on a standard bipolar device, the technical content is the same as any one of embodiments 12-16, further, by selectively etching the thick and thin gate oxides grown through a mask pattern, the DMOS device can select the gate oxide thickness to produce a high and low threshold DMOS device, the first gate oxide layer thickness range is between the second gate oxide layer thickness and the third gate oxide layer thickness, and the specific thickness is determined by the second gate oxide layer thickness; the second gate oxide layer is a thin gate oxide region, the specific thickness is determined according to the CMOS gate breakdown, and the third gate oxide layer is a thick gate oxide region; the second gate oxide layer includes a CMOS region and a low threshold DMOS device region, and the third gate oxide layer includes a region other than the region included in the second gate oxide layer;

[0150] Embodiment 18:

[0151] A method for manufacturing BiCMOS based on a standard bipolar device, the technical content is the same as any one of embodiments 12-17, further, the first emitter region is an N-type Bipolar emitter region, the first base heavy contact region is a P-type Bipolar base heavy contact region, the first CMOS source and drain region is an N-type CMOS source and drain region, the second DMOS source and drain region is an N-type DMOS source and drain region, and the above four regions are all formed simultaneously by arsenic ion implantation annealing;

[0152] Embodiment 19:

[0153] A method for manufacturing BiCMOS based on a standard bipolar device, the technical content of which is the same as any one of Embodiments 12-18, further comprising:

[0154] The second emitter region is a P-type Bipolar emitter region, the second base heavy contact region is an N-type Bipolar base heavy contact region, the second CMOS source and drain region is a P-type CMOS source and drain region, and the third DMOS source and drain region is a P-type DMOS source and drain region, and the above four regions are all formed simultaneously by injecting BF2 and annealing;

[0155] Embodiment 20:

[0156] The manufacturing method of BiCMOS based on standard bipolar devices has the same technical content as any one of Examples 12-19. Furthermore, when a high-speed VPNP device is used, in theory, except for the case where the epitaxial thickness is too thick and the PWELL cannot be connected to the fourth buried layer region, the PWELL injection in other cases can be connected to the fourth buried layer region by ordinary injection or high-energy injection. The injection conditions of the P-type WELL injection and the well region of the NMOS region are the same. According to the required P-type Bipolar requirements, the selection of VPNP high breakdown or high-speed VPNP can be achieved by using or not using PWELL doping. When using a high-speed VPNP, its PWELL should be connected to the upturned fourth buried layer region;

[0157] Embodiment 21:

[0158] The manufacturing method of BiCMOS based on standard bipolar devices can theoretically meet the needs of most standard bipolar devices. Taking the standard bipolar 40V process as an example, the standard 40V process includes 10 - the first buried layer region, 11 - the second buried layer region, 12 - the isolation region, 13 - the third buried layer region, 14 - the fourth buried region, 20 - the first deep collector contact region, 21 - the first deep collector contact region, 22 - the first CMOS substrate well region, 23 - the first DMOS source and drain region, 24 - the first DMOS substrate well region, 25 - second deep collector contact region, 26 - P-type WELL region, 30 - LOCOS oxidation isolation, 40 - first base region, 41 - second base region, 50 - first gate oxide layer, 51 - MOS channel adjustment, 60 - second gate oxide layer, 61 - third gate oxide layer, 70 - gate oxide polycrystalline, 80 - first emitter region, 81 - second base heavy contact region, 82 - CMOS source and drain region, 83 - DMOS source and drain region, 84 - first base heavy contact region, 85 - second emitter region, 91 - metal port. The steps are as follows:

[0159] Step 1: Provide a P-type silicon substrate, use a mask pattern, ion implant and anneal to form A buried layer regions and multiple isolation regions. A buried layer region includes B first buried layer regions 10, C second buried layer regions 11, D third buried layer regions 12 and E fourth buried layer regions 14, A = B + C + D + E, the buried layer region includes an N-type heavily doped buried layer and a P-type heavily doped buried layer, the isolation region 12 is a P-type heavily doped, the silicon substrate crystal orientation mentioned above should be 100 crystal orientation, its P-type heavily doped buried layer, the isolation region 12 is the same type of implantation, formed by B (boron) impurity doping, and the concentration peak is generally 10 18 cm-3~10 19 In the cm-3 range, the N-type heavily doped buried layer is formed by AS (arsenic) impurity doping, and the peak concentration is generally around 10 19 cm-3~10 20 cm-3 range;

[0160] 2) If Figure 3 As shown, epitaxy and oxidation growth of sacrificial oxide layer are performed on the substrate including buried layer and isolation. Using mask pattern, ion implantation and annealing are performed to form B first deep collector contact regions 20, C second deep collector contact regions 25 and P-type WELL well regions 26, D first CMOS substrate well regions 22, E first DMOS source and drain regions 23 and E first DMOS substrate well regions 24, and multiple PN junction isolations are formed at the same time. The epitaxy conditions mentioned above match the epitaxy conditions of 40V standard bipolar process. The concentration peaks of N-type substrate well region and P-type substrate well region in MOS region are generally 10 16 cm-3~10 17In this process, the VPNP area uses the high-speed type VPVP, and the PWELL25 is injected through the mask pattern to connect with the fourth buried layer turned up. The PWELL25 is consistent with the P-type MOS area substrate well area injection menu.

[0161] 3) If Figure 4 As shown, LOCOS oxidation isolation 30 is performed to form a field region;

[0162] 4) If Figure 5 As shown, the sacrificial oxide layer is etched, and the first gate oxide layer 50 is grown by oxidation. Ion implantation and annealing are performed using a mask pattern to form a first base region 40 and a second base region 41. The first base region 40 is implemented by Boron implantation, and the second base region 41 is implemented by PHOS implantation. The second base region 41 should be annealed first and then the first base region 40.

[0163] 5) If Figure 6 As shown, the channels in the CMOS region and the DMOS region are grooved 51 through mask patterns, and the groove concentration is determined according to the actual threshold requirements;

[0164] 6) If Figure 7 As shown, the first gate oxide layer is etched using a mask pattern, and then the second gate oxide layer 60 and the third gate oxide layer 61 are oxidized and grown again to form thick and thin gate oxides;

[0165] 7) If Figure 8 As shown, polycrystalline deposition is performed, a mask is used to fully inject and etch the gate polycrystalline to form a gate polycrystalline, and SPACER oxidation etching is performed on the polycrystalline to form a gate oxide polycrystalline 70 of the MOS tube;

[0166] 8) If Fig. 9 As shown, the mask pattern and the polycrystalline gate self-alignment are used to perform ion implantation to simultaneously form the first emitter region 80, the first base heavy contact region 84, the first CMOS source and drain region, and the second DMOS source and drain region. The above ion implantation uses AS (arsenic) ions with a peak concentration of 10 20 cm-3~10 21 Between cm-3;

[0167] 9) If Fig. 9 As shown, the mask pattern and the polycrystalline gate are used for ion implantation to form the second emitter region, the second base heavy contact region, the second CMOS source and drain region, and the third DMOS source and drain region at the same time. The above ion implantation is performed using BF2 (boron difluoride) with a peak concentration of 10 20 cm-3~10 21 Between cm-3;

[0168] 10) Fig.10As shown, a first dielectric layer is formed. Taking a standard bipolar 40V process as an example, the first dielectric layer formed is an ILD TEOS oxide layer;

[0169] 11) If Fig.11 Use the mask to etch out the CT hole; perform metal deposition, and use the mask pattern to etch out the metal terminal to form BJT, CMOS, and DMOS devices;

[0170] 12) If Fig.12 and Fig.13 As shown, the NPN output curve and NMOS threshold voltage curve finally obtained by this manufacturing process are normal, meeting the requirements of the standard 40V bipolar process.

Claims

1. A BiCMOS integration method based on standard bipolar devices, characterized in that: The following steps are involved: 1) A buried layer region and a plurality of isolation regions (12) are formed on the substrate; the A buried layer region comprises B first buried layer regions (10), C second buried layer regions (11), D third buried layer regions (13) and E fourth buried layer regions (14), A=B+C+D+E; each buried layer region comprises an N-type heavily doped buried layer and a P-type heavily doped buried layer arranged on the left and right; the isolation region (12) is a P-type heavily doped region. 2) epitaxially and oxidatively growing a sacrificial oxide layer on a substrate including a buried layer region and an isolation region (12) to form B first deep collector contact regions (20), C second deep collector contact regions (25) and a P-type WELL well region (26), D first CMOS substrate well regions (22), E first DMOS source and drain regions (23) and E first DMOS substrate well regions (24), and simultaneously forming a plurality of PN junction isolations; 3) performing LOCOS oxidation isolation (30) to form a field region; 4) etching the sacrificial oxide layer, oxidizing and growing the first gate oxide layer (50), and forming a first base region (40) and a second base region (41); 5) Adjusting the channels of the CMOS region and the DMOS region through mask patterns (51); 6) etching the first gate oxide layer (50) using the mask pattern, and then oxidizing and growing the second gate oxide layer (60) and the third gate oxide layer (61) to form thick and thin gate oxides; 7) performing polycrystalline deposition, using a mask to implant and etch to form gate polycrystalline, and performing SPACER oxidation etching on the polycrystalline to form gate oxide polycrystalline of the MOS tube (70); 8) Using the mask pattern and the polycrystalline gate self-alignment to perform ion implantation to simultaneously form a first emitter region (80), a first base heavy contact region (84), a first CMOS source and drain region (82), and a second DMOS source and drain region (83); 9) Using the mask pattern and the polycrystalline gate to self-align and perform ion implantation, a second emitter region (85), a second base heavy contact (81), a second CMOS source and drain region (82), and a third DMOS source and drain region (83) are simultaneously formed; 10) forming a first dielectric layer; 11) Using the mask plate to etch out CT holes; performing metal deposition, and using the mask pattern to etch out metal terminals (91), forming BJT, CMOS, DMOS devices.

2. A BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that: The method of forming A buried layer regions and a plurality of isolation regions comprises: using a mask pattern, forming by ion implantation and annealing; The method for forming B first deep collector contact regions (20), C second deep collector contact regions (25) and P-type WELL well regions (26), D first CMOS substrate well regions (22), E first DMOS source and drain regions (23) and E first DMOS substrate well regions (24) comprises: using a mask pattern, forming by ion implantation and annealing; The method for forming the first base region (40) and the second base region (41) is: using a mask pattern, forming them by ion implantation and annealing.

3. A BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that: The first buried layer region is an N-type Bipolar buried layer, the second buried layer region is a P-type Bipolar buried layer, the third buried layer region is a CMOS buried layer, and the fourth buried layer region is a DMOS buried layer.

4. A BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that: The B first deep collector contact regions are N-type and connected to the first buried layer region by ion implantation annealing or diffusion through a mask pattern; The C second deep collector contact regions 25 are of P type and are connected to the fourth buried layer region through ion implantation annealing via a mask pattern; The injection menu conditions of the second deep collector contact region and the isolation region are consistent with the injection menu conditions of the isolation region; The conditions for P-type WELL injection and NMOS well region injection are the same. When the MOS types are consistent, the injection menu conditions of the first DMOS source and drain regions and the first DMOS substrate well region are the same.

5. A BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that: The D first CMOS substrate well regions, E first DMOS source and drain regions, E first DMOS substrate well regions and P-type WELL well regions are formed by mask pattern ion implantation annealing, and the implanted ion type is related to the device type; If the BiCMOS device is an N-type CMOS, the doping type of the first CMOS substrate well region is a P-type; If the BiCMOS device is a P-type CMOS, the doping type of the first CMOS substrate well region is N-type; The doping energy injected into the well region of the first CMOS substrate is determined according to the thickness of the epitaxial layer, and the doping depth after annealing is 70% of the thickness of the epitaxial layer.

6. A BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that: The isolation area is doped with high concentration of BORON; To prevent the parasitic PNP tube from punching through and improve breakdown, the minimum distance between the isolation region and the first deep collector contact region is 1.2 times the epitaxial thickness, and the minimum distance between the isolation region and the second deep collector contact region is 1.5 times the epitaxial thickness.

7. A BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that: The thickness range of the first gate oxide layer is between the thickness of the second gate oxide layer and the thickness of the third gate oxide layer; the second gate oxide layer is a thin gate oxide region, and the thickness is determined according to the CMOS gate breakdown, and the third gate oxide layer is a thick gate oxide region; the second gate oxide layer includes a CMOS region and a low threshold DMOS device region, and the third gate oxide layer includes a region other than the region included in the second gate oxide layer.

8. A BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that: The first emitter region is an N-type Bipolar emitter region, the first base heavy contact region is a P-type Bipolar base heavy contact region, the first CMOS source and drain region is an N-type CMOS source and drain region, and the second DMOS source and drain region is an N-type DMOS source and drain region; the first emitter region, the first base heavy contact region, the first CMOS source and drain region, and the second DMOS source and drain region are formed simultaneously by arsenic ion implantation annealing.

9. A BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that: The second emitter region is a P-type Bipolar emitter region, the second base heavy contact region is an N-type Bipolar base heavy contact region, the second CMOS source and drain region is a P-type CMOS source and drain region, and the third DMOS source and drain region is a P-type DMOS source and drain region; The second emitter region, the second base heavy contact region, the second CMOS source and drain region, and the third DMOS source and drain region are all formed simultaneously by injecting BF2 and annealing.

10. A BiCMOS integration method based on standard bipolar devices according to claim 1, characterized in that: When the BiCMOS device is a VPNP high breakdown device, a P-type WELL well region (26) in the MOS region is formed by doping and implantation, and the P-type WELL well region (26) is connected to the fourth buried layer region (14); When the BiCMOS device is used as a VPNP high-speed device, a P-type WELL well region (26) in the MOS region is formed by an undoped annealing injection method, and the P-type WELL well region (26) is not connected to the fourth buried layer region (14).

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