Preparation method of semiconductor element with air gap

Abstract

The invention discloses a preparation method of a semiconductor element, which comprises the following steps: providing a substrate, and forming a drain electrode in the substrate; forming a top dielectric layer on the substrate, and forming an opening along the top dielectric layer to expose the drain; conformally forming a sacrificial layer in the opening; performing a first stamping etching process to partially remove the sacrificial layer, thereby forming a sacrificial segment on a sidewall of the opening and exposing the drain; forming a cell plug bottom conductive layer on the drain and surrounded by the sacrificial segment; performing a removal process to remove the sacrificial segment and form a bottom conductive layer surrounding the unit plug; forming a cell plug top sealing layer on the cell plug bottom conductive layer to seal the space, thereby forming a first air gap around the cell plug bottom conductive layer; and forming a cell plug top conductive layer on the cell plug bottom conductive layer and surrounded by the cell plug top sealing layer. The cell plug bottom conductive layer, the cell plug top conductive layer, and the cell plug top sealing layer constitute a cell plug structure.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2023110989616, filed on August 29, 2023, with the invention name of "Semiconductor element with air gap". Application No. 2023110989616 claims priority and benefits of U.S. formal application No. 18 / 207,828 filed on June 9, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a method for preparing a semiconductor element, and in particular to a method for preparing a semiconductor element with an air gap. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. In order to meet the increasingly stringent computing performance requirements, the size of semiconductor components is constantly being reduced. However, the reduction in size leads to various problems in the process, and these problems continue to derive different situations. Therefore, there are still challenges in improving quality, yield, performance and reliability, and reducing complexity.

[0004] The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] One aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, and forming a drain in the substrate; forming a top dielectric layer on the substrate, and forming an opening along the top dielectric layer to expose the drain; conformally forming a sacrificial layer in the opening; performing a first stamping etching process to partially remove the sacrificial layer, thereby forming a sacrificial segment on a side wall of the opening and exposing the drain; forming a cell plug bottom conductive layer on the drain and surrounded by the sacrificial segment; performing a removal process to remove the sacrificial segment and form a cell plug bottom conductive layer; forming a cell plug top sealing layer on the cell plug bottom conductive layer to seal the space, thereby forming a first air gap around the cell plug bottom conductive layer; and forming a cell plug top conductive layer on the cell plug bottom conductive layer and surrounded by the cell plug top sealing layer. The cell plug bottom conductive layer, the cell plug top conductive layer and the cell plug top sealing layer constitute a cell plug structure.

[0006] Due to the design of the semiconductor element disclosed herein, the first air gap can be used to reduce the parasitic capacitance between the conductive features. This reduction in parasitic capacitance promotes improved performance of the semiconductor element. In addition, the parasitic capacitance can be further reduced by incorporating the second air gap. Therefore, the performance of the semiconductor element can be further improved.

[0007] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] A more complete understanding of the disclosure of the present application may be obtained by referring to the embodiments and claims in conjunction with the drawings, in which the same reference numerals refer to the same elements.

[0009] Figure 1 is a flow chart illustrating a method for preparing a semiconductor element according to an embodiment of the present disclosure;

[0010] Figure 2 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0011] Figure 3 is a cross-sectional view, showing Figure 2 The cross-sectional structure intercepted by the A-A' and B-B' line segments;

[0012] Figure 4 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0013] Figure 5 is a cross-sectional view, showing Figure 4 The cross-sectional structure intercepted by the A-A' and B-B' line segments;

[0014] Figure 6 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0015] Figure 7 is a cross-sectional view, showing Figure 6 The cross-sectional structure intercepted by the A-A' and B-B' line segments;

[0016] Figure 8 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0017] Fig. 9 is a cross-sectional view, showing Figure 8 The cross-sectional structure intercepted by the A-A' and B-B' line segments;

[0018] Fig.10 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0019] Fig.11 is a cross-sectional view, showing Fig.10 The cross-sectional structure taken by the A-A' and B-B' line segments;

[0020] Fig.12 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0021] Fig.13 and Fig.14 is a cross-sectional view, showing Fig.12 The cross-sectional structure taken along the line segments AA' and BB' in the figure is used to represent a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0022] Fig.15 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0023] Fig.16 and Fig.17 is a cross-sectional view, showing Fig.15 The cross-sectional structure taken along the line AA' and the line BB' in the figure is used to represent a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0024] Fig.18 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0025] Fig.19 and Fig. 20 is a cross-sectional view, showing Fig.18 The cross-sectional structure taken along the line AA' and the line BB' in the figure is used to represent a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0026] Fig.21 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0027] Fig. 22 and Fig.23 is a cross-sectional view, showing Fig.21 The cross-sectional structure taken along the line AA' and the line BB' in the figure is used to represent a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0028] Fig.24 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0029] Fig.25 is a cross-sectional view, showing Fig.24 The cross-sectional structure intercepted by the A-A' and B-B' line segments;

[0030] Fig.26 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0031] Fig. 27 and Fig.28 is a cross-sectional view, showing Fig.26 The cross-sectional structure taken along the line AA' and the line BB' in the figure is used to represent a partial process of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0032] Fig.29 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0033] Fig.30 is a cross-sectional view, showing Fig.30 The cross-sectional structure intercepted by the A-A' and B-B' line segments;

[0034] Fig.31 is a top view illustrating a middle semiconductor element according to an embodiment of the present disclosure;

[0035] Fig.32 is a cross-sectional view, showing Fig.31 The cross-sectional structure taken by the A-A' and B-B' line segments;

[0036] Figure 33 to Figure 36 is a cross-sectional view illustrating a partial process of manufacturing a semiconductor device according to another embodiment of the present disclosure; and

[0037] Figures 37 to 41 The cross-sectional view illustrates a partial process of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0038] The reference numerals are described as follows:

[0039] 1A: Semiconductor components

[0040] 1B: Semiconductor components

[0041] 1C: Semiconductor components

[0042] 10: Preparation method

[0043] 101: Base

[0044] 103: Isolation layer

[0045] 105: Bottom dielectric layer

[0046] 105TS: Top

[0047] 107: Top dielectric layer

[0048] 107O: Opening

[0049] 107B: Bottom

[0050] 107SW: Sidewall

[0051] 107TS: Top

[0052] 200: Character line structure

[0053] 201: word line dielectric layer

[0054] 203: word line conductive layer

[0055] 205: Character line overlay

[0056] 300: Bit line structure

[0057] 300SW: Sidewall

[0058] 301: Bit line bottom conductive layer

[0059] 301TS: Top surface

[0060] 303: Bit line middle conductive layer

[0061] 305: Bit line top conductive layer

[0062] 305BS: bottom surface

[0063] 305TS: Top surface

[0064] 307: Bit line cover

[0065] 311: First bit line spacer

[0066] 313: Second bit line spacer

[0067] 315: Third bit line spacer

[0068] 317: Padding layer

[0069] 317SW: Sidewall

[0070] 321: Bit line plug

[0071] 400: Unit plug structure

[0072] 401: Cell plug bottom conductive layer

[0073] 401TS: Top

[0074] 403: Cell plug top conductive layer

[0075] 405: Unit plug top seal layer

[0076] 501: First air gap

[0077] 503: Second air gap

[0078] 601: first conductive material

[0079] 603: Second conductive material

[0080] 605: The third conductive material

[0081] 607: The fourth conductive material

[0082] 609: Sacrificial layer

[0083] 609S: Sacrificial segment

[0084] 611: Sacrificial spacer

[0085] 613: Sealing material

[0086] 613BS: Bottom

[0087] 617: Spacer material

[0088] 701: First mask

[0089] AA: Active Area

[0090] CS: Common Source

[0091] DR: Drain

[0092] S11: Steps

[0093] S13: Steps

[0094] S15: Steps

[0095] S17: Steps

[0096] SP: Space

[0097] T1: Thickness

[0098] T2: Thickness

[0099] VL1: Vertical Level

[0100] W1: Width

[0101] W2: Width

[0102] W3: Width

[0103] W4: Width

[0104] W5: Width

[0105] WR: Well Region

[0106] X: Direction

[0107] Y: direction

[0108] Z: Direction DETAILED DESCRIPTION

[0109] The following description of the present disclosure is accompanied by the drawings which are incorporated into and constitute a part of the specification, and illustrate embodiments of the present disclosure, but the present disclosure is not limited to the embodiments. In addition, the following embodiments can be appropriately integrated to complete another embodiment.

[0110] "One embodiment", "an embodiment", "an exemplary embodiment", "another embodiment", "another embodiment", etc. mean that the embodiment described in the present disclosure may include specific features, structures or characteristics, but not every embodiment must include the specific features, structures or characteristics. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but it can be the same embodiment.

[0111] In order to make the present disclosure fully understood, the following description provides detailed steps and structures. Obviously, the implementation of the present disclosure will not be limited to the specific details known to those skilled in the art. In addition, the known structures and steps are no longer described in detail to avoid unnecessarily limiting the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to the detailed description, the present disclosure can also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the content of the detailed description, but is defined by the claims.

[0112] In the present disclosure, a semiconductor element generally refers to a device that can function by utilizing semiconductor characteristics, and electro-optical devices, light-emitting display devices, semiconductor circuits, and electronic devices all fall within the category of semiconductor elements.

[0113] It should be noted that, in the description of the present invention, the upper side (or up) corresponds to the direction of the arrow in the Z direction, and the lower side (or down) corresponds to the opposite direction of the arrow in the Z direction.

[0114] It should be noted that the term "formation" refers to any method of creating, establishing, patterning, implanting or depositing an element, a dopant or a material, including, but not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, crystal growth, implantation, lithography, dry etching and wet etching.

[0115] It should be noted that in the description of the present disclosure, the functions or steps mentioned herein may appear in a different order than the order marked in the drawings. For example, depending on the functions or steps involved, two consecutively displayed diagrams may actually be executed substantially simultaneously or may sometimes be executed in the opposite order.

[0116] Figure 1 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figure 2 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 is a cross-sectional view, showing Figure 2 The cross-sectional structure taken along the A-A' and B-B' line segments. Figure 4 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 5 is a cross-sectional view, showing Figure 4 The cross-sectional structure taken along the A-A' and B-B' line segments. Figure 6 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 7 is a cross-sectional view, showing Figure 6 The cross-sectional structure taken along the A-A' and B-B' line segments. Figure 8 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig. 9 is a cross-sectional view, showing Figure 8 The cross-sectional structure taken along the A-A' and B-B' line segments.

[0117] Reference Figures 1 to 9 In step S11, a substrate 101 is provided, an isolation layer 103 is formed in the substrate 101 to define a plurality of active areas AA, and a plurality of well regions WR are formed in the active areas AA, a plurality of word line structures 200 may be formed in the substrate 101, and a plurality of common sources CS and a plurality of drains DR are formed in the well regions WR.

[0118] Reference Figure 2 and Figure 3 In some embodiments, the substrate 101 includes a bulk semiconductor substrate composed of at least one semiconductor material. The bulk semiconductor substrate can be formed of an elemental semiconductor such as silicon or germanium, or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors, II-VI compound semiconductors, or a combination thereof.

[0119] In some embodiments, substrate 101 includes a semiconductor-on-insulator structure, which consists of a processing substrate, an insulator layer, and a topmost semiconductor material layer from bottom to top. The processing substrate and the topmost semiconductor material layer are formed of the same material as the bulk semiconductor substrate described above. The insulator layer is a crystalline or non-crystalline dielectric material, such as an oxide and / or a nitride. For example, the insulator layer is a dielectric oxide, such as silicon oxide. For another example, the insulator layer can be a dielectric nitride, such as silicon nitride or boron nitride. For another example, the insulator layer includes a stack of dielectric oxides and dielectric nitrides, such as silicon oxide and silicon nitride or boron nitride stacked in any order. The insulator layer has a thickness between about 10 nanometers (nm) and about 200 nm. The insulator layer can eliminate leakage currents between adjacent elements in substrate 101 and reduce parasitic capacitance associated with the source / drain.

[0120] It should be noted that the term "about" changes the amount of an ingredient, component, or reactant of the present disclosure to refer to a variation in the value that may occur, for example, in a concentrate or solution by typical measurement and liquid handling procedures used for preparation. In addition, variations may also arise from unintentional errors in measurement procedures, differences in the preparation, source, or purity of the ingredients used in preparing the composition or implementing the method, etc. In one aspect, the term "about" refers to a variation within 10% of the stated value. In another aspect, the term "about" refers to a variation within 5% of the stated value. In other aspects, the term "about" refers to a variation within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the stated value.

[0121] Reference Figure 2 and Figure 3 , a series of deposition processes are performed to deposit a pad oxide layer (not shown for clarity) and a pad nitride layer (not shown for clarity) on the substrate 101. A lithography process is performed to define the position of the isolation layer 103. After the lithography process, an etching process, such as an anisotropic dry etching process, is performed to form a trench penetrating the pad oxide layer, the pad nitride layer and extending to the substrate 101. An insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxynitride may be deposited into the trench, and then a planarization process such as chemical mechanical polishing is performed until the top surface of the substrate 101 is exposed to remove excess filling material to form the isolation layer 103. The top surface of the isolation layer 103 and the top surface of the substrate 101 may be substantially coplanar.

[0122] Reference Figure 2 and Figure 3 The isolation layer 103 is used to define the active area AA. In some embodiments, the active area AA extends along a direction inclined relative to the X-axis and the Y-axis in a top view.

[0123] It should be noted that each active area AA includes a portion of the substrate 101 and a space above the substrate 101. Describing an element as being disposed on the active area AA means that the element is disposed on the top surface of the portion of the substrate 101. Describing an element as being disposed in the active area AA means that the element is disposed in the portion of the substrate 101; however, the top surface of the element may be flush with the top surface of the portion of the substrate 101. Describing an element as being disposed above the active area AA means that the element is disposed above the top surface of the portion of the substrate 101.

[0124] It should be noted that in the description of the present disclosure, the surface of an element (or feature) located at the highest vertical level in the Z direction is referred to as the top surface of the element (or feature). The surface of an element (or feature) located at the lowest vertical level in the Z direction is regarded as the bottom surface of the element (or feature).

[0125] It should be noted that in the description of the present disclosure, silicon oxynitride refers to a substance containing silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon oxynitride refers to a substance containing silicon, oxygen and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0126] Reference Figure 4 and Figure 5 , well regions WR are respectively formed in the active area AA. For the sake of brevity, clarity and convenience of description, only one well region WR is described. The well region WR is formed by an implantation process using, for example, a p-type dopant. The well region WR may have a first electrical type (e.g., p-type). The term "p-type dopant" refers to an impurity that produces a valence electron defect when added to an intrinsic semiconductor material. In silicon-containing semiconductor materials, examples of p-type dopants include, but are not limited to, boron, aluminum, gallium and / or indium.

[0127] Reference Figure 6 and 7 , a plurality of word line trenches TR are formed in the well region WR to define the position of the word line structure 200. The word line trenches TR can be formed by a lithography process and a subsequent etching process. In some embodiments, the word line trenches TR have a linear shape and extend in a direction X and cross the active area AA in a top view. For example, each active area AA may intersect with two word line trenches TR. A plurality of word line structures 200 (for example, two word line structures 200) are respectively formed in the two word line trenches TR. For the sake of brevity, clarity and convenience of description, only one word line structure 200 is described. The word line structure 200 may include a word line dielectric layer 201, a word line conductive layer 203 and a word line capping layer 205.

[0128] Reference Figure 6 and Figure 7, the word line dielectric layer 201 may be conformally formed on the inner surface of the word line trench TR. The word line dielectric layer 201 may have a U-shaped cross-sectional profile. In other words, the word line dielectric layer 201 may be formed inwardly in the well region WR. In some embodiments, the word line dielectric layer 201 may be formed by a thermal oxidation process. For example, the word line dielectric layer 201 may be formed by oxidizing the inner surface of the word line trench TR. In some embodiments, the word line dielectric layer 201 may be formed by a deposition process such as chemical vapor deposition or atomic layer deposition. The word line dielectric layer 201 may include a high-k material, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, after depositing a liner polysilicon layer (not shown for clarity), the word line dielectric layer 201 may be formed by free radical oxidation of the liner polysilicon layer. In some embodiments, after forming a liner silicon nitride layer (not shown for clarity), the word line dielectric layer 201 may be formed by free radical oxidation of the liner silicon nitride layer.

[0129] In some embodiments, the high-k material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high-k material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0130] Reference Figure 6 and Figure 7 , the word line conductive layer 203 may be formed on the word line dielectric layer 201. In some embodiments, to form the word line conductive layer 203, a conductive layer (not shown for clarity) may be formed to fill the word line trench TR, and then a recess process may be performed. The recess process may be performed as an etch-back process or as a planarization process and an etch-back process sequentially performed. The word line conductive layer 203 may have a recessed shape that partially fills the word line trench TR. That is, the top surface of the word line conductive layer 203 may be at a vertical level lower than the top surface of the substrate 101.

[0131] In some embodiments, the word line conductive layer 203 may include a metal, a metal nitride, or a combination thereof. For example, the word line conductive layer 203 may be formed of titanium nitride, tungsten, or titanium nitride / tungsten. After conformally forming the titanium nitride, the titanium nitride / tungsten may have a structure in which the word line trench TR is partially filled with tungsten. Titanium nitride or tungsten may be used alone for the word line conductive layer 203. In some embodiments, the word line conductive layer 203 may be formed of a conductive material such as polysilicon, polycrystalline silicon germanium, or a combination thereof. In some embodiments, the word line conductive layer 203 may be doped with a dopant such as phosphorus, arsenic, antimony, or boron. In some embodiments, the word line conductive layer 203 may be formed of, for example, tungsten, aluminum, titanium, copper, etc., or a combination thereof.

[0132] Reference Figure 6 and Figure 7 , a dielectric material (not shown) may be deposited by, for example, chemical vapor deposition to completely fill the word line trench TR and cover the top surface of the substrate 101. A planarization process such as chemical mechanical polishing may be performed to provide a substantially flat surface for subsequent processing steps and to form a word line capping layer 205. In some embodiments, the word line capping layer 205 may be formed of, for example, silicon oxide, silicon nitride, or other applicable dielectric materials.

[0133] Reference Figure 8 and Fig. 9 , a common source CS and a drain DR may be formed in the active area AA. For the sake of brevity, clarity and convenience of description, only a common source CS and two drains DR in one active area AA are described. All other active areas AA may have the same elements and may have the same configuration. The two drains DR may be formed between two word line structures 200 and the isolation layer 103, respectively. A common source CS may be formed between two word line structures 200. The common source CS and the drain DR may be formed by an implantation process. The implantation process may employ, for example, an n-type dopant. An n-type dopant may be added to an intrinsic semiconductor to contribute free electrons to the intrinsic semiconductor. In a silicon-containing substrate, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. The common source CS and the drain DR may have a second electrical type (e.g., n-type) that is opposite to the electrical type of the well region WR. In some embodiments, the doping concentration of the common source CS and the drain DR may be between about 1E19 atoms / cm^3 and about 1E21 atoms / cm^3; however, other dopant concentrations less than or greater than the above ranges may also be used in the present application.

[0134] In some embodiments, an annealing process may be performed to activate the common source CS, the drain DR, and the well region WR. The annealing process may have a process temperature between about 800° C. and about 1250° C. The annealing process may have a process duration between about 1 millisecond and about 500 milliseconds. The annealing process may be, for example, rapid thermal annealing, laser spike annealing, or flash lamp annealing.

[0135] Fig.10 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig.11 is a cross-sectional view, showing Fig.10 The cross-sectional structure taken along the A-A' and B-B' lines. Fig.12 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig.13 and Fig.14 is a cross-sectional view, showing Fig.12 The cross-sectional structures taken along the lines AA′ and BB′ in the figure represent a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Fig.15FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig.16 and Fig.17 is a cross-sectional view, showing Fig.15 The cross-sectional structures taken along the lines AA′ and BB′ represent a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure.

[0136] Reference Figures 10 to 17 In step S13 , a plurality of bit line plugs 321 are formed on the common source CS, a plurality of bit line structures 300 are formed on the bit line plugs 321 , a plurality of first bit line spacers 311 are formed on the sidewalls of the bit line structures 300 , and a top dielectric layer 107 covering the bit line structures 300 is formed.

[0137] Reference Fig.10 and 11 , a bottom dielectric layer 105 is formed on the substrate 101. The bottom dielectric layer 105 can be used as an etch stop layer for subsequent semiconductor processes. Generally, the etch stop layer can provide a mechanism to stop the etching process when forming conductive features. In some embodiments, the bottom dielectric layer 105 is preferably formed of a dielectric material having an etching selectivity different from that of adjacent layers. For example, the bottom dielectric layer 105 can be formed of silicon nitride, silicon carbonitride, silicon oxycarbide, etc. The bottom dielectric layer 105 is deposited by chemical vapor deposition or plasma enhanced chemical vapor deposition.

[0138] Reference Fig.10 and 11 , the bit line plugs 321 are formed along the bottom dielectric layer 105 and are respectively formed on the common source CS. The bit line plugs 321 are respectively electrically connected to the common source CS. In some embodiments, the bit line plugs 321 may be formed of, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof. In some embodiments, the bit line plugs 321 may have a square cross-sectional profile in a top view, but are not limited to this shape. In some embodiments, the bit line plugs 321 may have a rectangular, circular, or other applicable cross-sectional profile in a top view.

[0139] Reference Fig.12 and 13, a layer of a first conductive material 601 is formed on the bottom dielectric layer 105. In some embodiments, the first conductive material 601 may be, for example, polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the dopant for the first conductive material 601 may include boron, aluminum, gallium, indium, antimony, arsenic, or phosphorus. In some embodiments, the layer of the first conductive material 601 may be formed, for example, by chemical vapor deposition or other applicable deposition processes.

[0140] Reference Fig.12 and 13 , a layer of a second conductive material 603 is formed on the layer of the first conductive material 601. In some embodiments, the second conductive material 603 may be, for example, titanium silicide, nickel silicide, nickel platinum silicide, tantalum silicide, or cobalt silicide. In some embodiments, the layer of the second conductive material 603 may have a thickness between about 2 nm and about 20 nm.

[0141] Reference Fig.12 and 13 A layer of a third conductive material 605 is formed on the layer of the second conductive material 603. In some embodiments, the third conductive material 605 can be, for example, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other suitable conductive materials or combinations thereof.

[0142] For the sake of brevity, clarity and convenience of description, only one bit line cover layer 307 is described.

[0143] Reference Fig.12 and 13 , a bit line cover layer 307 is formed on the layer of the third conductive material 605 and above the common source CS. The bit line cover layer 307 has a patterned configuration of the bit line structure 300. In some embodiments, in a top view, the bit line cover layer 307 extends in a direction perpendicular to the word line structure 200. In some embodiments, the bit line cover layer 307 can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or other applicable insulating materials. In some embodiments, the width W1 of the bit line cover layer 307 is greater than the width W2 of the bit line plug 321.

[0144] Reference Fig.14 , a bit line etching process is performed to remove a portion of the first conductive material 601, a portion of the second conductive material 603, and a portion of the third conductive material 605. In some embodiments, the bit line etching process can be a multi-stage etching process. For example, the bit line etching process can be a three-stage anisotropic dry etching process. The etching chemistry of each stage can be different to provide different etching selectivities.

[0145] In some embodiments, during the first stage of the bit line etching process, the etch rate ratio of the third conductive material 605 to the bit line cap layer 307 may be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1. In some embodiments, during the first stage of the bit line etching process, the etch rate ratio of the third conductive material 605 to the second conductive material 603 may be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1.

[0146] In some embodiments, in the second stage of the bit line etching process, the etching rate ratio of the second conductive material 603 to the bit line cap layer 307 may be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1. In some embodiments, in the second stage of the bit line etching process, the etching rate ratio of the second conductive material 603 to the first conductive material 601 may be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1.

[0147] In some embodiments, in the third stage of the bit line etching process, the etching rate ratio of the first conductive material 601 to the bit line cap layer 307 may be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1. In some embodiments, in the third stage of the bit line etching process, the etching rate ratio of the first conductive material 601 to the bottom dielectric layer 105 may be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1.

[0148] Reference Fig.14 , the remaining first conductive material 601 can be regarded as the bit line bottom conductive layer 301. The bit line bottom conductive layer 301 is formed on the bit line plug 321 and can be electrically connected to the common source CS. The remaining second conductive material 603 can be regarded as the bit line middle conductive layer 303. The bit line middle conductive layer 303 is formed on the bit line bottom conductive layer 301. The remaining third conductive material 605 can be regarded as the bit line top conductive layer 305. The bit line top conductive layer 305 is formed between the bit line middle conductive layer 303 and the bit line capping layer 307. The bit line bottom conductive layer 301, the bit line middle conductive layer 303, the bit line top conductive layer 305 and the bit line capping layer 307 together constitute the bit line structure 300.

[0149] Reference Fig.15 and 16, a layer of spacer material (not shown) is conformally formed to cover the bottom dielectric layer 105 and the bit line structure 300. In some embodiments, the layer of spacer material can be formed by, for example, atomic layer deposition, chemical vapor deposition, or other applicable deposition processes. In some embodiments, the spacer material can be, for example, an undoped oxide. In some embodiments, the spacer material can be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, or other applicable insulating materials. Subsequently, a spacer etching process is performed to remove part of the spacer material. The remaining spacer material can be regarded as a plurality of first bit line spacers 311. The first bit line spacers 311 are formed on the sidewalls 300SW of the bit line structure 300. In some embodiments, the spacer etching process can be, for example, an anisotropic etching process such as reactive ion etching.

[0150] Reference Fig.17 , a top dielectric layer 107 is formed over the substrate 101 to cover the bit line structure 300 and the first bit line spacer 311. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material and provide a substantially flat surface for subsequent process steps. In some embodiments, the top dielectric layer 107 may be formed of, for example, an undoped oxide. In some embodiments, the top dielectric layer 107 includes, for example, silicon oxide, undoped silicate glass, a spin-on low-k dielectric layer, a chemical vapor deposited low-k dielectric layer, or a combination thereof. In some embodiments, the top dielectric layer 107 includes a self-planarizing material such as spin-on glass or a self-planarizing material such as SiLK TM In some embodiments, the top dielectric layer 107 may be formed by a deposition process including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, or spin coating.

[0151] Reference Fig.17 , a first mask 701 is formed on the top dielectric layer 107. In some embodiments, the first mask 701 may be a photoresist layer. The first mask 701 includes a pattern defining a position and a contour of a cell plug structure 400 to be described later.

[0152] Fig.18 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig.19 and Fig. 20 is a cross-sectional view, showing Fig.18 The cross-sectional structures taken along the lines AA′ and BB′ represent a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Fig.21 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig. 22 and Fig.23 is a cross-sectional view, showing Fig.21The cross-sectional structures taken along the lines AA′ and BB′ represent a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Fig.24 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig.25 is a cross-sectional view, showing Fig.24 The cross-sectional structure taken by the A-A' and B-B' line segments.

[0153] Reference Figure 1 and Figures 18 to 25 In step S15 , a plurality of openings 107O are formed to expose the drains DR, a plurality of sacrificial segments 609S are conformally formed on the sidewalls 107SW of the openings 107O, and a plurality of cell plug bottom conductive layers 401 are formed in the openings 107O.

[0154] Reference Fig.18 and 19 , an opening etching process can be performed using the first mask 701 as a mask to remove a portion of the top dielectric layer 107 and a portion of the bottom dielectric layer 105. In some embodiments, the opening etching process can be a multi-stage etching process. For example, the opening etching process can be a two-stage anisotropic dry etching process. The etching chemistry of each stage can be different to provide different etching selectivities.

[0155] In some embodiments, in the first stage of the opening etching process, the etching rate ratio of the top dielectric layer 107 to the first mask 701 may be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1. In some embodiments, in the first stage of the opening etching process, the etching rate ratio of the top dielectric layer 107 to the bottom dielectric layer 105 may be between about 100: 1 and about 1.05: 1, between about 15: 1 and about 2: 1, or between about 10: 1 and about 2: 1.

[0156] In some embodiments, in the second stage of the opening etching process, the etching rate ratio of the bottom dielectric layer 105 to the first mask 701 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, in the second stage of the opening etching process, the etching rate ratio of the bottom dielectric layer 105 to the drain DR may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0157] After the opening etching process, an opening 107O may be formed along the top dielectric layer 107 and the bottom dielectric layer 105. The drain DR may be exposed through the openings 107O respectively. The first mask 701 will be removed after the opening 107O is formed. In some embodiments, the opening 107O may have a circular cross-sectional profile in a top view, but is not limited to this shape. In some embodiments, the opening 107O may have a rectangular, square, or other suitable cross-sectional profile in a top view.

[0158] Reference Fig. 20 , the sacrificial layer 609 is conformally formed on the top surface 107TS of the top dielectric layer 107 and in the opening 107O. In some embodiments, the sacrificial layer 609 can be formed of a material having an etching selectivity relative to the top dielectric layer 107. In some embodiments, the sacrificial layer 609 can be formed of a doped oxide such as borosilicate glass, phosphosilicate glass, borophosphosilicate glass, fluorosilicate glass, carbon-doped silicon oxide, etc. In some embodiments, the sacrificial layer 609 can be formed of a thermally decomposable polymer or a thermally degradable polymer. When exposed to a temperature exceeding the decomposition temperature of the thermally decomposable polymer or the degradation temperature of the thermally degradable polymer, the thermally decomposable polymer or the thermally degradable polymer decomposes or degrades into a gaseous state. In some embodiments, the sacrificial layer 609 can be formed by, for example, atomic layer deposition, chemical vapor deposition, or other applicable deposition processes. The drain DR can be covered by the sacrificial layer 609 at the current stage.

[0159] Reference Fig.21 and Fig. 22 , a first stamping etching process is performed to remove a portion of the sacrificial layer 609. In detail, the sacrificial layer 609 formed on the top surface 107TS of the top dielectric layer 107 and the bottom 107B of the opening 107O is removed. In some embodiments, the first stamping etching process may be an anisotropic etching process, such as an anisotropic dry etching process or reactive ion etching. In some embodiments, during the first stamping etching process, the etching rate ratio of the sacrificial layer 609 to the top dielectric layer 107 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the first stamping etching process, the etching rate ratio of the sacrificial layer 609 to the drain DR may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. After the first stamp etching process, the remaining sacrificial layer 609 may be referred to as a sacrificial segment 609S.

[0160] Reference Fig.21 and 22, the sacrificial segments 609S are respectively formed on the sidewalls 107SW of the openings 107O. The sacrificial segments 609S may have a circular cross-sectional profile in a top view, but are not limited thereto. The top view shape of the sacrificial segments 609S is determined by the top view shape of the openings 107O. The drain DR may be partially exposed at this stage.

[0161] Reference Fig.23 , a layer of the fourth conductive material 607 is formed on the top surface 107TS of the top dielectric layer 107 and may completely fill the opening 107O. A planarization process, such as chemical mechanical polishing, is performed to remove excess material and provide a substantially flat surface for subsequent process steps. In some embodiments, the fourth conductive material 607 may be, for example, polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the dopant of the fourth conductive material 607 may include boron, aluminum, gallium, indium, antimony, arsenic, or phosphorus. In some embodiments, the layer of the fourth conductive material 607 may be formed, for example, by chemical vapor deposition or other applicable deposition processes.

[0162] Reference Fig.24 and 25 , an etch-back process may be performed to remove a portion of the fourth conductive material 607. In some embodiments, in the etch-back process, an etch rate ratio of the fourth conductive material 607 to the top dielectric layer 107 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, in the etch-back process, an etch rate ratio of the fourth conductive material 607 to the plurality of sacrificial segments 609S may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. After the etch-back process, the remaining fourth conductive material 607 may be regarded as a cell plug bottom conductive layer 401. The cell plug bottom conductive layers 401 are respectively and correspondingly formed in the openings 107O. The cell plug bottom conductive layers 401 are respectively and correspondingly surrounded by the sacrificial segments 609S.

[0163] For the sake of brevity, clarity and convenience of description, only one cell plug bottom conductive layer 401 is described.

[0164] Reference Fig.25 In some embodiments, the top surface 401TS of the cell plug bottom conductive layer 401 is located at a vertical level VL1 between the top surface 305TS of the bit line top conductive layer 305 and the bottom surface 305BS of the bit line top conductive layer 305. Alternatively, in some embodiments, the top surface 401TS of the cell plug bottom conductive layer 401 (e.g. Fig.28107O). The cell plug structure 400 is a vertical level between the top surface 301TS of the bit line bottom conductive layer 301 and the top surface 105TS of the bottom dielectric layer 105. In some embodiments, the width ratio of the width W3 of the cell plug bottom conductive layer 401 to the width W4 of the opening 107O may be between about 0.5 and about 0.95 or between about 0.6 and about 0.85. It should be noted that the cell plug structure 400 to be described later is formed in the opening 107O. Therefore, the width W4 of the opening 107O will be inherited by the cell plug structure 400.

[0165] Fig.26 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig. 27 and Fig.28 is a cross-sectional view, showing Fig.26 The cross-sectional structures taken along the lines AA′ and BB′ represent a partial process of manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Fig.29 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig.30 is a cross-sectional view, showing Fig.30 The cross-sectional structure taken along the A-A' and B-B' line segments. Fig.31 FIG. 1 is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Fig.32 is a cross-sectional view, showing Fig.31 The cross-sectional structure taken along the A-A' and B-B' lines.

[0166] Reference Figure 1 and Figure 26 to Figure 32 In step S17, the sacrificial segment 609S is removed to form a plurality of spaces SP around the cell plug bottom conductive layer 401, a plurality of cell plug top sealing layers 405 are formed to seal the spaces SP, and a plurality of first air gaps 501 are formed at the same time, and a plurality of cell plug top conductive layers 403 are formed on the cell plug bottom conductive layer 401 to constitute a plurality of cell plug structures 400.

[0167] Reference Fig.26 and Fig. 27 , a removal process is performed to remove the sacrificial segment 609S, and a space SP (or gap) is formed (or established) around the cell plug bottom conductive layer 401. In some embodiments, the space SP has a circular cross-sectional profile in a top view, but is not limited thereto. The shape of the space SP in a top view is determined by the shape of the opening 107O in a top view.

[0168] In some embodiments, the removal process may involve gas phase etching. For example, gas phase hydrogen fluoride may be used to remove the sacrificial segment 609S, thereby forming the space SP in situ. Due to the density difference between the sacrificial segment 609S formed of doped oxide and the top dielectric layer 107 and the bottom dielectric layer 105 formed of undoped oxide, gas phase hydrogen fluoride exhibits a higher etching rate on the sacrificial segment 609S formed of doped oxide. Therefore, gas phase hydrogen fluoride selectively removes the sacrificial segment 609S formed of doped oxide, while leaving the top dielectric layer 107 and the bottom dielectric layer 105 formed of undoped oxide intact.

[0169] In some embodiments, the removal process may involve thermal treatment. Fig.25 The intermediate semiconductor element shown may be heated to decompose or degrade the sacrificial segment 609S formed of a thermally decomposable polymer or a thermally degradable polymer. The temperature of the heat treatment may be about 300° C. to about 450° C. In some embodiments, the temperature of the heat treatment may be about 350° C. to about 420° C.

[0170] Reference Fig.28 , a layer of sealing material 613 is conformally formed on the top surface 107TS of the top dielectric layer 107, on the cell plug bottom conductive layer 401, and on the sidewalls 107SW of the opening 107O. The layer of sealing material 613 seals the space SP and converts the sealed space into the first air gap 501. In some embodiments, the bottom surface 613BS of the layer of sealing material 613 may be located at a vertical level substantially coplanar with the top surface 401TS of the cell plug bottom conductive layer 401. In some embodiments, the sealing material 613 may flow downward toward the bottom dielectric layer 105. This means that the bottom surface 613BS of the layer of sealing material 613 may be disposed at a relatively lower vertical level ( Fig.28 Even in this case, when the sealing material 613 flows downward, there is still a remaining unfilled space to form the first air gap 501.

[0171] In a top view, the cross-sectional shape of the first air gap 501 is determined by the cross-sectional shape of the space SP. That is, the first air gap 501 may have a circular cross-sectional profile or a cross-sectional profile of other suitable shapes.

[0172] In some embodiments, the sealing material 613 may be, for example, silicon oxide, silicon nitride, or other suitable dielectric materials.

[0173] Reference Fig.29 and Fig.30, a second stamping etching process is performed to remove a portion of the sealing material 613. In detail, the sealing material 613 formed on the top surface 107TS of the top dielectric layer 107 is completely removed. In addition, the sealing material 613 formed on the top surface 401TS of the cell plug bottom conductive layer 401 may be partially removed. Such partial removal allows the remaining sealing material 613 to continue to seal the first air gap 501 while partially exposing the top surface 401TS of the cell plug bottom conductive layer 401.

[0174] In some embodiments, the second stamping etching process may be an anisotropic etching process, such as an anisotropic dry etching process or reactive ion etching. In some embodiments, during the second stamping etching process, the etching rate ratio of the sealing material 613 to the top dielectric layer 107 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the second stamping etching process, the etching rate ratio of the sealing material 613 to the cell plug bottom conductive layer 401 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0175] After the second stamping and etching process, the remaining sealing material 613 can be regarded as the cell plug top sealing layer 405. For the sake of brevity, clarity and convenience of description, only one cell plug top sealing layer 405 is described. In some embodiments, the thickness T1 of the cell plug top sealing layer 405 is greater than the thickness T2 of the first air gap 501. In some embodiments, the cell plug top sealing layer 405 has a circular cross-sectional profile in a top view, but is not limited thereto. The shape of the cell plug top sealing layer 405 in a top view is determined by the shape of the opening 107O in a top view.

[0176] Reference Fig.31 and Fig.32, the cell plug top conductive layer 403 is formed on the cell plug bottom conductive layer 401 respectively. The cell plug top conductive layer 403 is surrounded by the cell plug top sealing layer 405 respectively. For the sake of brevity, clarity and convenience of description, only one cell plug top conductive layer 403 is described. In some embodiments, the width W5 of the cell plug top conductive layer 403 is less than the width W3 of the cell plug bottom conductive layer 401. The cell plug top conductive layer 403 is electrically coupled to the drain DR through the cell plug bottom conductive layer 401 and is electrically connected to the capacitor (not shown). In some embodiments, the cell plug top conductive layer 403 has a circular cross-sectional profile in a top view, but is not limited to this shape. The shape of the cell plug top sealing layer 405 in a top view is determined by the shape of the opening 107O in a top view. In some embodiments, the cell plug top conductive layer 403 is formed by completely filling the opening 107O with a conductive material; then, a planarization process is performed until the top surface 107TS of the top dielectric layer 107 is exposed. In some embodiments, the conductive material can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof.

[0177] Reference Fig.31 and Fig.32 The cell plug bottom conductive layer 401 , the cell plug top conductive layer 403 and the cell plug top sealing layer 405 together constitute a cell plug structure 400 .

[0178] Due to the presence of the first air gap 501, parasitic capacitance between conductive features (eg, the bit line structure 300 and the cell plug structure 400) can be reduced. As a result, the performance of the semiconductor device 1A can be improved.

[0179] Figure 33 to Figure 36 2 is a cross-sectional view illustrating a partial process of manufacturing a semiconductor device 1B according to another embodiment of the present disclosure.

[0180] Reference Fig.33 , the intermediate semiconductor element can be used similar to Figures 2 to 16The first bit line spacers 311 are prepared by the process shown in, which will not be repeated here. A plurality of first bit line spacers 311 can be formed of, for example, undoped oxide or silicon nitride. A plurality of sacrificial spacers 611 are respectively formed on the plurality of first bit line spacers 311. In some embodiments, the sacrificial spacers 611 are formed of a material having an etching selectivity relative to the first bit line spacers 311. In some embodiments, the sacrificial spacers 611 can be formed of doped oxides such as borosilicate glass, phosphosilicate glass, borophosphosilicate glass, fluorinated silicate glass, carbon-doped silicon oxide, etc. In some embodiments, the sacrificial spacers 611 can be formed of a thermally decomposable polymer or a thermally degradable polymer. When exposed to a temperature exceeding the decomposition temperature of the thermally decomposable polymer or the degradation temperature of the thermally degradable polymer, the thermally decomposable polymer or the thermally degradable polymer decomposes or degrades into a gaseous state.

[0181] Reference Fig.34 A plurality of third bit line spacers 315 are respectively formed on the plurality of sacrificial spacers 611. The plurality of third bit line spacers 315 may be formed of, for example, undoped oxide or silicon nitride.

[0182] Reference Fig.35 , a removal process is performed to remove the plurality of sacrificial spacers 611 and to form (or generate) a plurality of second air gaps 503 respectively. For the sake of brevity, clarity and convenience of description, only one second air gap 503 is described. The second air gap 503 is formed between the first bit line spacer 311 and the third bit line spacer 315. In some embodiments, the second air gap 503 has a linear cross-sectional profile in a top view (not shown).

[0183] In some embodiments, the removal process involves vapor phase etching. For example, gas phase hydrogen fluoride can be used to remove the sacrificial spacer 611, thereby forming the second air gap 503 in situ. Due to the density difference between the sacrificial spacer 611 formed by the doped oxide and the first bit line spacer 311 and the third bit line spacer 315 formed by the undoped oxide, the gas phase hydrogen fluoride exhibits a higher etching rate on the sacrificial spacer 611 formed by the doped oxide. Therefore, the gas phase hydrogen fluoride selectively removes the sacrificial spacer 611 formed by the doped oxide, while leaving the first bit line spacer 311 and the third bit line spacer 315 formed by the undoped oxide intact.

[0184] In some embodiments, the removal process may involve thermal treatment. Fig.25 The intermediate semiconductor element shown may be heated to decompose or degrade the sacrificial spacer 611 formed of a thermally decomposable polymer or a thermally degradable polymer. The temperature of the heat treatment may be about 300° C. to about 450° C. In some embodiments, the temperature of the heat treatment may be about 350° C. to about 420° C.

[0185] Reference Fig.36 The top dielectric layer 107, the plurality of first air gaps 501 and the plurality of cell plug structures 400 may be formed by using a structure similar to Figures 17 to 32 The process shown in is used to form it, and the description will not be repeated here.

[0186] Due to the existence of the second air gap 503, the parasitic capacitance between the conductive features (eg, the bit line structure 300 and the cell plug structure 400) can be further reduced. Therefore, the performance of the semiconductor device 1B can be further improved.

[0187] Figures 37 to 41 2 is a cross-sectional view illustrating a partial process of manufacturing a semiconductor device 1C according to another embodiment of the present disclosure.

[0188] Reference Fig.37 , the intermediate semiconductor element can be used similar to Figures 2 to 14 The bottom dielectric layer 105 and the plurality of bit line structures 300 may be formed by the process shown in , which will not be repeated here. A liner layer 317 may be conformally formed to cover the bottom dielectric layer 105 and the plurality of bit line structures 300. The liner layer 317 may be formed by, for example, atomic layer deposition, chemical vapor deposition, or other applicable deposition processes. In some embodiments, the liner layer 317 may be formed of, for example, silicon nitride, silicon oxynitride, silicon oxynitride, or other applicable dielectric materials.

[0189] Reference Fig.38 , a layer of a spacer material 617 is conformally formed on the liner layer 317. In some embodiments, the spacer material 617 may include vanadium and a low-k material. For example, the spacer material 617 may include one or more vanadium oxides. The type of vanadium oxide depends on the VO x , where x is in a range from about 1 to about 3. In some embodiments, the dielectric constant of the spacer material 617 may be between about 1 and about 3.

[0190] In some embodiments, the layer of spacer material 617 can be formed by, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, or plasma enhanced atomic layer deposition. The atomic layer deposition process is theoretically self-limiting and continues until all available active sites on the substrate surface have reacted. The atomic layer deposition process can be performed by time domain or spatial atomic layer deposition.

[0191] In a time domain process, a substrate (e.g., liner layer 317) is exposed to a single reactive gas at any given time. In an exemplary time domain process, a processing chamber may be filled with a metal precursor for a period of time to allow the metal precursor to fully react with available sites on the substrate. A second reactive gas may then be flowed into the processing chamber, and the precursor may be purged from the processing chamber before the second reactive gas fully reacts with the substrate surface or material on the substrate surface. The time domain process minimizes the mixing of reactive gases by ensuring that only one reactive gas is present in the processing chamber at any given time. At the beginning of any reactive gas exposure, there is a delay in the concentration of the reactive species going from zero to a final predetermined pressure. Similarly, there is a delay in purging all reactive species from the processing chamber.

[0192] In spatial atomic layer deposition, the substrate moves between different processing zones within a single processing chamber. Each individual processing zone is separated from adjacent processing zones by a gas curtain. The gas curtain helps prevent the reactant gases from mixing to minimize any gas phase reactions. The movement of the substrate through the different processing zones allows the substrate to be sequentially exposed to different reactant gases while preventing gas phase reactions.

[0193] In some embodiments, the vanadium precursor can be any vanadium organometallic compound. Suitable vanadium precursors include but are not limited to triisopropoxy vanadium oxy, triethoxy vanadium oxy, vanadium acetylacetonate, vanadium trichloride, vanadium chloride (III), vanadium chloride (IV), etc. The vanadium precursor can be delivered by a carrier gas such as argon, helium or hydrogen. In some embodiments, the reactant may include an oxygen source, a nitrogen source, a carbon source, a hydrogen source, a boron source, a silicon source or a combination thereof.

[0194] In some embodiments, the layer of spacer material 617 may be doped. The layer of spacer material 617 may include a dopant in an amount ranging from 0 to 50 atomic % of the layer. Dopants include, but are not limited to, carbon, nitrogen, silicon, boron, and fluorine.

[0195] Reference Fig.39 , a spacer etching process is performed to remove a portion of the spacer material 617. The remaining spacer material 617 can be regarded as a plurality of second bit line spacers 313 covering the sidewalls 317SW of the liner layer 317. The spacer etching process can be, for example, an anisotropic etching process such as reactive ion etching.

[0196] Reference Fig.40 , a plurality of third bit line spacers 315 are respectively formed on the plurality of sacrificial spacers 611. The third bit line spacers 315 may be formed of, for example, undoped oxide or silicon nitride. In some embodiments, the third bit line spacers 315 may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride or other applicable insulating materials.

[0197] Reference Fig.41 The top dielectric layer 107, the plurality of first air gaps 501 and the plurality of cell plug structures 400 may be formed by using a structure similar to Figures 17 to 32 The process shown in is formed and will not be repeated here.

[0198] By using the second bit line spacer 313 containing vanadium, the parasitic capacitance between the conductive features (eg, the bit line structure 300 and the cell plug structure 400) can be further reduced. Therefore, the performance of the semiconductor device 1C can be further improved.

[0199] One aspect of the present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, and forming a drain in the substrate; forming a top dielectric layer on the substrate, and forming an opening along the top dielectric layer to expose the drain; conformally forming a sacrificial layer in the opening; performing a first stamping etching process to partially remove the sacrificial layer, thereby forming a sacrificial segment on a side wall of the opening and exposing the drain; forming a cell plug bottom conductive layer on the drain and surrounded by the sacrificial segment; performing a removal process to remove the sacrificial segment and form a cell plug bottom conductive layer; forming a cell plug top sealing layer on the cell plug bottom conductive layer to seal the space, thereby forming a first air gap around the cell plug bottom conductive layer; and forming a cell plug top conductive layer on the cell plug bottom conductive layer and surrounded by the cell plug top sealing layer. The cell plug bottom conductive layer, the cell plug top conductive layer and the cell plug top sealing layer constitute a cell plug structure.

[0200] Due to the design of the semiconductor device disclosed in the present invention, the parasitic capacitance between the conductive features can be reduced by using the first air gap 501. The reduction of the parasitic capacitance promotes the improvement of the performance of the semiconductor device 1A. In addition, the parasitic capacitance can be further reduced by including the second air gap 503 and / or the second bit line spacer 313 including vanadium. Therefore, the performance of the semiconductor device 1A will be improved.

[0201] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0202] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A method for preparing a semiconductor element, include: Providing a substrate and forming a drain in the substrate; forming a top dielectric layer on the substrate, and forming an opening along the top dielectric layer to expose the drain; conformally forming a sacrificial layer in the opening; Performing a first stamp etching process to partially remove the sacrificial layer, thereby forming a sacrificial segment on a sidewall of the opening and exposing the drain; forming a cell plug bottom conductive layer on the drain and surrounded by the sacrificial segment; Performing a removal process to remove the sacrificial segment and form a space around the bottom conductive layer of the cell plug; forming a cell plug top sealing layer on the cell plug bottom conductive layer to seal the space, thereby forming a first air gap around the cell plug bottom conductive layer; and forming a cell plug top conductive layer on the cell plug bottom conductive layer and surrounded by the cell plug top sealing layer, The bottom conductive layer of the unit plug, the top conductive layer of the unit plug and the top sealing layer of the unit plug constitute a unit plug structure.

2. The preparation method as claimed in claim 1, wherein the removal process comprises a vapor phase etching process. The method of claim 2 , wherein the top dielectric layer comprises undoped oxide. The method of claim 3 , wherein the sacrificial segment comprises undoped oxide. 5 . The method of claim 4 , wherein the vapor etching process comprises using vapor phase hydrogen fluoride to remove the sacrificial segment. 6 . The method of claim 5 , wherein the bottom conductive layer of the cell plug comprises polysilicon, polygermanium, polysilicon germanium, doped polysilicon, doped polygermanium, doped polysilicon, or a combination thereof.

7. The method of claim 6, wherein the cell plug top conductive layer comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminide, or a combination thereof. 8 . The manufacturing method according to claim 7 , wherein the cell plug top sealing layer comprises silicon oxide or silicon nitride. 9 . The method of claim 8 , wherein the first air gap comprises a circular cross-sectional profile in a top view. 10 . The manufacturing method of claim 9 , wherein the cell plug top sealing layer comprises a circular cross-sectional profile in the top view.

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