Wafer
By dividing the wafer into multiple sorting areas and arranging conventional, reference and model grains, the problem of poor accuracy of sorting machines in small grain sorting is solved, improving sorting accuracy and reducing preparation costs .
Patent Information
- Application Number
- CN202410990503.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-23
- Publication Date
- 2024-12-10
AI Technical Summary
During the preparation process of light emitting diode chips, as the number of grains after wafer cutting increases, it is difficult for the sorting machine to accurately find the required grains, resulting in missing selection of qualified grains or misselecting of unqualified grains, affecting the preparation Cost and efficiency.
By dividing the wafer into multiple sorting areas and arranging conventional grains, reference grains and model grains in each area in a perpendicular direction, the reference grains are used to identify the sorting reference position. The particle is used to identify the position of the sorting model and improve the identification accuracy of the sorting machine.
It effectively improves the accuracy of grain sorting, reduces manual point errors and combined misalignment, improves the overall yield and reduces the preparation cost.
Smart Images
Figure CN119108379A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor preparation, and in particular relates to a wafer. Background Art
[0002] A wafer is an intermediate product in the preparation process of a light-emitting diode chip, which includes a substrate and an epitaxial layer grown on the substrate.
[0003] In the related art, a wafer is usually cut into multiple crystal grains, and qualified crystal grains are selected through a sorting machine, thereby completing the sorting process for the wafer.
[0004] However, in order to reduce the production cost of LED chips, the number of crystals cut from a wafer is increasing, and the size of the crystals is naturally getting smaller and smaller. As a result, during the crystal sorting process, the sorting machine is difficult to accurately find the required crystals, resulting in the missed selection of qualified crystals or the misselection of unqualified crystals. Summary of the invention
[0005] The embodiment of the present disclosure provides a wafer that can improve the accuracy of grain sorting. The technical solution is as follows:
[0006] The disclosed embodiment provides a wafer, comprising: a plurality of sorting areas;
[0007] A plurality of crystal grains are arranged in each of the sorting regions, and the plurality of crystal grains are arranged in a matrix along a first direction and a second direction, respectively, the first direction and the second direction are perpendicular to each other, and the plurality of crystal grains include conventional crystal grains, reference crystal grains, and standard crystal grains;
[0008] Each of the conventional grains is evenly arranged in the corresponding sorting area;
[0009] The reference crystal grain is located in the middle of the corresponding sorting area, and the reference crystal grain is close to the sorting reference point of the wafer, and the reference crystal grain is used for the sorting machine to identify the sorting reference position;
[0010] Each of the benchmark crystal grains is evenly spaced and arranged in the corresponding sorting area, and the benchmark crystal grains are used for the sorting machine to identify the sorting benchmark position.
[0011] In an implementation of the present disclosure, the ratio of the number of the benchmark grains to the number of the grains is 1 / 200 to 1 / 800.
[0012] In an implementation of the present disclosure, in the first direction, there are 19 to 29 conventional grains between two adjacent model grains;
[0013] In the second direction, there are 13 to 23 conventional grains between two adjacent model grains.
[0014] In one implementation of the present disclosure, the model crystal grain includes a substrate, an epitaxial layer and a model primary electrode stacked in sequence;
[0015] The benchmark primary electrode includes a first section and a second section, an angle is formed between the first section and the second section, and the first section and the second section intersect.
[0016] In one implementation of the present disclosure, the length direction of the first segment is consistent with the first direction;
[0017] The length direction of the second segment is consistent with the second direction.
[0018] In one implementation of the present disclosure, the epitaxial layer includes a first semiconductor layer and a second semiconductor layer stacked in sequence;
[0019] The first semiconductor layer and the second semiconductor layer each have a groove at their outer edges extending to the substrate.
[0020] In one implementation of the present disclosure, the benchmark crystal grain further includes a reflective layer;
[0021] The reflective layer covers the benchmark primary electrode and the epitaxial layer.
[0022] In one implementation of the present disclosure, the reference crystal grain includes a substrate, an epitaxial layer, and a reference primary electrode stacked in sequence;
[0023] The reference primary electrode includes an arrow portion and a lead segment, one end of the lead segment is connected to the arrow portion, and the length direction of the lead segment is consistent with the direction of the arrow portion.
[0024] In one implementation of the present disclosure, the epitaxial layer includes a first semiconductor layer and a second semiconductor layer stacked in sequence;
[0025] The first semiconductor layer and the second semiconductor layer each have a groove at their outer edges extending to the substrate.
[0026] In one implementation of the present disclosure, the reference crystal grain further includes a reflective layer;
[0027] The reflective layer covers the reference primary electrode and the epitaxial layer.
[0028] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:
[0029] The wafer is divided into multiple sorting areas so that the sorting machine can sort each sorting area in turn, thereby reducing the range of a single sorting, which is beneficial to improving the sorting accuracy. In each sorting area, a plurality of grains are arranged, and each grain is arranged in a matrix along a first direction and a second direction perpendicular to each other, so that the arrangement of the grains has a strong regularity, which is beneficial to the identification of the sorting machine. The grains include three types, namely conventional grains, reference grains and standard grains. Conventional grains are standard grains, which are evenly arranged in the corresponding sorting area. The reference grains are used for the sorting machine to identify the sorting reference position. Since the reference grains are located in the middle of the corresponding sorting area and close to the sorting reference point of the wafer, the reference grains are easily recognized by the sorting machine and used as the sorting reference point, avoiding manual point setting errors, resulting in problems such as misalignment of the closing. The benchmark crystal grains are used for the sorting machine to identify the sorting benchmark position. Since the benchmark crystal grains are evenly spaced in the corresponding sorting area, during the sorting process, the sorting machine can always identify the benchmark position through the benchmark crystal grains, thereby achieving accurate self-movement, which is beneficial to improving the accuracy of sorting.
[0030] That is to say, the wafer provided in the embodiment of the present disclosure divides the grains into three types: conventional grains, reference grains and model grains. The accuracy of grain sorting by the sorting machine can be effectively improved through the reference grains and model grains. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0032] Figure 1 It is a structural schematic diagram of a wafer provided by the related technology;
[0033] Figure 2 is a schematic diagram of the layout of grains in a sorting area provided by an embodiment of the present disclosure;
[0034] Figure 3 The embodiment of the present disclosure provides Figure 2 A magnified image of area A;
[0035] Figure 4 The embodiment of the present disclosure provides Figure 2 A magnified view of area B;
[0036] Figure 5 is a schematic structural diagram of a benchmark crystal grain provided by an embodiment of the present disclosure;
[0037] Figure 6 It is a schematic diagram of the structure of the reference grain provided by the embodiment of the present disclosure.
[0038] The symbols in the figure mean the following:
[0039] 10. Sorting area;
[0040] 20. Conventional grains;
[0041] 30. Reference grain;
[0042] 310, reference primary electrode; 311, arrow portion; 312, lead wire segment;
[0043] 40. Pacesetter grain;
[0044] 410, standard primary electrode; 411, first section; 412, second section;
[0045] 50. Sorting reference point;
[0046] 60. substrate;
[0047] 70. Epitaxial layer;
[0048] 710, a first semiconductor layer; 720, a second semiconductor layer;
[0049] 80. Groove;
[0050] 90. Reflective layer.
[0051] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION
[0052] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0053] In order to better understand the wafer provided by the embodiments of the present disclosure, the relevant technology is first introduced below.
[0054] In the preparation process of light-emitting diode chips, after the wafer is prepared, it is necessary to cut the wafer to obtain a large number of grains. Among these grains, there are both qualified grains and unqualified grains (commonly known as NG grains in the industry), so after cutting, a sorting process is required, that is, the qualified grains are sorted out by a sorting machine for subsequent processes, such as wire bonding, packaging, etc. In the sorting process, in order to ensure the movement accuracy of the suction arm of the sorting machine, a mapping diagram needs to be prepared. The mapping diagram is formulated according to the layout of the grains on the wafer. The suction arm can accurately find the grains that need to be sucked according to the mapping diagram.
[0055] In order to reduce the preparation cost, the number of grains cut from a wafer is increasing, which makes the mapping diagram more and more complicated. It is more likely to have abnormalities such as setting the wrong (0, 0) point, that is, the sorting reference position, and the sorting go point error, which will lead to different data of the same wafer being misaligned, and finally a large number of NG grains will be outflowed.
[0056] In order to solve the above technical problems, the present disclosure provides a wafer. Figure 1 is a schematic diagram of the structure of the wafer, see Figure 1 In this embodiment, the wafer includes a plurality of sorting regions 10 .
[0057] Figure 2 The schematic diagram of the grain layout in the sorting area 10 is shown in FIG. Figure 2 In this embodiment, a plurality of grains are arranged in each sorting area 10, and the plurality of grains are arranged in a matrix along a first direction a and a second direction b, respectively. The first direction a and the second direction b are perpendicular to each other, and the plurality of grains include conventional grains 20, reference grains 30, and standard grains 40. Each conventional grain 20 is evenly arranged in the corresponding sorting area 10. The reference grain 30 is located in the middle of the corresponding sorting area 10, and the reference grain 30 is close to the sorting reference point 50 of the wafer (commonly known as the mark point in the industry), and the reference grain 30 is used for the sorting machine to identify the sorting reference position. Each standard grain 40 is evenly spaced in the corresponding sorting area 10, and the standard grain 40 is used for the sorting machine to identify the sorting standard position.
[0058] It is worth noting that, since the density of the conventional grains 20 is very high, in order to avoid the conventional grains 20 affecting Figure 2 The display of other components in Figure 2 Only some conventional grains 20 in region A are retained, and the rest of the conventional grains 20 are omitted. The arrangement of the rest of the omitted conventional grains 20 can refer to the conventional grains 20 shown in region A.
[0059] The wafer is divided into a plurality of sorting areas 10, so that the sorting machine can sort each sorting area 10 in turn, thereby reducing the range of a single sorting, which is conducive to improving the sorting accuracy. In each sorting area 10, a plurality of crystal grains are arranged, and each crystal grain is arranged in a matrix along a first direction a and a second direction b that are perpendicular to each other, so that the arrangement of the crystal grains has a strong regularity, which is conducive to the identification of the sorting machine.
[0060] The grains include three types, namely conventional grains 20, reference grains 30 and standard grains 40. Conventional grains 20 are standard grains, which are evenly arranged in the corresponding sorting area 10. The reference grains 30 are used for the sorting machine to identify the sorting reference position. Since the reference grains 30 are located in the middle of the corresponding sorting area 10 and close to the sorting reference point 50 of the wafer, the reference grains 30 are easily identified by the sorting machine and used as the sorting reference point 50, avoiding manual point setting errors and causing problems such as misalignment. Standard grains 40 are used for the sorting machine to identify the standard position of sorting. Since each standard grain 40 is evenly spaced in the corresponding sorting area 10, during the sorting process, the sorting machine can always identify the standard position through each standard grain 40, thereby achieving accurate self-movement (commonly known as go point in the industry), which is conducive to improving the accuracy of sorting.
[0061] That is to say, the wafer provided in the embodiment of the present disclosure divides the grains into three types: conventional grains 20, reference grains 30 and model grains 40. The reference grains 30 and model grains 40 can effectively improve the accuracy of grain sorting by a sorting machine.
[0062] In this embodiment, the arrangement of the benchmark dies 40 on the wafer is consistent with the arrangement of the F benchmark points on the mapping diagram.
[0063] In this way, the sorting machine can compare the identified benchmark crystal grain 40 with the F benchmark point on the mapping diagram during operation, thereby achieving accurate self-movement, which is conducive to improving the accuracy of sorting.
[0064] As can be seen from the foregoing, since the standard grain 40 is inserted into each conventional grain 20, it is beneficial to improve the accuracy of sorting. Therefore, the insertion method of the standard grain 40 into each conventional grain 20 is the key to improving the accuracy of sorting. The standard grain 40 is introduced below.
[0065] In this embodiment, the ratio of the number of the model crystal grains 40 to the number of the crystal grains is 1 / 200 to 1 / 800.
[0066] In the above implementation, the ratio of the number of the standard grains 40 to the number of grains determines the insertion density of the standard grains 40 in the conventional grains 20. The larger the ratio of the number of the standard grains 40 to the number of grains, the more the number of the standard grains 40, and the greater the insertion density of the standard grains 40 in the conventional grains 20. The smaller the ratio of the number of the standard grains 40 to the number of grains, the fewer the number of the standard grains 40, and the smaller the insertion density of the standard grains 40 in the conventional grains 20.
[0067] Exemplarily, in this embodiment, the ratio of the number of the benchmark crystal grains 40 to the number of the crystal grains is 1 / 400-1 / 500.
[0068] Designing the ratio of the number of benchmark grains 40 to the number of grains to the above-mentioned value can ensure that the insertion density of the benchmark grains 40 in the conventional grains 20 is relatively high, so that the sorting machine has more points to locate, which can effectively prevent the misalignment of the mapping diagram and the actual scan diagram in the sorting machine, reduce the rescanning of the sorting machine, improve the utilization rate, and thus reduce the overall yield and cost.
[0069] Figure 3 for Figure 2 A magnified image of area A, combined with Figure 3 In this embodiment, in the first direction a, there are 19 to 29 regular grains 20 between two adjacent model grains 40. In the second direction b, there are 13 to 23 regular grains 20 between two adjacent model grains 40.
[0070] In the above implementation, since the grains are arranged in a matrix along the first direction a and the second direction b, respectively, and the arrangement of the model grains 40 and the conventional grains 20 is cyclic, by determining the arrangement rules of the model grains 40 and the conventional grains 20 in the first direction a and the second direction b, the arrangement of the model grains 40 and the conventional grains 20 in the entire wafer can be determined.
[0071] For example, in this embodiment, in the first direction a, there are 24 regular grains 20 between two adjacent model grains 40 , and in the second direction b, there are 18 regular grains 20 between two adjacent model grains 40 .
[0072] The arrangement pattern of the model grains 40 and the conventional grains 20 in the first direction a and the second direction b is designed in this way, which can ensure that the insertion density of the model grains 40 in the conventional grains 20 is relatively high, so that the sorting machine has more points to locate, which can effectively prevent the misalignment of the mapping diagram and the actual scan diagram in the sorting machine, reduce the rescanning of the sorting machine, improve the utilization rate, and thus reduce the overall yield and cost.
[0073] Figure 4 for Figure 2 A magnified view of area B, combined with Figure 4 In this embodiment, the reference grain 30 is close to the sorting reference point 50 of the wafer, and the reference grain 30 is any one of the grains in a circle adjacent to the sorting reference point 50 .
[0074] In the above implementation, the reference die 30 is arranged close to the sorting reference point 50, so that the test machine can automatically identify and locate the (0, 0) point, thereby avoiding manual point setting errors and causing problems such as misalignment.
[0075] Figure 5 A schematic diagram of the structure of a benchmark die 40 provided in an embodiment of the present disclosure, Figure 5 The upper side is a top view of the model die 40. Figure 5 The lower side is the AA direction cross-section of the benchmark grain 40, combined with Figure 5 In this embodiment, the model crystal grain 40 includes a substrate 60, an epitaxial layer 70 and a model primary electrode 410 stacked in sequence. The model primary electrode 410 includes a first section 411 and a second section 412, and the first section 411 and the second section 412 have an angle therebetween, and the first section 411 and the second section 412 intersect.
[0076] In the above implementation, the primary electrode of the standard grain 40 is designed as a standard primary electrode 410, which is different in shape from the primary electrode of the conventional grain 20, so that the sorting machine can quickly and accurately identify the standard grain 40. In addition, the standard primary electrode 410 includes a first section 411 and a second section 412, and there is an angle between the first section 411 and the second section 412, and the first section 411 and the second section 412 intersect, which can facilitate the sorting machine to identify on the one hand, and on the other hand, the structure is relatively simple, which will not increase the difficulty of preparation too much.
[0077] In some examples, the length direction of the first segment 411 is consistent with the first direction a, and the length direction of the second segment 412 is consistent with the second direction b.
[0078] In the above implementation, the first section 411 and the second section 412 are perpendicular to each other, which can maximize the difference between the standard primary electrode 410 of the standard grain 40 and the primary electrode of the conventional grain 20. In addition, the extension direction of the first section 411 and the second section 412 is designed in this way, which can facilitate the suction arm to identify the first section 411 and the second section 412 when moving along the first direction a and the second direction b.
[0079] In some other examples, the first section 411 and the second section 412 may not be perpendicular to each other, and the angle between them may be an acute angle or an obtuse angle, which is not limited in the present disclosure.
[0080] In other embodiments, the benchmark primary electrode 410 also includes a third segment, the end of the third segment is connected to the first segment 411, and the length direction of the third segment is consistent with the second direction b, that is, the third segment is parallel to the second segment 412, and the third segment is perpendicular to the first segment 411.
[0081] In the above implementation, after the third section is added, the difference between the benchmark primary electrode 410 of the benchmark die 40 and the primary electrode of the conventional die 20 can be further improved.
[0082] In addition, the standard primary electrode 410 may not include the first section 411, the second section 412, and the third section, but may be in other shapes, such as a circle or a triangle, etc. It is only necessary that the shape of the standard primary electrode 410 is different from that of the primary electrode of the conventional crystal grain 20, so that the sorting machine can quickly and accurately identify the standard crystal grain 40.
[0083] Continue to see Figure 5 In this embodiment, the epitaxial layer 70 includes a first semiconductor layer 710 and a second semiconductor layer 720 stacked in sequence. The first semiconductor layer 710 and the second semiconductor layer 720 both have a groove 80 extending to the substrate 60 at their outer edges.
[0084] One of the first semiconductor layer 710 and the second semiconductor layer 720 is a p-type layer, and the other of the first semiconductor layer 710 and the second semiconductor layer 720 is an n-type layer.
[0085] In this embodiment, the first semiconductor layer 710 is a p-type layer, and the second semiconductor layer 720 is an n-type layer.
[0086] For example, the first semiconductor layer 710 is a p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 3 μm.
[0087] For example, the second semiconductor layer 720 is an n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.
[0088] In this embodiment, an active layer is further provided between the first semiconductor layer 710 and the second semiconductor layer 720 , and the active layer may be a multi-quantum well layer.
[0089] In this embodiment, the multi-quantum well layer includes quantum well layers and quantum barrier layers that are grown alternately, and the Al content in the quantum well layers and the quantum barrier layers is different. The multi-quantum well layer may include 3 to 8 periods of quantum well layers and quantum barrier layers that are alternately stacked.
[0090] Exemplarily, the multi-quantum well layer includes five periods of quantum well layers and quantum barrier layers stacked alternately.
[0091] Exemplarily, the thickness of the multi-quantum well layer may be 150 nm to 200 nm.
[0092] In this embodiment, the benchmark crystal grain 40 further includes a reflective layer 90 , and the reflective layer 90 covers the benchmark primary electrode 410 and the epitaxial layer 70 .
[0093] Exemplarily, the reflective layer 90 may be a distributed Bragg reflector (DBR), which includes a plurality of SiO2 layers and TiO2 layers that are periodically and alternately stacked, and the number of periods of the distributed Bragg reflector may be between 20 and 50.
[0094] In this embodiment, the number of periods of the distributed Bragg reflector is 32.
[0095] In addition to the passivation function, the distributed Bragg reflector is also used to reflect the light emitted from the active layer to the distributed Bragg reflector back to the direction of the epitaxial layer 70, thereby improving the light extraction effect.
[0096] Figure 6 A schematic diagram of the structure of a reference grain 30 provided in an embodiment of the present disclosure, Figure 6 The upper side is a top view of the reference grain 30. Figure 6 The lower side is a cross-sectional view of the reference grain 30 in the BB direction. Figure 6 In this embodiment, the reference crystal grain 30 includes a substrate 60, an epitaxial layer 70 and a reference primary electrode 310 which are stacked in sequence. The reference primary electrode 310 includes an arrow portion 311 and a lead segment 312, one end of the lead segment 312 is connected to the arrow portion 311, and the length direction of the lead segment 312 is consistent with the direction of the arrow portion 311.
[0097] In the above implementation, the primary electrode of the reference grain 30 is designed as a reference primary electrode 310, which is different in shape from the primary electrode of the conventional grain 20, so that the sorting machine can quickly and accurately identify the reference grain 30. In addition, the reference primary electrode 310 includes an arrow portion 311 and a lead segment 312, one end of the lead segment 312 is connected to the arrow portion 311, and the length direction of the lead segment 312 is consistent with the direction of the arrow portion 311, which can facilitate the sorting machine to identify on the one hand, and on the other hand, the structure is relatively simple, which will not increase the difficulty of preparation too much.
[0098] In addition, the reference primary electrode 310 may not include the arrow portion 311 and the lead segment 312, but may be in other shapes, such as a circle or a triangle, etc. It is only necessary that the shape of the reference primary electrode 310 is different from the primary electrode of the conventional crystal grain 20 and the standard primary electrode 410 of the standard crystal grain 40, so that the sorting machine can quickly and accurately identify the reference crystal grain 30.
[0099] Continue to see Figure 6 In this embodiment, the epitaxial layer 70 includes a first semiconductor layer 710 and a second semiconductor layer 720 stacked in sequence. The first semiconductor layer 710 and the second semiconductor layer 720 both have a groove 80 extending to the substrate 60 at their outer edges.
[0100] One of the first semiconductor layer 710 and the second semiconductor layer 720 is a p-type layer, and the other of the first semiconductor layer 710 and the second semiconductor layer 720 is an n-type layer.
[0101] In this embodiment, the first semiconductor layer 710 is a p-type layer, and the second semiconductor layer 720 is an n-type layer.
[0102] For example, the first semiconductor layer 710 is a p-type GaN layer, and the thickness of the p-type GaN layer may be 0.5 μm to 3 μm.
[0103] For example, the second semiconductor layer 720 is an n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 3 μm.
[0104] In this embodiment, an active layer is further provided between the first semiconductor layer 710 and the second semiconductor layer 720 , and the active layer may be a multi-quantum well layer.
[0105] In this embodiment, the multi-quantum well layer includes quantum well layers and quantum barrier layers that are grown alternately, and the Al content in the quantum well layers and the quantum barrier layers is different. The multi-quantum well layer may include 3 to 8 periods of quantum well layers and quantum barrier layers that are alternately stacked.
[0106] Exemplarily, the multi-quantum well layer includes five periods of quantum well layers and quantum barrier layers stacked alternately.
[0107] Exemplarily, the thickness of the multi-quantum well layer may be 150 nm to 200 nm.
[0108] In this embodiment, the reference crystal grain 30 further includes a reflective layer 90 , and the reflective layer 90 covers the reference primary electrode 310 and the epitaxial layer 70 .
[0109] Exemplarily, the reflective layer 90 may be a distributed Bragg reflector (DBR), which includes a plurality of SiO2 layers and TiO2 layers that are periodically and alternately stacked, and the number of periods of the distributed Bragg reflector may be between 20 and 50.
[0110] In this embodiment, the number of periods of the distributed Bragg reflector is 32.
[0111] In addition to the passivation function, the distributed Bragg reflector is also used to reflect the light emitted from the active layer to the distributed Bragg reflector back to the direction of the epitaxial layer 70, thereby improving the light extraction effect.
[0112] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0113] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. A wafer, characterized in that: include: A plurality of sorting regions (10); A plurality of crystal grains are arranged in each of the sorting regions (10), the plurality of crystal grains are arranged in a matrix along a first direction and a second direction, the first direction and the second direction are perpendicular to each other, and the plurality of crystal grains include conventional crystal grains (20), reference crystal grains (30) and standard crystal grains (40); Each of the conventional crystal grains (20) is evenly arranged in the corresponding sorting area (10); The reference crystal grain (30) is located in the middle of the corresponding sorting area (10), and the reference crystal grain (30) is close to the sorting reference point (50) of the wafer, and the reference crystal grain (30) is used for the sorting machine to identify the sorting reference position; Each of the benchmark crystal grains (40) is evenly spaced and arranged in the corresponding sorting area (10), and the benchmark crystal grains (40) are used for the sorting machine to identify the sorting benchmark position.
2. The wafer according to claim 1, characterized in that The ratio of the number of the benchmark crystal grains (40) to the number of the crystal grains is 1 / 200 to 1 / 800.
3. The wafer according to claim 1, characterized in that In the first direction, there are 19 to 29 conventional grains (20) between two adjacent standard grains (40); In the second direction, there are 13 to 23 conventional grains (20) between two adjacent model grains (40).
4. The wafer according to claim 1, characterized in that The model crystal grain (40) comprises a substrate (60), an epitaxial layer (70) and a model primary electrode (410) stacked in sequence; The benchmark primary electrode (410) comprises a first section (411) and a second section (412), wherein an angle is formed between the first section (411) and the second section (412), and the first section (411) and the second section (412) intersect.
5. The wafer according to claim 4, characterized in that The length direction of the first section (411) is consistent with the first direction; The length direction of the second section (412) is consistent with the second direction.
6. The wafer according to claim 4, characterized in that The epitaxial layer (70) comprises a first semiconductor layer (710) and a second semiconductor layer (720) which are stacked in sequence; The first semiconductor layer (710) and the second semiconductor layer (720) both have grooves (80) at their outer edges extending to the substrate (60).
7. The wafer according to claim 4, characterized in that The benchmark crystal grain (40) further includes a reflective layer (90); The reflective layer (90) covers the outside of the benchmark primary electrode (410) and the epitaxial layer (70).
8. The wafer according to claim 1, characterized in that The reference crystal grain (30) comprises a substrate (60), an epitaxial layer (70) and a reference primary electrode (310) which are stacked in sequence; The reference primary electrode (310) comprises an arrow portion (311) and a lead segment (312), one end of the lead segment (312) is connected to the arrow portion (311), and the length direction of the lead segment (312) is consistent with the direction of the arrow portion (311).
9. The wafer according to claim 8, characterized in that The epitaxial layer (70) comprises a first semiconductor layer (710) and a second semiconductor layer (720) which are stacked in sequence; The first semiconductor layer (710) and the second semiconductor layer (720) both have grooves (80) at their outer edges extending to the substrate (60).
10. The wafer according to claim 9, characterized in that The reference crystal grain (30) further includes a reflective layer (90); The reflective layer (90) covers the reference primary electrode (310) and the epitaxial layer (70).