Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, and the packaging structure comprises a frame unit which comprises a plurality of pins, the pins comprise functional pins and non-functional pins, the functional pins and the non-functional pins are arranged at intervals, the functional pins are located in the periphery of the frame unit, and the non-functional pins extend to the periphery of the frame unit; the chip is positioned on the functional pin of the frame unit and is electrically connected with the functional pin; the plastic package layer wraps the chip and the frame unit and exposes the side face, located at the periphery position of the frame unit, of the non-functional pin and the bottom face of the functional pin, and the plastic package layer, the chip and the frame unit form a plastic package body; and the shielding layer is positioned on the top surface and the side surface of the plastic package body and is connected with the side surface of the non-functional pin exposed out of the plastic package layer. The bottom of the plastic package body is provided with the non-functional pin, and the shielding layer is connected with the non-functional pin, so that the non-functional pin and the shielding layer jointly play an electromagnetic shielding role, electromagnetic shielding is realized on each surface of the chip, the shielding effect is improved, and the performance of the packaging structure is correspondingly improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor packaging technology, and in particular to a packaging structure and a packaging method. Background Art

[0002] With the rapid development of packaging technology, packaging products are gradually developing in the direction of miniaturization, high density and high integration. High-frequency chips will generate strong electromagnetic waves during transportation and transmission, which often cause interference or noise to other chips inside the packaged product or electronic components outside the packaged product. Moreover, when the integration of electronic components is too high, the distance between the signal transmission lines of the electronic components is getting closer and closer, resulting in increasingly serious electromagnetic interference (EMI) problems between chips outside or inside the packaged product.

[0003] Therefore, the existence of electromagnetic interference problems means that the performance of the packaging structure needs to be improved. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method to improve the performance of the packaging structure.

[0005] To solve the above problems, an embodiment of the present invention provides a packaging structure, including: a frame unit, including a plurality of pins, wherein the pins include spaced functional pins and non-functional pins, wherein the functional pins are located inside the perimeter of the frame unit, and the non-functional pins extend to the perimeter of the frame unit; a chip, located on the functional pins of the frame unit and electrically connected to the functional pins; a plastic encapsulation layer, covering the chip and the frame unit, and exposing the side surfaces of the non-functional pins located at the perimeter of the frame unit and the bottom surface of the functional pins, wherein the plastic encapsulation layer, the chip and the frame unit constitute a plastic encapsulation body; a shielding layer, located on the top surface and the side surfaces of the plastic encapsulation body, wherein the shielding layer is connected to the side surfaces of the non-functional pins exposed to the plastic encapsulation layer.

[0006] Correspondingly, an embodiment of the present invention also provides a packaging method, comprising: providing a frame unit, comprising a plurality of pins, the pins comprising spaced functional pins and non-functional pins, the functional pins being located inside the perimeter of the frame unit, and the non-functional pins extending to the perimeter position of the frame unit; arranging a chip on the functional pins, the chip being electrically connected to the functional pins; forming a first plastic encapsulation layer covering the chip and the frame unit, and obtaining a plastic encapsulation body consisting of the first plastic encapsulation layer, the chip and the frame unit, wherein in the plastic encapsulation body, the first plastic encapsulation layer exposes the side surfaces of the non-functional pins located at the perimeter position of the frame unit and the bottom surfaces of the functional pins; forming a shielding layer covering the top surface and side surfaces of the plastic encapsulation body, the shielding layer being connected to the side surfaces of the non-functional pins exposed to the first plastic encapsulation layer.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] In the packaging structure provided by the embodiment of the present invention, the pins of the frame unit include spaced functional pins and non-functional pins, and the non-functional pins extend to the perimeter of the frame unit so that the sides of the non-functional pins are exposed by the plastic packaging layer, and the shielding layer covers the top and side surfaces of the plastic packaging body, and the shielding layer can be connected to the non-functional pins through the exposed sides. Therefore, the bottom of the plastic packaging body of the packaging structure has non-functional pins, and the non-functional pins and the shielding layer jointly play the role of electromagnetic shielding, thereby realizing electromagnetic shielding on all sides of the chip and improving the shielding effect; moreover, the functional pins are located inside the perimeter of the frame unit, so that the sides of the functional pins are covered by the plastic packaging layer, and the plastic packaging layer can isolate the shielding layer from the functional pins, thereby reducing the probability of short circuit between the functional pins caused by the connection between the shielding layer and the functional pins, thereby reducing the impact on the chip performance; in summary, the performance of the packaging structure can be improved.

[0009] In the packaging method provided by the embodiment of the present invention, the pins of the frame unit include spaced functional pins and non-functional pins, and the non-functional pins extend to the perimeter position of the frame unit, then a first plastic packaging layer covering the chip and the frame unit is formed and a plastic packaging body is obtained. In the plastic packaging body, the first plastic packaging layer exposes the side of the non-functional pin located at the perimeter position of the frame unit, so that the shielding layer covering the plastic packaging body can be connected to the side of the non-functional pin exposed to the first plastic packaging layer. Therefore, the bottom of the plastic packaging body has non-functional pins, and the non-functional pins and the shielding layer jointly play the role of electromagnetic shielding, realizing electromagnetic shielding on all sides of the chip, thereby improving the shielding effect; moreover, the functional pins are located inside the perimeter of the frame unit, so that the side of the functional pins is covered by the first plastic packaging layer, and the first plastic packaging layer can isolate the shielding layer from the functional pins, thereby reducing the probability of short circuit between the functional pins caused by the connection between the shielding layer and the functional pins; in summary, the packaging method can improve the performance of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a bottom view of the second surface of the frame unit in the first embodiment of the packaging structure of the present invention;

[0011] Figure 2 yes Figure 1 A cross-sectional view at the position A1-A2;

[0012] Figure 3 is a cross-sectional view of a second embodiment of a packaging structure of the present invention;

[0013] Figure 4 is a cross-sectional view of a third embodiment of a packaging structure of the present invention;

[0014] Figure 5 is a cross-sectional view of a fourth embodiment of a packaging structure of the present invention;

[0015] Figures 6 to 15 is a schematic diagram corresponding to each step in an embodiment of a packaging method of the present invention;

[0016] Figures 16 to 20 It is a schematic diagram corresponding to each step in another embodiment of the packaging method of the present invention. DETAILED DESCRIPTION

[0017] As can be seen from the background technology, due to the increasingly serious electromagnetic interference problem, the performance of the packaging structure needs to be improved.

[0018] In order to improve the electromagnetic interference problem, one approach is to cover the plastic package with an electromagnetic shielding layer. However, for a pinless plastic package, such as a Quad Flat No-lead Package (QFN), the functional pins corresponding to the chip are exposed on all sides of the plastic package. If an electromagnetic shielding layer is directly covered on the plastic package, the electromagnetic shielding layer will directly contact the exposed side of the pins, and because the electromagnetic shielding layer is conductive, a short circuit will occur between the functional pins, affecting the performance of the package structure.

[0019] In order to solve the technical problem, an embodiment of the present invention provides a packaging structure, including: a frame unit, including a plurality of pins, the pins including spaced functional pins and non-functional pins, the functional pins being located inside the perimeter of the frame unit, and the non-functional pins extending to the perimeter of the frame unit; a chip being located on the functional pins of the frame unit and electrically connected to the functional pins; a plastic encapsulation layer covering the chip and the frame unit, and exposing the side surfaces of the non-functional pins located at the perimeter of the frame unit and the bottom surface of the functional pins, the plastic encapsulation layer, the chip and the frame unit constituting a plastic encapsulation body; a shielding layer being located on the top surface and the side surfaces of the plastic encapsulation body, the shielding layer being connected to the side surfaces of the non-functional pins exposed to the plastic encapsulation layer.

[0020] In the packaging structure provided by the embodiment of the present invention, the pins of the frame unit include spaced functional pins and non-functional pins, and the non-functional pins extend to the perimeter of the frame unit so that the sides of the non-functional pins are exposed by the plastic packaging layer, and the shielding layer covers the top and side surfaces of the plastic packaging body, and the shielding layer can be connected to the non-functional pins through the exposed sides. Therefore, the bottom of the plastic packaging body of the packaging structure has non-functional pins, and the non-functional pins and the shielding layer jointly play the role of electromagnetic shielding, thereby realizing electromagnetic shielding on all sides of the chip and improving the shielding effect; moreover, the functional pins are located inside the perimeter of the frame unit, so that the sides of the functional pins are covered by the plastic packaging layer, and the plastic packaging layer can isolate the shielding layer from the functional pins, thereby reducing the probability of short circuit between the functional pins caused by the connection between the shielding layer and the functional pins, thereby reducing the impact on the chip performance; in summary, the performance of the packaging structure can be improved.

[0021] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0022] refer to Figure 1 and Figure 2 , Figure 1 is a bottom view of the second surface of the frame unit in the first embodiment of the packaging structure of the present invention, Figure 2 yes Figure 1Cross-sectional view at position A1-A2.

[0023] In this embodiment, the packaging structure includes: a frame unit 260, including a plurality of pins 250 (such as Figure 2 As shown), the pins 250 include spaced functional pins 200 and non-functional pins 201, and the functional pins 200 are located at the perimeter 260C of the frame unit 260 (as shown in FIG. Figure 1 , the non-functional pin 201 extends to the perimeter 260C of the frame unit 260; the chip 210 is located on the functional pin 200 of the frame unit 260 and is electrically connected to the functional pin 200; the plastic encapsulation layer 203 covers the chip 210 and the frame unit 260, and exposes the side surface of the non-functional pin 201 located at the perimeter 260C of the frame unit 260 and the bottom surface of the functional pin 200 (not marked), the plastic encapsulation layer 203, the chip 210 and the frame unit 260 constitute a plastic encapsulation body (not marked); the shielding layer 204 is located on the top and side surfaces of the plastic encapsulation body, and the shielding layer 204 is connected to the side surfaces of the non-functional pin 201 exposed to the plastic encapsulation layer 203.

[0024] In this embodiment, the package structure is a leadless package structure, including but not limited to a Quad Flat No-lead Package (QFN). For example, in other embodiments, the package structure may also be a Dual Flat No-lead Package (DFN) or a Land Grid Array (LGA).

[0025] The frame unit 260 is used as a carrier for packaging the chip 210 , and the frame unit 260 is used to prepare a single package.

[0026] The frame unit 260 includes a first surface 260A and a second surface 260B opposite to the first surface 260A. The first surface 260A is used for mounting the chip 210 .

[0027] In this embodiment, the frame unit 260 is made of a material having good electrical conductivity, thermal conductivity and mechanical strength, and the material of the frame unit 260 may include metal materials such as copper, copper alloy or nickel-iron alloy. As an example, the material of the frame unit 260 is copper. It should be noted that in other embodiments, under the conditions of satisfying electrical conductivity, thermal conductivity and mechanical strength, the frame unit may also be made of a material having good wettability with solder.

[0028] In this embodiment, the packaging structure includes one frame unit 260. In other embodiments, the packaging structure may also include multiple frame units according to actual needs.

[0029] In this embodiment, the frame unit 260 is a frame structure without a base, thereby providing more space for the setting of non-functional pins 201 and facilitating the setting of non-functional pins 201 at different positions on the bottom surface of the plastic package body, thereby ensuring that the non-functional pins 201 can play an electromagnetic shielding role.

[0030] The non-functional pin 201 extends to the perimeter 260C position of the frame unit 260, so that the side of the non-functional pin 201 is exposed by the plastic packaging layer 203, and the shielding layer 204 covers the top and side surfaces of the plastic packaging body 203. The shielding layer 204 can be connected to the non-functional pin 201 through the exposed side surface. Therefore, the bottom of the plastic packaging body of the packaging structure has a non-functional pin 201, and the non-functional pin 201 and the shielding layer 204 jointly play a role in electromagnetic shielding, and electromagnetic shielding is realized on each side of the chip 210 (for example, taking the packaging structure as a square as an example, the shielding layer 204 can realize electromagnetic shielding on the six sides of the plastic packaging body), thereby improving the shielding effect and improving the performance of the packaging structure.

[0031] In this embodiment, the non-functional pins 201 are arranged vertically and horizontally in the frame unit 260, that is, the non-functional pins 201 include horizontal (such as Figure 1 The non-functional pin 201 extending in the longitudinal direction (as shown in the X direction) is connected to the non-functional pin 201 extending in the longitudinal direction (as shown in the Figure 1 The non-functional pin 201 extends in the Y direction (as shown in the figure), thereby performing electromagnetic shielding in the horizontal and vertical directions, so that the electromagnetic shielding structure composed of the shielding layer 204 and the non-functional pin 201 is more like a Faraday cage, thereby improving the shielding effect.

[0032] In this embodiment, there is a gap between the non-functional pins 201 extending laterally and the non-functional pins 201 extending longitudinally, thereby reducing the complexity of preparing the frame unit 260. For example, the frame unit 260 can be prepared using an integrated original frame.

[0033] In other embodiments, the non-functional pins extending laterally and the non-functional pins extending longitudinally are crisscrossed to form a grid, thereby further improving the shielding effect.

[0034] It is understandable that the larger the surface area of ​​the non-functional pin 201 (for example, the larger the width, the longer the length, and the greater the density of the non-functional pin 201), the better the shielding effect it provides. Therefore, the surface area of ​​the non-functional pin 201 can be increased as much as possible according to actual circumstances.

[0035] In this embodiment, the bottom surfaces of the functional pin 200 and the non-functional pin 201 are flush with each other, so that the plastic packaging layer 203 exposes the bottom surface of the non-functional pin 201. Therefore, when the packaging structure is welded to the substrate, the non-functional pin 201 can also be used for welding, thereby improving the welding strength and also helping to enhance the heat conduction effect of the frame unit 260 to the outside world.

[0036] It should be noted that the bottom surface of the pin 250 is the pin surface on the second surface 260B side of the frame unit 260 , and the top surface of the pin 250 is the pin surface on the first surface 260A side of the frame unit 260 .

[0037] In other embodiments, the bottom surface of the non-functional pin may also be higher than the bottom surface of the functional pin, so that the plastic packaging layer covers the bottom surface of the non-functional pin.

[0038] In this embodiment, the pins 250 include chip pins (not shown), which are pins used to connect to the chip 210, and the chip pins include function pins 200. It should be noted that the function pins 200 refer to the pins of the chip except the ground pins.

[0039] In this embodiment, the functional pin 200 is located inside the perimeter 260C of the frame unit 260, so that the side of the functional pin 200 is covered by the plastic layer 203. The plastic layer 203 can isolate the shielding layer 204 and the functional pin 200, thereby reducing the probability of a short circuit between the functional pins 200 caused by the connection between the shielding layer 204 and the functional pin 200, thereby improving the reliability of the packaging structure.

[0040] In this embodiment, the top surface of the functional pin 200 is higher than the top surface of the non-functional pin 201, so that the non-functional pin 201 and the chip 210 have a certain distance in the thickness direction of the frame unit 260, so as to reduce the impact of the non-functional pin 201 on the performance of the chip 210; moreover, when the chip 210 is soldered to the functional pin 200 using solder, it is also beneficial to reduce the probability of the solder being connected to the non-functional pin 201, thereby reducing the probability of a short circuit between the non-functional pin 201 and the chip 210.

[0041] like Figure 2 As shown, in this embodiment, along the thickness direction of the frame unit 260, the functional pin 200 includes a top functional pin 200t located on one side of the first surface 260A of the frame unit 260, and a bottom functional pin 200b located at the bottom of the top functional pin 200t, and the line width of the top functional pin 200t is greater than the line width of the bottom functional pin 200b.

[0042] The bottom functional pin 200b located on the second surface 260B of the frame unit 260 has a smaller line width, which is beneficial to reducing burrs on the surface of the bottom functional pin 200b. Moreover, the area occupied by the bottom functional pin 200b is smaller, which also provides more space for the setting of the non-functional pin 201.

[0043] The line width of the top functional pin 200t is larger, providing more bearing surface for setting the chip 210. Moreover, when the chip 210 is soldered to the functional pin 200 using solder, the area of ​​the solder after melting will become larger, so increasing the line width of the top functional pin 200t is also conducive to ensuring that the solder can always be located on the top functional pin 200t, thereby improving the reliability of the package.

[0044] The line width of the top functional pin 200t is greater than the line width of the bottom functional pin 200b. The bottom functional pin 200b exposes part of the bottom surface of the top functional pin 200t, which is beneficial to increase the bonding strength between the functional pin 200 and the plastic packaging layer 203.

[0045] It should be noted that the line width refers to the dimension in the direction parallel to the top surface of the functional pin 200 .

[0046] In this embodiment, the longitudinal section of the functional pin 200 is T-shaped, which increases its structural symmetry, thereby facilitating the improvement of the stability of the functional pin 200 and increasing its top area. In other embodiments, the longitudinal sections of the top functional pin and the bottom functional pin may also be L-shaped.

[0047] In this embodiment, the pin 250 further includes a ground pin 202 , and the ground pin 202 is used for grounding.

[0048] Specifically, the chip pins include a functional pin 200 and a ground pin 202 . In other words, the ground pin 202 is used to connect to the chip 210 .

[0049] The ground pin 202 is flush with the top surface of the functional pin 200 , thereby providing a flat surface for the chip 210 to be disposed, thereby improving the reliability of the combination of the chip 210 and the frame unit 260 .

[0050] In this embodiment, the ground pin 202 is connected to the shielding layer 204 , so that the shielding layer 204 is grounded through the ground pin 202 .

[0051] The ground pin 202 is used to connect a ground signal, so that the ground pin 202 is connected to the shielding layer 204, so that the shielding layer 204 can be connected to the ground signal through the ground pin 202. For example, the ground pin 202 is usually used to be soldered to a substrate (e.g., a PCB board or a packaging substrate, etc.) and connected to the ground signal through the substrate.

[0052] In this embodiment, the ground pin 202 extends to a peripheral position 260C of the frame unit 260 .

[0053] Correspondingly, the plastic encapsulation layer 203 also exposes the side surface of the ground pin 202 located at the perimeter 260C of the frame unit 260 , and the shielding layer 204 is connected to the side surface of the ground pin 202 exposed to the plastic encapsulation layer 203 .

[0054] It should be noted that, in this embodiment, the ground pin 202 is in direct contact with the shielding layer 204. In other embodiments, the ground pin may also be electrically connected to the shielding layer through other conductive components. For example, the electrical connection between the ground pin and the shielding layer located on the top surface of the plastic packaging layer may be achieved through a conductive column disposed in the plastic packaging layer.

[0055] In this embodiment, along the thickness direction of the frame unit 260, the ground pin 202 includes a top ground pin 202t located on one side of the first surface 260A of the frame unit 260, and a bottom ground pin 202b located at the bottom of the top ground pin 202t, the top ground pin 202t and the top functional pin 200t are located at the same height position, and the bottom ground pin 202b and the bottom functional pin 200b are located at the same height position.

[0056] In this embodiment, the top ground pin 202 t and the bottom ground pin 202 b partially overlap, thereby providing more space for the arrangement of the non-functional pin 201 .

[0057] It should be noted that in the frame unit 260, the spacing between adjacent pins 250 should not be too small, otherwise it is easy to increase the risk of short circuit between adjacent pins 250. Specifically, when the bottom surface of the pin 250 exposed to the plastic encapsulation layer 203 has a solder wetting layer, it is easy to cause the solder wetting layers on adjacent pins 250 to contact each other, for example, it is easy to cause tinning problems. In this embodiment, the spacing between adjacent pins 250 is greater than one times the width of the pin 250.

[0058] The chip 210 is electrically connected to the functional pin 200, thereby obtaining a packaging structure with certain functions and realizing the functional requirements of the product.

[0059] Specifically, the chip 210 is located on a side of the first surface 260A of the frame unit 260 .

[0060] In this embodiment, the chip 210 is a radio frequency (RF) chip. An electromagnetic shielding structure is provided around the RF chip to reduce the probability of electromagnetic interference between the RF chip and other surrounding devices. In other embodiments, the chip 210 may also be other types of chips.

[0061] In this embodiment, the chip 210 is flipped onto the functional pin 200, thereby eliminating the need for a base. Accordingly, the front of the chip 210 faces the functional pin 200, and the front of the chip 210 has a connection terminal (e.g., a pad), thereby achieving electrical connection with the functional pin 200 through the connection terminal.

[0062] In other embodiments, the back side of the chip may be directed toward the functional pins and disposed on the functional pins. For example, the connection terminals on the front side of the chip may be connected to the back side of the chip.

[0063] It should be noted that the chip 210 includes a front side and a back side disposed opposite to each other, and the back side of the chip 210 refers to the back side of the substrate, and the front side of the chip 210 refers to a side surface of the chip 210 having a functional surface.

[0064] In this embodiment, since the ground pin 202 is a chip pin, the chip 210 is also disposed on the ground pin 202 and electrically connected to the ground pin 202 , thereby meeting the grounding requirement of a specific connection terminal of the chip 210 .

[0065] In this embodiment, the packaging structure further includes: conductive bumps 230 located between the chip 210 and the functional pins 200 , and between the chip 210 and the ground pins 202 , for achieving the combination and electrical connection between the chip 210 and the frame unit 260 .

[0066] In this embodiment, a plurality of (eg, two) conductive bumps 230 are located on the same functional pin 200 .

[0067] The conductive bumps 230 connected to the same electrical signal are connected to the same functional pin 200 , which reduces the number of functional pins 200 and provides more space for the arrangement of non-functional pins 201 .

[0068] In this embodiment, the longitudinal section of the functional pin 200 is T-shaped so that a plurality of conductive bumps 230 are disposed on the top functional pin 200 t.

[0069] In other embodiments, only one conductive bump may be disposed on one functional pin, for example, the conductive bumps correspond to the functional pins one by one.

[0070] In this embodiment, the conductive bump 230 includes a copper pillar 230 a and a tin cap 230 b located on the top surface of the copper pillar 230 a , and the tin cap 230 b is in contact with the pin 250 .

[0071] The plastic packaging layer 203 is used to protect the components covered by it, and plastic packaging the chip 210 and the frame unit 260 into a whole to obtain a plastic packaging body.

[0072] In this embodiment, the material of the plastic encapsulation layer 203 is a molding material, such as epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties and low cost. In other embodiments, the plastic encapsulation layer can also be made of other suitable packaging materials.

[0073] In this embodiment, the plastic packaging layer 203 exposes the side surface of the non-functional pin 201 located at the perimeter 260C of the frame unit 260 , so that the non-functional pin 201 is connected to the shielding layer 204 .

[0074] In this embodiment, the plastic layer 203 also exposes the bottom surface of the functional pin 200 so as to subsequently weld the exposed pin 250 to the substrate, and it is also beneficial to improve the heat conduction effect of the frame unit 260 to the outside.

[0075] In this embodiment, the plastic packaging layer 203 exposes the back side of the chip 210 , thereby reducing the thickness of the plastic packaging body and also facilitating improving the heat dissipation effect of the chip 210 when it is working.

[0076] In other embodiments, the plastic packaging layer may also cover the back side of the chip.

[0077] The shielding layer 204 is electrically connected to the non-functional pin 201 , thereby forming an electromagnetic shielding structure.

[0078] In this embodiment, in order to achieve a shielding effect, the material of the shielding layer 204 may be metal, for example, the material of the shielding layer 204 includes one or more metals such as copper, tin, aluminum, zinc, tungsten, etc. In other embodiments, the material of the shielding layer 204 may also be an alloy, for example, an alloy of stainless steel, etc.

[0079] In this embodiment, the top surface of the plastic package body has a roughened surface (not shown).

[0080] Accordingly, the shielding layer 204 covers the roughened surface, which is beneficial to increase the bonding force between the shielding layer 204 and the top surface of the plastic package body.

[0081] In one embodiment, both the top surface of the plastic encapsulation layer 203 and the back surface of the chip 210 have a roughened surface. In another embodiment, only the back surface of the chip has a roughened surface. In other embodiments, when the back surface of the chip is covered by the plastic encapsulation layer, only the top surface of the plastic encapsulation layer has a roughened surface.

[0082] It should be noted that, in order to improve the roughening effect, the groove depth of the roughened surface is greater than or equal to 8 microns.

[0083] It should also be noted that the depth of the grooves (not shown) of the roughened surface should not be too large, otherwise it is easy to damage the chip 210. Therefore, in this embodiment, the depth of the grooves of the roughened surface is 8 microns to 15 microns.

[0084] In other embodiments, the top surface of the plastic package body may not have a roughened surface.

[0085] In this embodiment, the packaging structure further includes: a solder wetting layer 220 located on the bottom surface of the pin 250 exposed to the plastic packaging layer 203 .

[0086] The solder wetting layer 220 is used as a protective plating layer to protect the pins 250 exposed to the plastic layer 203, reduce the exposed area of ​​the pins 250 (ie, the copper-clad area), and reduce the probability of oxidation or corrosion of the pins 250, which is beneficial to improving the performance of the packaging structure.

[0087] Moreover, when the pin 250 is subsequently soldered to the substrate by solder, the solder wetting layer 220 has good solder wettability and can guide the flow of the solder, thereby facilitating enhancing the soldering strength between the pin 250 and the substrate.

[0088] In this embodiment, the material of the solder wetting layer 220 may include one or more alloys of tin, nickel, palladium and silver. As an example, the material of the solder wetting layer 220 is tin.

[0089] Figure 3 is a cross-sectional view of a second embodiment of the packaging structure of the present invention.

[0090] The differences between this embodiment and the above embodiment are that the function pin 100 includes a top function pin 100t and a bottom function pin 100b, and the shape of the longitudinal section of the function pin 100 includes an L shape.

[0091] The longitudinal section of the functional pin 100 is L-shaped, and the projection area of ​​the functional pin 100 on the frame unit is reduced, which can provide more space for the arrangement of non-functional pins (not shown), which is conducive to increasing the width of the non-functional pins (for example, Figure 3To improve the shielding effect.

[0092] It should be noted that the same frame unit may include both T-shaped functional pins 100 and L-shaped functional pins 100 .

[0093] It should also be noted that for the detailed description of the packaging structure described in this embodiment, reference may be made to the relevant content in the first embodiment, which will not be repeated here.

[0094] Figure 4 is a cross-sectional view of a third embodiment of the packaging structure of the present invention.

[0095] The differences between this embodiment and the above embodiment are as follows: the functional pin 102 includes a top functional pin 102t and a bottom functional pin 102b, and the non-functional pin 101 is located at the bottom of the top functional pin 102t.

[0096] The non-functional pin 101 is located at the bottom of the top functional pin 102t, and the space at the bottom of the top functional pin 102t can be utilized, which is beneficial to increase the width of the non-functional pin to improve the shielding effect.

[0097] In this embodiment, a non-functional pin 101 of a partial size is located at the bottom of the top functional pin 102t, and the non-functional pin 101 also extends to the side of the functional pin 102, thereby increasing the width of the non-functional pin.

[0098] In other embodiments, according to actual conditions, the non-functional pins of the entire size are located at the bottom of the top functional pins to reduce the volume of the plastic package.

[0099] It should also be noted that for the detailed description of the packaging structure described in this embodiment, reference may be made to the relevant content in the first embodiment, which will not be repeated here.

[0100] Figure 5 is a cross-sectional view of a fourth embodiment of a packaging structure of the present invention.

[0101] The differences between this embodiment and the above embodiment are as follows: the ground pin 104 is connected to any of the non-functional pins 103 ; the shielding layer 106 is connected to the ground pin 104 through the non-functional pin 103 .

[0102] The ground pin 104 is connected to any non-functional pin 103 . The ground pin 104 does not need to extend to the perimeter of the frame unit, which is beneficial to improving the regularity of the arrangement of the chip pins. For example, the chip pins can be arranged in an array.

[0103] In this embodiment, the ground pin 104 includes a top ground pin 104t and a bottom ground pin 104b. The structure of the ground pin 104 is consistent with the functional pin to reduce the processing complexity of the frame unit.

[0104] In other embodiments, the ground pins may also only include top ground pins that are at the same height as the top functional pins.

[0105] In this embodiment, the ground pin 104 is connected to any of the non-functional pins 103 via the solder layer 105 to improve the bonding strength and electrical connection performance of the ground pin 104 and the non-functional pin 103 .

[0106] It should also be noted that for the detailed description of the packaging structure described in this embodiment, reference may be made to the relevant content in the first embodiment, which will not be repeated here.

[0107] Correspondingly, an embodiment of the present invention also provides a packaging method. Figures 6 to 15 It is a schematic diagram corresponding to each step in an embodiment of a packaging method of the present invention.

[0108] refer to Figure 6 , providing chip 310.

[0109] Subsequently, the chip 310 is disposed on the frame unit and electrically connected to the functional pins of the frame unit, thereby obtaining a packaging structure with certain functions and realizing the functional requirements of the product.

[0110] In this embodiment, the chip 310 is a radio frequency chip. By setting an electromagnetic shielding structure around the radio frequency chip, the probability of electromagnetic interference between the radio frequency chip and other surrounding devices is reduced. In other embodiments, the chip 310 may also be other types of chips.

[0111] The chip 310 is subsequently flipped onto the functional pins. Therefore, the method further includes: forming a conductive bump 330 on the front side of the chip 310 .

[0112] The conductive bumps 330 are used to realize the combination and electrical connection between the chip 310 and the frame unit.

[0113] Specifically, the front side of the chip 310 has a connection terminal (eg, a pad), and thus a conductive bump 330 is formed on the connection terminal.

[0114] In other embodiments, the back side of the chip may be directed toward the functional pins and disposed on the functional pins. Accordingly, the connection terminals on the front side of the chip may be connected to the back side of the chip and conductive bumps may be formed on the back side of the chip.

[0115] In this embodiment, the conductive bump 330 includes a copper pillar 330 a and a tin cap 330 b located on the top surface of the copper pillar 330 a , and the tin cap 330 b is used to contact with the pins of the frame unit.

[0116] refer to Figure 7 and Figure 8 , Figure 8 is a bottom view of the second surface of the frame unit 360 in the first embodiment of the present invention, Figure 7 yes Figure 8 A cross-sectional view at the A1-A2 position provides a frame unit 360 including a plurality of pins 350 , wherein the pins 250 include spaced functional pins 300 and non-functional pins 301 , wherein the functional pins 300 are located inside the perimeter 360C of the frame unit 360 , and the non-functional pins extend to the perimeter 360C position of the frame unit 360 .

[0117] In this embodiment, the packaging method is used to form a pinless packaging structure, including but not limited to a quad flat no-lead package. For example, in other embodiments, the packaging structure may also be a double-sided flat no-lead package or a grid array package.

[0118] The frame unit 360 is used as a carrier for packaging the chip 310 , and the frame unit 360 is used to prepare a single package.

[0119] In this embodiment, the step of providing the frame unit 360 includes: providing a frame structure (not shown), the frame structure including a plurality of frame units 360. That is, in the step of providing the frame unit 360, there are a plurality of frame units 360, and the plurality of frame units 360 are connected to each other.

[0120] It should be noted that this is only a diagram, so Figure 7 and Figure 8 Only one frame unit 360 is shown in FIG.

[0121] In other embodiments, in the step of providing a frame unit, only one independent frame unit may be provided.

[0122] In this embodiment, the frame unit 360 is a frame structure without a base, thereby providing more space for the setting of non-functional pins 301 and facilitating the setting of non-functional pins 301 at different positions on the bottom surface of the plastic package body, thereby ensuring that the non-functional pins 301 can play an electromagnetic shielding role.

[0123] In this embodiment, the non-functional pin 301 extends to the perimeter 360C of the frame unit 360, so that the shielding layer can be connected to the non-functional pin 301 through the exposed side thereof. Therefore, the non-functional pin 301 and the shielding layer jointly play the role of electromagnetic shielding, and realize electromagnetic shielding on each side of the chip 310 (for example, taking the packaging structure as a square as an example, the shielding layer can realize electromagnetic shielding on the six sides of the plastic package body), thereby improving the shielding effect and enhancing the performance of the packaging structure.

[0124] Figure 7 As shown, in this embodiment, the non-functional pins 301 are arranged vertically and horizontally in the frame unit 360, that is, the non-functional pins 301 include horizontal (such as Figure 7 The non-functional pin 301 extending in the longitudinal direction (as shown in the X direction) is connected to the Figure 7 The non-functional pin 301 extends in the Y direction (as shown in the figure), thereby performing electromagnetic shielding in the horizontal and vertical directions, so that the electromagnetic shielding structure composed of the shielding layer and the non-functional pin 301 is more like a Faraday cage, thereby improving the shielding effect.

[0125] In this embodiment, there is a gap between the non-functional pins 301 extending laterally and the non-functional pins 301 extending longitudinally, thereby reducing the complexity of preparing the frame unit 360. In other embodiments, the non-functional pins extending laterally and the non-functional pins extending longitudinally are crisscrossed to form a grid, thereby further improving the shielding effect.

[0126] In this embodiment, the bottom surfaces of the functional pins 300 and the non-functional pins 301 are flush, so that the plastic encapsulation layer can expose the bottom surface of the non-functional pins 301. In other embodiments, the bottom surface of the non-functional pins is higher than the bottom surface of the functional pins, so that the plastic encapsulation layer covers the bottom surface of the non-functional pins.

[0127] It should be noted that the bottom surface of the pin 350 is the pin surface on the second surface 360B side of the frame unit 360 , and the top surface of the pin 350 is the pin surface on the first surface 360A side of the frame unit 360 .

[0128] In this embodiment, the pins 350 include chip pins (not shown), which are pins used to connect to the chip 310, and the chip pins include function pins 300. It should be noted that the function pins 300 refer to the pins of the chip except the ground pins.

[0129] In this embodiment, the functional pins 300 are located inside the perimeter 360C of the frame unit 360 , so that the sides of the functional pins 300 are covered by the plastic packaging layer, thereby reducing the probability of short circuit between the functional pins 300 caused by the connection between the shielding layer and the functional pins 300 .

[0130] In this embodiment, the top surface of the functional pin 300 is higher than the top surface of the non-functional pin 301 .

[0131] like Figure 8 As shown, in this embodiment, along the thickness direction of the frame unit 360, the functional pin 300 includes a top functional pin 300t located on one side of the first surface 360A of the frame unit 360, and a bottom functional pin 300b located at the bottom of the top functional pin 300t, and the line width of the top functional pin 300t is greater than the line width of the bottom functional pin 300b.

[0132] In this embodiment, the longitudinal section of the functional pin 300 is T-shaped. In other embodiments, the longitudinal section of the functional pin may also be L-shaped.

[0133] In this embodiment, the pins 350 further include a ground pin 302 , and the ground pin 302 is used for grounding. Specifically, the chip pins include a functional pin 300 and a ground pin 302 . In other words, the ground pin 302 is used for connecting to the chip 310 .

[0134] The ground pin 302 is used to connect the ground signal, so that the ground pin 302 is connected to the shielding layer, so that the shielding layer can be connected to the ground signal through the ground pin 302. For example, the ground pin 302 is usually used to be soldered to a substrate (e.g., a PCB board or a packaging substrate, etc.) and connected to the ground signal through the substrate.

[0135] The ground pin 302 is flush with the top surface of the functional pin 300 , thereby providing a flat surface for the chip 310 to be disposed, thereby improving the reliability of the combination of the chip 310 and the frame unit 360 .

[0136] In this embodiment, the ground pin 302 extends to the perimeter 360C of the frame unit 360. Accordingly, the subsequently formed plastic encapsulation layer exposes the side of the ground pin 302 located at the perimeter 360C of the frame unit 360, and the shielding layer is connected to the side of the ground pin 302 exposed to the plastic encapsulation layer.

[0137] It should be noted that in other embodiments, the ground pin may also be located within the perimeter of the frame unit, so as to be electrically connected to the shielding layer through other conductive components. For example, the ground pin may be electrically connected to the shielding layer located on the top surface of the plastic packaging layer through a conductive column disposed in the plastic packaging layer.

[0138] It should also be noted that, in other embodiments, in the step of providing the frame unit, the ground pin may also be connected to any non-functional pin.

[0139] In this embodiment, along the thickness direction of the frame unit 360, the grounding pin 302 includes a top grounding pin 302t located on one side of the first surface 360A of the frame unit 360, and a bottom grounding pin 302b located at the bottom of the top grounding pin 302t, the top grounding pin 302t and the top functional pin 300t are located at the same height position, and the bottom grounding pin 302b and the bottom functional pin 300b are located at the same height position.

[0140] In this embodiment, the top ground pin 302 t and the bottom ground pin 302 b partially overlap, thereby providing more space for the arrangement of the non-functional pin 301 .

[0141] In the frame unit 360, the spacing between adjacent pins 350 should not be too small, otherwise it is easy to increase the risk of short circuit between adjacent pins 350. For example, when the bottom surface of the pin 350 exposed to the plastic layer has a solder wetting layer, it is easy to cause the solder wetting layers on adjacent pins 350 to contact each other, for example, it is easy to cause a tinning problem. In this embodiment, the spacing between adjacent pins 350 is greater than one times the width of the pin 350.

[0142] It should be noted that for a detailed description of the frame unit 360 , reference may be made to the relevant content in any of the aforementioned embodiments, which will not be repeated here.

[0143] like Figure 8 As shown, in this embodiment, the step of providing the frame unit 360 includes: providing a first frame unit, the first frame unit having a non-functional pin 301; providing a second frame unit, the second frame unit having a functional pin 300; combining the first frame unit and the second frame unit to obtain a frame unit 360 including the non-functional pin and the functional pin.

[0144] The non-functional pins 301 are arranged on a separate frame, and the functional pins 300 are arranged on another separate frame, so as to facilitate the separate preparation of the non-functional pins 301 and the functional pins 300 . For example, it is easy to make the laterally extending non-functional pins 301 and the longitudinally extending non-functional pins 301 criss-cross to form a grid.

[0145] Moreover, the non-functional pins 301 and the functional pins 300 are obtained respectively through different frames, and it is also easy to adjust the height positions of the non-functional pins 301 and the functional pins 300 in the frame unit 360 according to actual needs.

[0146] It should be noted that in the step of combining the first frame unit and the second frame unit, the functional pins 300 are arranged at the gaps between the non-functional pins 301 , so that the non-functional pins 301 and the functional pins 300 are spaced apart, reducing the probability of a short circuit between the two.

[0147] In this embodiment, after the first frame unit and the second frame unit are combined, the ground pin 302 extends to the perimeter 360C of the frame unit 360 .

[0148] In other embodiments, on a projection plane parallel to the surface of the first frame unit, the projection of the second frame unit is located inside the projection of the first frame unit, that is, the ground pin may also be located inside the perimeter of the frame unit. In this case, in the step of combining the first frame unit with the second frame unit, the ground pin may also be welded to any non-functional pin; for example, the ground pin may be welded to any non-functional pin through a solder layer.

[0149] As an example, the method of combining the first frame unit and the second frame unit includes: arranging the first frame unit and the second frame unit on the same tape 380 .

[0150] The adhesive film 380 can fix the first frame unit and the second frame unit, and can be easily separated from the frame unit 360 after the first frame unit and the second frame unit are subsequently plastic-sealed.

[0151] It should be noted that, in order to improve the stability of subsequent processes, a carrier plate may be disposed at the bottom of the adhesive film 380 .

[0152] In other embodiments, the first frame unit and the second frame unit may be combined by pre-sealing the first frame unit and the second frame unit. The pre-sealing is performed so that the gap between the first frame unit and the second frame unit is filled with a second plastic sealing layer, thereby combining the two through the second plastic sealing layer.

[0153] refer to Fig. 9 , Fig. 9 is based on Figure 7 In the cross-sectional view, a chip 310 is arranged on the functional pin 300, and the chip 310 is electrically connected to the functional pin 300.

[0154] Specifically, the chip 310 is disposed on one side of the first surface 360A of the frame unit 360. The chip 310 is electrically connected to the function pins 300 so as to achieve electrical connection with an external circuit through the function pins 300.

[0155] In this embodiment, a flip-chip process is used to arrange the chip 310 on the functional pin 300. Specifically, a conductive bump 330 is arranged on the chip 310, so the chip 310 is soldered to the functional pin 300 through the conductive bump 330.

[0156] The chip 310 is arranged on the functional pin 300 by using a flip-chip process, so that the base can be omitted.

[0157] In this embodiment, after the first frame unit and the second frame unit are combined, a chip 310 is disposed on the functional pin 300 of the second frame unit.

[0158] In other embodiments, according to actual needs, a chip may be provided on the functional pin of the second frame unit before the first frame unit and the second frame unit are combined.

[0159] It can be seen that obtaining the non-functional pins 301 and the functional pins 300 respectively through different frames is also beneficial to improving the flexibility of the packaging process.

[0160] In this embodiment, multiple (for example, 2) conductive bumps 330 are located on the same functional pin 300. Conductive bumps 330 connected to the same electrical signal are connected to the same functional pin 300, which reduces the number of functional pins 300 and provides more space for the non-functional pins 301.

[0161] In this embodiment, the longitudinal section of the functional pin 300 is T-shaped so that a plurality of conductive bumps 330 are disposed on the top functional pin 300 t.

[0162] In other embodiments, only one conductive bump may be disposed on one functional pin, for example, the conductive bumps correspond to the functional pins one by one.

[0163] In this embodiment, in the step of disposing the chip 310 on the functional pin 300 , the chip 310 is also disposed on the ground pin 302 and electrically connected to the ground pin 302 .

[0164] Since the ground pin 302 is a chip pin, the chip 310 is also disposed on the ground pin 302 and electrically connected to the ground pin 302 , thereby meeting the grounding requirement of a specific connection terminal of the chip 310 .

[0165] Combined with reference Figures 10 to 12 , Fig.10 is based on Fig. 9 A cross-sectional view of Fig.11 is based on Fig.10 Sectional view, Fig.12 is based on Fig.11 A cross-sectional view is formed to form a first plastic encapsulation layer 303 covering the chip 310 and the frame unit 360, and a plastic encapsulation body 370 (such as Fig.12 As shown), and in the plastic package body 370, the first plastic package layer 303 exposes the side surface of the non-functional pin 301 located at the perimeter 360C of the frame unit 360 and the bottom surface of the functional pin 300.

[0166] The first plastic packaging layer 303 is used to protect the components covered by it and to plastic-package the chip 310 and the frame unit 360 into a whole to obtain a plastic packaging body.

[0167] In this embodiment, the material of the first plastic layer 303 is a molding material, such as epoxy resin.

[0168] In this embodiment, in the plastic package body 370 , the first plastic package layer 303 exposes the side surface of the non-functional pin 301 located at the perimeter 360C of the frame unit 360 , so that the non-functional pin 301 is connected to the shielding layer.

[0169] In this embodiment, the first plastic packaging layer 303 also exposes the bottom surface of the functional pin 300 so as to subsequently weld the exposed pin 350 to the substrate, and it is also beneficial to improve the heat conduction effect of the frame unit 360 to the outside.

[0170] In this embodiment, the first plastic encapsulation layer 303 exposes the back side of the chip 310, thereby reducing the thickness of the plastic encapsulation body 370 and improving the heat dissipation effect of the chip 310 during operation. In other embodiments, the plastic encapsulation layer may also cover the back side of the chip.

[0171] In this embodiment, the first plastic packaging layer 303 also exposes the bottom surface of the ground pin 302 so that the exposed ground pin 302 can be subsequently soldered to the substrate.

[0172] As an example, in the plastic package body 370 , the first plastic package layer 303 further exposes the side surface of the non-functional pin 302 located at the perimeter 360C of the frame unit 360 , so that the shielding layer is connected to the ground pin 302 .

[0173] In some other embodiments, the grounding pin may also be located inside the perimeter of the frame unit, and the first plastic packaging layer correspondingly covers the side wall of the grounding pin.

[0174] In other embodiments, in the step of providing a frame unit, the bottom surface of the non-functional pin is higher than the bottom surface of the functional pin; correspondingly, in the step of forming a first plastic encapsulation layer covering the chip and the frame unit, the first plastic encapsulation layer covers the bottom surface of the non-functional pin.

[0175] In this embodiment, after forming the first plastic packaging layer 303 covering the chip 310 and the frame unit 360 , the packaging method further includes: removing the adhesive film 380 to expose the bottom surface of the pin 350 , thereby preparing for subsequent processes.

[0176] refer to Fig.11After forming the first plastic packaging layer 303 covering the chip 310 and the frame unit 360, and before forming the shielding layer covering the top and side surfaces of the plastic packaging body 370, the packaging method further includes: forming a solder wetting layer 320 on the bottom surface of the pin 350 exposed to the first plastic packaging layer 303 through an electroplating process.

[0177] The solder wetting layer 320 is used as a protective plating layer to protect the pins 350 exposed to the plastic layer 303, reduce the exposed area of ​​the pins 350 (ie, the copper-clad area), and reduce the probability of oxidation or corrosion of the pins 350, which is beneficial to improving the performance of the packaging structure.

[0178] Moreover, when the pin 350 is subsequently soldered to the substrate by solder, the solder wetting layer 320 has good solder wettability and can guide the flow of the solder, thereby facilitating enhancing the soldering strength between the pin 350 and the substrate.

[0179] In this embodiment, the material of the solder wetting layer 320 may include one or more alloys of tin, nickel, palladium and silver. As an example, the material of the solder wetting layer 320 is tin.

[0180] In this embodiment, in the step of providing a frame unit 360, a plurality of connected frame units 360 constitute a frame structure. Therefore, before separating each frame unit 360 to obtain an independent plastic package body 370, a solder wetting layer 320 is formed on the bottom surface of the pin 350 exposed to the first plastic package layer 303.

[0181] Before cutting to form each independent plastic package body, the side of the non-functional pin 301 is covered by the first plastic package layer 303, so as to avoid the formation of a solder wetting layer 320 on the side of the non-functional pin 301. After subsequent cutting, the side of the non-functional pin 301 can be exposed by the first plastic package layer 303 corresponding to the plastic package body 370, so that the non-functional pin 301 is in direct contact with the shielding layer.

[0182] In other embodiments, after the frame units 360 are separated to obtain independent plastic packaging bodies, a solder wetting layer may be formed on the bottom surfaces of the pins exposed to the first plastic packaging layer.

[0183] refer to Fig.12 After forming the first plastic encapsulation layer 303 covering the chip 310 and the frame unit, the first plastic encapsulation layer 303 and the frame structure (not shown) are cut at the junction of the frame unit 360 (eg, Fig.12 The frame units 360 are separated to obtain independent plastic packaging bodies 370 .

[0184] An independent plastic package body 370 is obtained, providing a process basis for the subsequent formation of a shielding layer.

[0185] In other embodiments, the side of the plastic package body 370 where the pins 350 are exposed is first attached to the carrier board by means of an adhesive film, and then the first plastic package layer 303 and the frame structure are cut at the junction of the frame unit 360 to expose the side of the plastic package body 370 and the side of the non-functional pin 301, so as to carry out subsequent processes of the entire plastic package body 370.

[0186] Combined with reference Fig.13 and Fig.14 , Fig.13 is based on Fig.12 A cross-sectional view of Fig.14 It is a top view of the top surface of the plastic package 370. After obtaining the plastic package 370 composed of the first plastic package layer 303, the chip 310 and the frame unit 360, and before forming a shielding layer covering the top surface and side surfaces of the plastic package 370, it also includes: roughening the top surface of the plastic package 370.

[0187] The top surface of the plastic package body 370 is roughened to form a roughened surface, which is beneficial to increase the bonding force between the shielding layer and the top surface of the plastic package body 370 .

[0188] The roughened surface includes crisscross grooves 390 to form a grid structure, thereby improving the bonding force between the shielding layer and the top surface of the plastic package body 370 in all directions.

[0189] It should be noted that, compared with the chip 310 , the shielding layer is easier to combine with the first plastic layer 303 . Therefore, in this embodiment, the first plastic layer 303 exposes the back side of the chip 310 , so at least the back side of the chip 310 is roughened.

[0190] As an example, in order to improve the bonding force between the shielding layer and the top surface of the plastic package body 370 , the top surface of the first plastic package layer 303 and the back surface of the chip 310 are roughened.

[0191] In this embodiment, the step of roughening the top surface of the plastic packaging body 370 includes: performing a first laser treatment on the back side of the chip 310 through a laser process, and performing a second laser treatment on the top surface of the first plastic packaging layer 303, wherein the power of the first laser treatment is greater than the power of the second laser treatment.

[0192] A groove 390 of a certain depth can be laser-printed on the top surface of the plastic package 370 by laser processing.

[0193] The chip 310 is made of a material with greater hardness, so the power of the first laser processing is greater than the power of the second laser processing, which makes it easier to improve the depth uniformity of the grooves formed in the chip 310 and the first plastic packaging layer 303 .

[0194] It should be noted that the first plastic packaging layer 303 covers a portion of the top surface of the pin 350 , and therefore, the power of the second laser processing needs to be controlled within a reasonable range.

[0195] It should also be noted that if the ratio of the power of the first laser process to the power of the second laser process is too small, it is easy to cause poor roughening effect on the chip 310; if the ratio of the power of the first laser process to the power of the second laser process is too large, it is easy to damage the chip 310. Therefore, in this embodiment, the power of the first laser process is 2 to 5 times the power of the second laser process.

[0196] In order to improve the roughening effect, in this embodiment, the depth of the grooves 390 of the roughened surface is greater than or equal to 8 micrometers.

[0197] In other embodiments, the roughening process may also be performed by chemical etching.

[0198] The depth of the groove 390 of the roughened surface should not be too large, otherwise it is easy to damage the chip 210. Therefore, in this embodiment, the depth of the groove 390 of the roughened surface is 8 micrometers to 15 micrometers.

[0199] In another embodiment, only the back side of the chip may be roughened. In some other embodiments, when the back side of the chip is covered by a plastic layer, only the top side of the plastic layer may be roughened. In other embodiments, the roughening may not be performed.

[0200] refer to Fig.15 , forming a shielding layer 304 covering the top surface and side surfaces of the plastic package body 370 , wherein the shielding layer 304 is connected to the side surfaces of the non-functional pins 301 exposed to the first plastic package layer 303 .

[0201] The shielding layer 304 is electrically connected to the non-functional pin 201 , thereby forming an electromagnetic shielding structure.

[0202] Among them, the bottom of the plastic package body 370 has a non-functional pin 301, and the non-functional pin 301 and the shielding layer 304 jointly play the role of electromagnetic shielding, realizing electromagnetic shielding on each surface of the chip 310, and improving the shielding effect; moreover, the functional pin 300 is located inside the perimeter 360C of the frame unit 360, so that the side of the functional pin 300 is covered by the first plastic package layer 303, and the first plastic package layer 303 can isolate the shielding layer 304 from the functional pin 300, thereby reducing the probability of short circuit between the functional pins 300 caused by the connection between the shielding layer 304 and the functional pin 300; in summary, the packaging method can improve the performance of the packaging structure.

[0203] It should be noted that by arranging the functional pins 300 below the chip 310 and placing the non-functional pins 301 on the side, the complexity of the process for forming the shielding layer 304 is reduced.

[0204] In this embodiment, the shielding layer 304 is also connected to the grounding pin 302 , so that the shielding layer 304 is grounded through the grounding pin 302 .

[0205] Specifically, the shielding layer 304 is connected to the side surface of the grounding pin 302 exposed to the first plastic packaging layer 303 , thereby directly contacting the grounding pin 302 .

[0206] In other embodiments, the ground pin is connected to any non-functional pin; correspondingly, the shielding layer is connected to the ground pin through the non-functional pin to achieve electrical connection between the two.

[0207] In this embodiment, the shielding layer 304 is formed by a sputtering process.

[0208] In this embodiment, in order to achieve a shielding effect, the material of the shielding layer 304 may be metal, for example, the material of the shielding layer 304 includes one or more metals such as copper, tin, aluminum, zinc, tungsten, etc. In other embodiments, the material of the shielding layer 304 may also be an alloy, for example, an alloy of stainless steel, etc.

[0209] Figures 16 to 20 It is a schematic diagram corresponding to each step in another embodiment of the packaging method of the present invention.

[0210] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that each pin in the frame unit is obtained through an integrated original frame.

[0211] refer to Fig.16 , providing an original frame 500, including a frame unit area (not shown).

[0212] The original frame 500 is a raw material frame, and the original frame 500 in the frame unit area is used to prepare the frame unit.

[0213] For example, Fig.16 As shown, the original frame 500 is a frame panel having a certain thickness.

[0214] It should be noted that this is only a diagram. Fig.16 A framework unit area is schematically shown in FIG.

[0215] In this embodiment, the original frame 500 may include a plurality of frame unit regions, thereby preparing a plurality of frame units.

[0216] In this embodiment, the original frame 500 includes a first surface 460A and a second surface 460B that are oppositely disposed.

[0217] After the frame unit is subsequently obtained, the first surface 460A of the frame unit is used to mount the chip.

[0218] refer to Fig.17 In the frame unit region (not shown), a first groove 510 is formed on the second surface 460B of the original frame 500 to obtain a bottom functional pin 400 b and an initial non-functional pin 401 ′ separated by the first groove 510 .

[0219] Initial non-functional pins 401 ′ are first formed on one side of the second surface 460B. At this time, the first surface 460A of the original frame 500 has not been patterned. Subsequently, second grooves are formed on the first surface 460A to separate the final non-functional pins.

[0220] By forming the first groove 501 , the functional pins with a partial thickness are separated from the initial non-functional pins 401 ′, and subsequently, the functional pins and the non-functional pins can be completely separated by forming a second groove on the first surface 460A.

[0221] In this embodiment, in the first groove 510 formed on the second surface 460B of the original frame 500 , a bottom ground pin 402 b spaced apart from the initial non-functional pin 401 ′ by the first groove 510 is also obtained.

[0222] As an embodiment, a first cutting tool may be used to perform cutting to form the first groove 510 .

[0223] In other embodiments, the first groove may also be formed by etching.

[0224] refer to Fig.18 After forming the first groove 510 , a second plastic encapsulation layer 520 is filled in the first groove 510 .

[0225] By forming the second plastic encapsulation layer 520, pre-molding is achieved, so that the sidewalls of the bottom functional pins 400b are covered by the second plastic encapsulation layer 520. Moreover, after the second grooves are subsequently formed on the first surface 460A, the pins are separated from each other and will not fall off.

[0226] In this embodiment, the material of the second plastic packaging layer 520 is a plastic packaging material, such as epoxy resin.

[0227] refer to Fig.19 After the second plastic encapsulation layer 520 is filled in the first groove 510, the original frame 500 (such as Fig.18 On one side of the first surface 460A of the substrate, a second groove 530 is formed at the position of the initial non-functional pin 401' to obtain a top functional pin 400a connected to the bottom functional pin 400b, and the initial non-functional pin 401' and the top functional pin 400a of the remaining thickness at the bottom of the second groove 530 are separated, and the initial non-functional pin 401' of the remaining thickness at the bottom of the second groove 530 serves as the non-functional pin 401, and the top functional pin 400a and the bottom functional pin 400b constitute the functional pin 400.

[0228] In this embodiment, in the step of forming the second groove 530 on the first surface 460A of the initial original frame 500, a top grounding pin 402t separated from the top functional pin 400t and connected to the bottom grounding pin 402b is also obtained, and the top grounding pin 402t and the bottom grounding pin 402b constitute a grounding pin 402.

[0229] Therefore, the non-functional pin 401 , the functional pin 400 , and the ground pin 400 serve as respective pins 450 of the frame unit.

[0230] In this embodiment, the line width of the top functional pin 400t is greater than the line width of the bottom functional pin 400b.

[0231] As an embodiment, a second cutting tool may be used to perform cutting to form the second groove 530 .

[0232] In other embodiments, the second groove may also be formed by etching.

[0233] refer to Fig. 20 , Fig. 20 It is a bottom view on one side of the second surface of the frame unit, and a portion of the length of the end position of the top functional pin 400t is removed along the perimeter 460C of the frame unit (not marked) so that the top functional pin 400t is located inside the perimeter 460C of the frame unit.

[0234] It should be noted that, since the initial non-functional pin 401' of the remaining thickness at the bottom of the second groove 530 serves as the non-functional pin 401, the top surface of the non-functional pin 401 is lower than the top surface of the functional pin 400. Therefore, the top surface of the non-functional pin 401 can be used as the stopping surface of the operation process to remove a portion of the length at the end position of the top functional pin 400t, and the process of removing a portion of the length at the end position of the top functional pin 400t causes less damage to the non-functional pin 401.

[0235] As an embodiment, a third cutter may be used to perform cutting to remove a portion of the length of the end portion of the top functional pin 400t.

[0236] It should be noted that the subsequent steps are the same as those in the aforementioned embodiment. For the specific description of the packaging method described in this embodiment, reference can be made to the relevant contents in the aforementioned embodiment, which will not be repeated here.

[0237] It should be noted that the packaging structure of the aforementioned embodiment can be obtained by adopting the packaging method of the aforementioned embodiment, and can also be obtained by adopting other packaging methods. For the specific description of the packaging method of the aforementioned embodiment, please refer to the relevant description of the packaging structure part.

[0238] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: A frame unit, comprising a plurality of pins, wherein the pins include spaced functional pins and non-functional pins, wherein the functional pins are located inside the perimeter of the frame unit, and the non-functional pins extend to the perimeter of the frame unit; A chip, located on the functional pin of the frame unit and electrically connected to the functional pin; A plastic encapsulation layer, covering the chip and the frame unit, and exposing the side surfaces of the non-functional pins located at the periphery of the frame unit and the bottom surfaces of the functional pins, wherein the plastic encapsulation layer, the chip and the frame unit constitute a plastic encapsulation body; The shielding layer is located on the top surface and the side surface of the plastic package body, and the shielding layer is connected to the side surface of the non-functional pins exposed to the plastic package layer.

2. The packaging structure according to claim 1, characterized in that: The pins further include a ground pin, and the ground pin is flush with the top surface of the functional pin; the chip is also arranged on the ground pin and electrically connected to the ground pin; The shielding layer is also connected to the grounding pin.

3. The packaging structure according to claim 2, characterized in that: The ground pin extends to the perimeter of the frame unit; the plastic encapsulation layer further exposes the side of the ground pin located at the perimeter of the frame unit; the shielding layer is connected to the side of the ground pin exposed to the plastic encapsulation layer; Alternatively, the ground pin is connected to any of the non-functional pins; and the shielding layer is connected to the ground pin through the non-functional pin.

4. The packaging structure according to claim 1, characterized in that: The chip is flipped onto the functional pin; The plastic encapsulation layer exposes the back side of the chip, or the plastic encapsulation layer covers the back side of the chip.

5. The packaging structure according to any one of claims 1 to 4, characterized in that: The top surface of the functional pin is higher than the top surface of the non-functional pin.

6. The packaging structure according to claim 5, characterized in that: The frame unit includes a chip mounting surface for mounting a chip. Along the thickness direction of the frame unit, the functional pins include a top functional pin located on one side of the chip mounting surface of the frame unit, and a bottom functional pin located at the bottom of the top functional pin. The line width of the top functional pin is greater than the line width of the bottom functional pin.

7. The packaging structure according to claim 6, characterized in that: The non-functional pin is located at the bottom of the top functional pin.

8. The packaging structure according to any one of claims 1 to 4, characterized in that: The non-functional pins are arranged vertically and horizontally in the frame unit; There is a gap between the non-functional pins extending transversely and the non-functional pins extending longitudinally, or the non-functional pins extending transversely and the non-functional pins extending longitudinally are crisscrossed to form a grid.

9. The packaging structure according to any one of claims 1 to 4, characterized in that: The bottom surfaces of the functional pins and the non-functional pins are flush with each other; Alternatively, the bottom surface of the non-functional pin is higher than the bottom surface of the functional pin; and the plastic packaging layer covers the bottom surface of the non-functional pin.

10. The packaging structure according to any one of claims 1 to 4, characterized in that: The top surface of the plastic package body has a roughened surface.

11. The packaging structure according to claim 10, characterized in that: The groove depth of the roughened surface is 8 micrometers to 15 micrometers.

12. The packaging structure according to any one of claims 1 to 4, characterized in that: The packaging structure further includes: a solder wetting layer located on the bottom surface of the pins exposed to the plastic packaging layer.

13. A packaging method, characterized in that: include: Providing a frame unit, comprising a plurality of pins, wherein the pins include spaced functional pins and non-functional pins, wherein the functional pins are located inside the perimeter of the frame unit, and the non-functional pins extend to the perimeter of the frame unit; A chip is arranged on the functional pin, wherein the chip is electrically connected to the functional pin; Forming a first plastic encapsulation layer covering the chip and the frame unit, and obtaining a plastic encapsulation body consisting of the first plastic encapsulation layer, the chip and the frame unit, wherein the first plastic encapsulation layer exposes the side surface of the non-functional pin located at the periphery of the frame unit and the bottom surface of the functional pin in the plastic encapsulation body; A shielding layer is formed to cover the top surface and side surfaces of the plastic package body, and the shielding layer is connected to the side surfaces of the non-functional pins exposed to the first plastic package layer.

14. The packaging method according to claim 13, characterized in that: In the step of providing the frame unit, the pins further include a ground pin, and the ground pin is flush with the top surface of the functional pin; In the step of arranging a chip on the functional pin, the chip is also arranged on the ground pin and electrically connected to the ground pin; In the step of forming a shielding layer covering the top surface and side surfaces of the plastic package body, the shielding layer is also connected to the grounding pin.

15. The packaging method according to claim 14, characterized in that: In the step of providing the frame unit, the ground pin extends to a perimeter position of the frame unit; In the plastic package body, the first plastic package layer further exposes the side surface of the non-functional pin located at the periphery of the frame unit; In the step of forming a shielding layer covering the top surface and side surfaces of the plastic package body, the shielding layer is connected to the side surfaces of the grounding pins exposed to the first plastic package layer; or, In the step of providing the frame unit, the ground pin is connected to any of the non-functional pins; In the step of forming a shielding layer covering the top surface and the side surfaces of the plastic package body, the shielding layer is connected to the grounding pin through the non-functional pin.

16. The packaging method according to claim 13, characterized in that: Using a flip-chip process to place a chip on the functional pin; In the step of forming a first plastic encapsulation layer covering the chip and the frame unit, the first plastic encapsulation layer exposes the back side of the chip, or the first plastic encapsulation layer covers the back side of the chip.

17. The packaging method according to claim 13, characterized in that: In the step of providing the frame unit, the bottom surfaces of the functional pins and the non-functional pins are flush with each other; or, In the step of providing the frame unit, the bottom surface of the non-functional pin is higher than the bottom surface of the functional pin; in the step of forming a first plastic encapsulation layer covering the chip and the frame unit, the first plastic encapsulation layer covers the bottom surface of the non-functional pin.

18. The packaging method according to claim 13, characterized in that: In the step of providing the frame unit, the non-functional pins are arranged vertically and horizontally in the frame unit; There is a gap between the non-functional pins extending transversely and the non-functional pins extending longitudinally, or the non-functional pins extending transversely and the non-functional pins extending longitudinally are crisscrossed to form a grid.

19. The packaging method according to claim 13, characterized in that: After forming a first plastic packaging layer covering the chip and the frame unit, and before forming a shielding layer covering the top and side surfaces of the plastic packaging body, the packaging method further comprises: forming a solder wetting layer on the bottom surface of the pins exposed to the first plastic packaging layer through an electroplating process.

20. The packaging method according to claim 13, characterized in that: The step of providing the frame unit includes: providing a frame structure, the frame structure including a plurality of frame units; After forming the first plastic packaging layer covering the chip and the frame unit, the first plastic packaging layer and the frame structure are cut at the junction of the frame units to separate the frame units to obtain independent plastic packaging bodies.

21. The packaging method according to claim 20, characterized in that: After obtaining the plastic package body composed of the first plastic package layer, the chip and the frame unit, and before forming the shielding layer covering the top surface and the side surfaces of the plastic package body, the method further includes: roughening the top surface of the plastic package body.

22. The packaging method according to claim 21, characterized in that: A chip is arranged on the functional pin by using a flip-chip process, and the first plastic packaging layer exposes the back side of the chip; The step of roughening the top surface of the plastic package body includes: performing a first laser treatment on the back of the chip and a second laser treatment on the top surface of the first plastic package layer through a laser process, wherein the power of the first laser treatment is greater than the power of the second laser treatment.

23. The packaging method according to claim 22, characterized in that: The power of the first laser treatment is 2 to 5 times the power of the second laser treatment.

24. The packaging method according to any one of claims 13 to 23, characterized in that: The step of providing the frame unit includes: providing a first frame unit, wherein the first frame unit has non-functional pins; providing a second frame unit, the second frame unit having a functional pin; The first frame unit and the second frame unit are combined to obtain a frame unit including the non-functional pins and functional pins.

25. The packaging method according to claim 24, characterized in that: The method of combining the first frame unit and the second frame unit includes: pre-sealing the first frame unit and the second frame unit; Alternatively, the first frame unit and the second frame unit are arranged on the same adhesive film; after forming a first plastic packaging layer covering the chip and the frame unit, the packaging method further comprises: removing the adhesive film.

26. The packaging method according to claim 24, characterized in that: In the step of providing the second frame unit, the second frame unit further comprises a ground pin; In the step of combining the first frame unit and the second frame unit, the ground pin is welded to any non-functional pin.

27. The packaging method according to claim 24, characterized in that: Before combining the first frame unit with the second frame unit, a chip is arranged on the functional pin of the second frame unit; or after combining the first frame unit with the second frame unit, a chip is arranged on the functional pin of the second frame unit.

28. The packaging method according to any one of claims 13 to 23, characterized in that: The step of providing the frame unit includes: providing an original frame, including a frame unit area, the original frame including a first surface for mounting a chip and a second surface opposite to the first surface; In the frame unit area, a first groove is formed on the second surface of the original frame to obtain a bottom functional pin and an initial non-functional pin separated by the first groove; After forming the first groove, filling the first groove with a second plastic encapsulation layer; After the second plastic encapsulation layer is filled in the first groove, a second groove is formed at the position of the initial non-functional pin on one side of the first surface of the original frame to obtain a top functional pin connected to the bottom functional pin, and the initial non-functional pin of the remaining thickness at the bottom of the second groove is separated from the top functional pin, the initial non-functional pin of the remaining thickness at the bottom of the second groove is used as a non-functional pin, and the top functional pin and the bottom functional pin constitute a functional pin; A portion of the length of the top functional pin at the end position is removed along the perimeter of the frame unit so that the top functional pin is located inside the perimeter of the frame unit.

29. The packaging method according to claim 28, characterized in that: In the step of forming a first groove on the second surface of the original frame, a bottom ground pin separated from the initial non-functional pin by the first groove is also obtained; In the step of forming the second groove on the first surface of the original frame, a top grounding pin separated from the top functional pin and connected to the bottom grounding pin is also obtained, and the top grounding pin and the bottom grounding pin constitute a grounding pin.

30. The packaging method according to claim 20, characterized in that: Before the step of cutting the first plastic packaging layer and the frame structure, the method further includes: attaching the side of the plastic packaging body, where the pins are exposed, to a carrier board through an adhesive film.

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