GaN semiconductor device

Abstract

The invention discloses a GaN semiconductor device. The GaN semiconductor device comprises a substrate; the GaN channel layer is arranged on the substrate; the AlGaN layer is arranged on the GaN channel layer; the p-GaN grid electrode layer is arranged on the AlGaN layer; the nitrogen-rich TiN hard mask layer is arranged on the p-GaN gate layer, and the nitrogen-titanium ratio (N / Ti) of the nitrogen-rich TiN hard mask layer is larger than 1.0; and the gate electrode layer is arranged on the nitrogen-rich TiN hard mask layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an improved gallium nitride (GaN) high-electron mobility transistor (HEMT) and a manufacturing method thereof. Background Art

[0002] Gallium nitride (GaN) high electron mobility transistors (HEMTs) are suitable devices for high power and high frequency applications due to the high carrier density and high electron mobility of the two-dimensional electron gas (2DEG). The presence of 2DEG at the AlGaN / GaN heterostructure interface makes the HEMT essentially a normally-on device. However, for power electronics applications, normally-off operation is required for safety reasons and to simplify the driver circuit.

[0003] GaN HEMTs with p-GaN gates have been applied for normally off operation. However, injected electrons may be captured by traps in the depleted p-GaN gate layer, thus potentially affecting the reliability of the HEMT device. Depending on the applied gate bias, the electron capture process plays a key role in the reliability of p-GaN HEMTs. Summary of the invention

[0004] The main purpose of the present invention is to provide an improved GaN high electron mobility transistor and a method for manufacturing the same, so as to solve the deficiencies or shortcomings of the prior art.

[0005] On one hand, the present invention provides a GaN semiconductor device, comprising: a substrate; a GaN channel layer, arranged on the substrate; an AlGaN layer, arranged on the GaN channel layer; a p-GaN gate layer, arranged on the AlGaN layer; a nitrogen-rich TiN hard mask layer, arranged on the p-GaN gate layer, wherein the nitrogen-to-titanium ratio (N / Ti) of the nitrogen-rich TiN hard mask layer is greater than 1.0; and a gate electrode layer, arranged on the nitrogen-rich TiN hard mask layer.

[0006] According to an embodiment of the present invention, the GaN semiconductor device further includes: a buffer layer located on the substrate, wherein the buffer layer is disposed between the substrate and the GaN channel layer.

[0007] According to an embodiment of the present invention, the buffer layer includes AlN or GaN, and the thickness of the buffer layer is 4 μm.

[0008] According to an embodiment of the present invention, the thickness of the GaN channel layer is 200-400 nm.

[0009] According to an embodiment of the present invention, the thickness of the AlGaN layer is 10-14 nm.

[0010] According to an embodiment of the present invention, the thickness of the p-GaN gate layer is 60-100 nm.

[0011] According to an embodiment of the present invention, the gate electrode layer includes a TiN bottom layer, an AlCu middle layer and a TiN top layer, and the TiN bottom layer is in direct contact with the nitrogen-rich TiN hard mask layer.

[0012] According to an embodiment of the present invention, the N / Ti ratio of the nitrogen-rich TiN hard mask layer is equal to or greater than 1.04.

[0013] According to an embodiment of the present invention, the GaN semiconductor device further includes: Al 2 O 3 A passivation layer covers the sidewalls of the p-GaN gate layer, the sidewalls of the nitrogen-rich TiN hard mask layer, and the top surface of the AlGaN layer.

[0014] According to an embodiment of the present invention, the GaN semiconductor device further includes: an insulating layer disposed on the Al 2 O 3 on the passivation layer.

[0015] On the other hand, the present invention provides a method for manufacturing a GaN semiconductor device, comprising: providing a substrate; forming a GaN channel layer on the substrate; forming an AlGaN layer on the GaN channel layer; forming a p-GaN gate layer on the AlGaN layer; forming a nitrogen-rich TiN hard mask layer on the p-GaN gate layer, wherein a nitrogen-to-titanium ratio (N / Ti) of the nitrogen-rich TiN hard mask layer is greater than 1.0; and forming a gate electrode layer on the nitrogen-rich TiN hard mask layer.

[0016] According to an embodiment of the present invention, the method further includes: forming a buffer layer on the substrate, wherein the buffer layer is located between the substrate and the GaN channel layer.

[0017] According to an embodiment of the present invention, the buffer layer includes AlN or GaN, and the thickness of the buffer layer is 3-5 μm.

[0018] According to the embodiment of the present invention, the thickness of the GaN channel layer is 200-400 nm, the thickness of the AlGaN layer is 10-14 nm, and the thickness of the p-GaN gate layer is 60-100 nm.

[0019] According to an embodiment of the present invention, the nitrogen-rich TiN hard mask layer is formed on the p-GaN gate layer by sputtering at a direct current (DC) power equal to or greater than 4000W.

[0020] According to an embodiment of the present invention, the nitrogen-rich TiN hard mask layer is formed on the p-GaN gate layer by sputtering at a DC power of 7500-8500W.

[0021] According to an embodiment of the present invention, the gate electrode layer includes a TiN bottom layer, an AlCu middle layer and a TiN top layer, and the TiN bottom layer is in direct contact with the nitrogen-rich TiN hard mask layer.

[0022] According to an embodiment of the present invention, a nitrogen-to-titanium ratio of the nitrogen-rich TiN hard mask layer is equal to or greater than 1.04.

[0023] According to an embodiment of the present invention, the method further comprises: forming an AlGaN layer covering the sidewalls of the p-GaN gate layer, the sidewalls of the nitrogen-rich TiN hard mask layer, and the top surface of the AlGaN layer. 2 O 3 Passivation layer.

[0024] According to an embodiment of the present invention, the method further comprises: in Al 2 O 3 An insulating layer is formed on the passivation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A partial cross-sectional schematic diagram of a GaN semiconductor device depicted in an embodiment of the present invention;

[0026] Figure 2 The present invention is a flow chart of a method for manufacturing a GaN semiconductor device.

[0027] Main component symbols

[0028] 1GaN semiconductor devices

[0029] 100 substrate

[0030] 102 buffer layer

[0031] 104GaN channel layer

[0032] 106AlGaN layer

[0033] 106a two-dimensional electron cloud

[0034] 108p-GaN gate layer

[0035] 110 Nitrogen-rich TiN hard mask layer

[0036] 111Al 2 O 3 Passivation layer

[0037] 112 insulation layer

[0038] 112a opening

[0039] 120 gate electrode layer

[0040] 122TiN bottom layer

[0041] 124AlCu intermediate layer

[0042] 126TiN top layer

[0043] Steps 21-25 DETAILED DESCRIPTION

[0044] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0045] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0046] See also Figure 1 , which is a partial cross-sectional schematic diagram of a GaN semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the GaN semiconductor device 1 includes a substrate 100, for example, a silicon substrate with a (111) crystal plane, but not limited thereto. According to an embodiment of the present invention, the GaN semiconductor device 1 may be a p-GaN / AlGaN / GaN high electron mobility transistor (HEMT) device.

[0047] According to the embodiment of the present invention, a buffer layer 102 and a GaN channel layer 104 are formed on a substrate 100. The buffer layer 102 and the GaN channel layer 104 may be formed using an epitaxial process, such as a metalorganic chemical vapor deposition (MOCVD) process or a molecular beam epitaxy (MBE) process, but is not limited thereto.

[0048] According to an embodiment of the present invention, the buffer layer 102 may include AlN or GaN. According to an embodiment of the present invention, the thickness of the buffer layer 102 is, for example, 3 to 5 μm, but is not limited thereto. According to an embodiment of the present invention, the thickness of the GaN channel layer 104 is, for example, 200 to 400 nm, but is not limited thereto.

[0049] According to the embodiment of the present invention, the GaN semiconductor device 1 further includes an AlGaN layer 106 disposed on the GaN channel layer 104. According to the embodiment of the present invention, the thickness of the AlGaN layer 106 is, for example, 10-14 nm, but is not limited thereto.

[0050] According to the embodiment of the present invention, a two-dimensional electron cloud (2DEG) 106a is formed at the interface between the AlGaN layer 106 and the GaN channel layer 104. The two-dimensional electron cloud 106a is a very thin conductive layer with highly mobile and highly concentrated charge carriers.

[0051] According to an embodiment of the present invention, the GaN semiconductor device 1 further includes a patterned p-GaN gate layer 108 disposed on the AlGaN layer 106. According to an embodiment of the present invention, the p-GaN gate layer 108 can also be formed using an epitaxial process, such as a metal organic chemical vapor deposition process or molecular beam epitaxy, but is not limited thereto. According to an embodiment of the present invention, the thickness of the p-GaN gate layer 108 is, for example, 60 to 100 nm, but is not limited thereto.

[0052] According to an embodiment of the present invention, Figure 1 As shown in the partial enlarged view in , the GaN semiconductor device 1 also includes a patterned nitrogen-rich TiN hard mask layer 110, which is disposed on the p-GaN gate layer 108, wherein the nitrogen-to-titanium ratio (N / Ti) of the nitrogen-rich TiN hard mask layer 110 is greater than 1.0. According to an embodiment of the present invention, the nitrogen-to-titanium ratio of the entire nitrogen-rich TiN hard mask layer 110 is greater than 1.0. According to an embodiment of the present invention, for example, the nitrogen-to-titanium ratio of the nitrogen-rich TiN hard mask layer 110 may be between 1.0 and 1.2. According to an embodiment of the present invention, the N / Ti ratio of the nitrogen-rich TiN hard mask layer 110 is equal to or greater than 1.04.

[0053] According to an embodiment of the present invention, the nitrogen-rich TiN hard mask layer 110 can be formed by a physical vapor deposition (PVD) coating process such as sputtering, and the deposition conditions include: a DC power greater than 4000W, for example, 7500-8500W, an argon / nitrogen (Ar / N 2 ) gas flow ratio was 30 / 100, and deposition was performed at room temperature.

[0054] The present invention forms a nitrogen-rich TiN hard mask layer 110 using direct current high power to control the nitrogen-titanium ratio between 1.0 and 1.2, which can reduce electron capture in the p-GaN gate layer when the GaN semiconductor device 1 is in operation, thereby improving the reliability of the GaN semiconductor device 1 .

[0055] According to an embodiment of the present invention, patterning of the p-GaN gate layer 108 and the nitrogen-rich TiN hard mask layer 110 may be accomplished by using a photolithography process and a dry etching process.

[0056] According to an embodiment of the present invention, the GaN semiconductor device 1 further includes a gate electrode layer 120, which is disposed on the nitrogen-rich TiN hard mask layer 110. According to an embodiment of the present invention, for example, the gate electrode layer 120 may include a TiN bottom layer 122, an AlCu middle layer 124, and a TiN top layer 126. According to an embodiment of the present invention, the TiN bottom layer 122 is in direct contact with the nitrogen-rich TiN hard mask layer 110, and the TiN bottom layer 122 may be slightly sunken into the upper surface of the nitrogen-rich TiN hard mask layer 110.

[0057] According to an embodiment of the present invention, the GaN semiconductor device 1 further includes an Al 2 O 3 The passivation layer 111 covers the sidewalls of the p-GaN gate layer 108 , the sidewalls of the nitrogen-rich TiN hard mask layer 110 , and the top surface of the AlGaN layer 106 .

[0058] According to an embodiment of the present invention, the GaN semiconductor device 1 further includes an insulating layer 112, for example, a tetraethoxysilane (TEOS) silicon oxide layer, disposed on the Al 2 O 3 According to the embodiment of the present invention, the insulating layer 112 and the Al 2 O 3 An opening 112 a is formed in the passivation layer 111 , and the gate electrode layer 120 is filled in the opening 112 a , so that the gate electrode layer 120 and the nitrogen-rich TiN hard mask layer 110 are electrically connected.

[0059] See also Figure 2 , which is a flow chart of a method for manufacturing a GaN semiconductor device 1, wherein the same layers, regions or components are still represented by the same symbols. Figure 2 As shown, first, step 21 is performed to provide a substrate 100 , and a buffer layer 102 , a GaN channel layer 104 , an AlGaN layer 106 and a p-GaN gate layer 108 are sequentially formed on the substrate 100 .

[0060] According to an embodiment of the present invention, the buffer layer 102 may include AlN or GaN, and the thickness of the buffer layer 102 is, for example, 3 to 5 μm. According to an embodiment of the present invention, the thickness of the GaN channel layer 104 is, for example, 200 to 400 nm, the thickness of the AlGaN layer 106 is, for example, 10 to 14 nm, and the thickness of the p-GaN gate layer 108 is, for example, 60 to 100 nm.

[0061] Next, step 22 is performed to form a nitrogen-rich TiN hard mask layer 110 on the p-GaN gate layer 108 by using a physical vapor deposition (PVD) coating process at a DC power greater than 4000 W, for example, a DC power of 7500-8500 W, wherein the nitrogen-to-titanium ratio of the nitrogen-rich TiN hard mask layer 110 is greater than 1.0. According to an embodiment of the present invention, the nitrogen-to-titanium ratio of the nitrogen-rich TiN hard mask layer 110 is equal to or greater than 1.04.

[0062] Next, step 23 is performed to perform a photolithography process and a dry etching process to pattern the nitrogen-rich TiN hard mask layer 110 and the p-GaN gate layer 108 .

[0063] Next, step 24 is performed to deposit Al 2 O 3 The passivation layer 111 conformally covers the top surface and sidewalls of the p-GaN gate layer 108, the sidewalls of the nitrogen-rich TiN hard mask layer 110, and the top surface of the AlGaN layer 106. 2 O 3 An insulating layer 112 is formed on the passivation layer. According to an embodiment of the present invention, for example, the insulating layer 112 may include a tetraethoxysilane (TEOS) silicon oxide layer, but is not limited thereto.

[0064] Next, step 25 is performed to perform a metallization process, before the insulating layer 112 and the Al 2 O 3 An opening 112 a is formed in the passivation layer 111 to expose a portion of the upper surface of the nitrogen-rich TiN hard mask layer 110 , and then a gate electrode layer 120 is formed to fill the opening 112 a and be electrically connected to the nitrogen-rich TiN hard mask layer 110 .

[0065] According to an embodiment of the present invention, the gate electrode layer 120 may include a TiN bottom layer 122, an AlCu middle layer 124 and a TiN top layer 126, wherein the TiN bottom layer 122 is in direct contact with the nitrogen-rich TiN hard mask layer 110. Subsequent steps include the fabrication of source and drain contacts, which are well-known techniques and are not described in detail.

[0066] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A GaN semiconductor device, comprising: substrate; A GaN channel layer is disposed on the substrate; An AlGaN layer is disposed on the GaN channel layer; A p-GaN gate layer, disposed on the AlGaN layer; a nitrogen-rich TiN hard mask layer, disposed on the p-GaN gate layer, wherein a nitrogen-to-titanium ratio (N / Ti) of the nitrogen-rich TiN hard mask layer is greater than 1.0; and The gate electrode layer is disposed on the nitrogen-rich TiN hard mask layer.

2. The GaN semiconductor device according to claim 1, characterized in that: Also includes: A buffer layer is located on the substrate, wherein the buffer layer is arranged between the substrate and the GaN channel layer.

3. The GaN semiconductor device according to claim 2, characterized in that: The buffer layer includes AlN or GaN, and the thickness of the buffer layer is 3-5 μm.

4. The GaN semiconductor device according to claim 1, characterized in that: The thickness of the GaN channel layer is 200-400 nm.

5. The GaN semiconductor device according to claim 1, characterized in that: The thickness of the AlGaN layer is 10-14 nm.

6. The GaN semiconductor device according to claim 1, characterized in that: The thickness of the p-GaN gate layer is 60-100 nm.

7. The GaN semiconductor device according to claim 1, characterized in that: The gate electrode layer includes a TiN bottom layer, an AlCu middle layer and a TiN top layer, and the TiN bottom layer is in direct contact with the nitrogen-rich TiN hard mask layer.

8. The GaN semiconductor device according to claim 1, characterized in that: The nitrogen-rich TiN hard mask layer has an N / Ti ratio equal to or greater than 1.

04.

9. The GaN semiconductor device according to claim 1, characterized in that: Also includes: An Al2O3 passivation layer covers the sidewalls of the p-GaN gate layer, the sidewalls of the nitrogen-rich TiN hard mask layer and the top surface of the AlGaN layer.

10. The GaN semiconductor device according to claim 9, characterized in that: Also includes: The insulating layer is disposed on the Al2O3 passivation layer.

11. A method for manufacturing a GaN semiconductor device, comprising: providing a substrate; forming a GaN channel layer on the substrate; forming an AlGaN layer on the GaN channel layer; forming a p-GaN gate layer on the AlGaN layer; forming a nitrogen-rich TiN hard mask layer on the p-GaN gate layer, wherein a nitrogen-to-titanium ratio (N / Ti) of the nitrogen-rich TiN hard mask layer is greater than 1.0; and A gate electrode layer is formed on the nitrogen-rich TiN hard mask layer.

12. The manufacturing method according to claim 11, characterized in that: Also includes: A buffer layer is formed on the substrate, wherein the buffer layer is located between the substrate and the GaN channel layer.

13. The manufacturing method according to claim 12, characterized in that: The buffer layer includes AlN or GaN, and the thickness of the buffer layer is 3-5 μm.

14. The manufacturing method according to claim 11, characterized in that: The thickness of the GaN channel layer is 200-400 nm, the thickness of the AlGaN layer is 10-14 nm, and the thickness of the p-GaN gate layer is 60-100 nm.

15. The manufacturing method according to claim 11, characterized in that: The nitrogen-rich TiN hard mask layer is formed on the p-GaN gate layer by sputtering at a direct current (DC) power equal to or greater than 4000W.

16. The manufacturing method according to claim 11, characterized in that: The nitrogen-rich TiN hard mask layer is formed on the p-GaN gate layer by sputtering at a DC power of 7500-8500W.

17. The manufacturing method according to claim 11, characterized in that: The gate electrode layer includes a TiN bottom layer, an AlCu middle layer and a TiN top layer, and the TiN bottom layer is in direct contact with the nitrogen-rich TiN hard mask layer.

18. The manufacturing method according to claim 11, characterized in that: The nitrogen-rich TiN hard mask layer has a nitrogen-to-titanium ratio equal to or greater than 1.

04.

19. The manufacturing method according to claim 11, characterized in that: Also includes: An Al2O3 passivation layer is formed covering the sidewalls of the p-GaN gate layer, the sidewalls of the nitrogen-rich TiN hard mask layer, and the top surface of the AlGaN layer.

20. The manufacturing method according to claim 19, characterized in that: Also includes: An insulating layer is formed on the Al2O3 passivation layer.

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