Electrostatic discharge semiconductor device and manufacturing method thereof

Abstract

The invention discloses an electrostatic discharge semiconductor device and a manufacturing method thereof. The electrostatic discharge semiconductor device comprises a substrate and an epitaxial layer, the first well region is provided with a first doping type and extends from the surface of the epitaxial layer to the surface of the substrate; the second well region and the third well region are provided with a second doping type and are positioned on two sides of the first well region; the fourth well region is provided with the second doping type and extends in the first well region; the fifth well region and the sixth well region are provided with the first doping type and are symmetrically distributed on the two sides of the fourth well region; and the first injection region and the second injection region are respectively provided with a first doping type and a second doping type. Second injection regions in a second well region and a third well region and first injection regions in a fifth well region and a sixth well region of the electrostatic discharge semiconductor device are connected to a cathode, and all injection regions in a fourth well region are connected to an anode, so that a transverse triode current discharge path is formed, the maintaining voltage is improved, and the reliability of the device is improved. The avalanche breakdown voltage and the trigger voltage can be adjusted, and the electrostatic protection capability is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an electrostatic discharge semiconductor device and a manufacturing method thereof. Background Art

[0002] ESD (Electro-Static discharge) is an objective natural phenomenon that accompanies the entire product cycle. ESD is not easily perceived by the human body, but it can pose a serious threat to integrated circuit products. During the manufacturing, packaging, testing and application stages of the chip, its external environment and internal structure will accumulate a certain amount of charge and will be threatened by static electricity at any time. Therefore, in chip design, it is necessary to place ESD protection devices on each pin. LDMOS (laterally-diffused metal-oxide semiconductor) or SCR (Silicon Controlled Rectifier) ​​structures are often used as ESD protection devices.

[0003] Figure 1 A cross-sectional schematic diagram showing a prior art thyristor electrostatic protection semiconductor device, Figure 2 Shown corresponding to Figure 1 The circuit structure diagram of the SCR structure. Figure 1 and Figure 2 As shown, the electrostatic protection device of the SCR structure includes a P-type substrate 10, an N-type well region 30 and a P-type well region 20 located on the upper part of the substrate 10, a P+ injection region 14 and an N+ injection region 13 are formed in the N-type well region 30, and a P+ injection region 12 and an N+ injection region 11 are formed in the P-type well region 20. The cathode is connected to the P+ injection region 12 and the N+ injection region 11, and the anode is connected to the P+ injection region 14 and the N+ injection region 13. The SCR path of the traditional unidirectional SCR device is composed of the P+ injection region 14, the N-type well region 30, the P-type well region 20 and the N+ injection region 11. When the ESD pulse comes, a positive pulse appears at the anode end, and the reverse biased PN junction composed of the N-type well region 30 and the P-type well region 20 will undergo avalanche breakdown, thereby generating a large number of carriers, which continuously flow through the parasitic well resistance Rp on the P-type well region 20, causing the voltage drop Vbe between the base and the emitter of the lateral parasitic NPN transistor to increase. Until Vbe is greater than 0.7V, the lateral parasitic NPN transistor is triggered and works in the amplification region, and the amplified collector current will flow into the base of the parasitic PNP transistor, and finally the parasitic PNP transistor is turned on. At this time, the parasitic NPN transistor and the parasitic PNP transistor form an effective positive feedback, and finally a low-resistance lateral SCR discharge path is formed, with a high trigger voltage, a small holding voltage, and a latch effect that is prone to occur. Therefore, the electrostatic protection capability of the current SCR structure electrostatic protection device is relatively poor. Summary of the invention

[0004] In view of the above problems, an object of the present invention is to provide an electrostatic discharge semiconductor device and a manufacturing method thereof to solve the problems in the prior art.

[0005] According to one aspect of the present invention, an electrostatic discharge semiconductor device is provided, comprising: a substrate having a first doping type; an epitaxial layer located above the substrate; a first well region having a first doping type, extending from the surface of the epitaxial layer to the surface of the substrate; a second well region and a third well region having a second doping type, extending from the surface of the epitaxial layer to the surface of the substrate, and being located on both sides of the first well region and separated from the first well region; a fourth well region having a first doping type, extending from the surface of the first well region to the inside and separated from the substrate; a fifth well region and a sixth well region having a second doping type, extending from the surface of the first well region to the inside and separated from the substrate, the fifth well region and the sixth well region are symmetrically distributed on both sides of the fourth well region and separated from the fourth well region; a first injection region, distributed in the upper parts of the fourth well region, the fifth well region and the sixth well region, having a first doping type; and a second injection region, distributed in the upper parts of the second well region, the third well region and the fourth well region, having a second doping type, wherein the second injection region in the second well region and the third well region and the first injection region in the fifth well region and the sixth well region are all connected to the cathode, and the first injection region and the second injection region in the fourth well region are all connected to the anode.

[0006] Optionally, the electrostatic discharge semiconductor device also includes: a first drift region having a first doping type, located in the first well region, surrounding the fifth well region and separated from the fourth well region; and a second drift region having the first doping type, located in the first well region, surrounding the sixth well region and separated from the fourth well region.

[0007] Optionally, an avalanche breakdown voltage between the first drift region, the second drift region and the fourth well region and a trigger voltage of the electrostatic discharge semiconductor device decrease as the distance between the first drift region, the second drift region and the fourth well region decreases.

[0008] Optionally, when the semiconductor device is working, the triode structure composed of the first injection region in the fourth well region, the fourth well region, the first well region, the fifth well region and the sixth well region, and the first injection region in the fifth well region and the sixth well region is turned on to form a first current discharge path from the anode to the cathode.

[0009] Optionally, when the electrostatic discharge semiconductor device is working, the thyristor structure composed of the first injection region, the fourth well region, the first well region, the second well region and the third well region in the fourth well region and the second injection region in the second well region and the third well region is turned on to form a second current discharge path from the anode to the cathode.

[0010] Optionally, the electrostatic discharge semiconductor device also includes: a buried layer having a second doping type, located in the upper part of the substrate, contacting the first well region to the third well region, the first injection region having the highest doping concentration among all regions having the first doping type, the second injection region having the highest doping concentration among all regions having the second doping type, and the doping concentration of the buried layer is second only to the larger one of the first injection region and the second injection region.

[0011] Optionally, when the electrostatic discharge semiconductor device is working, the thyristor structure composed of the first injection region in the fourth well region, the fourth well region, the first well region, the buried layer, the second well region and the third well region, and the second injection region in the second well region and the third well region is turned on to form a third current discharge path from the anode to the cathode.

[0012] Optionally, when the electrostatic discharge semiconductor device receives an electrostatic pulse, the first current discharge path is opened before the second current discharge path and the third current discharge path, and the second current discharge path is opened before the third current discharge path; and the current on the first current discharge path is smaller than the current on the second current discharge path, and the current on the second current discharge path is smaller than the current on the third current discharge path.

[0013] Optionally, the doping concentration of the first injection region in the fifth well region and the sixth well region is greater than the doping concentration of the fifth well region and the sixth well region, the doping concentration of the fifth well region and the sixth well region is greater than the doping concentration of the first drift region and the second drift region, and the doping concentration of the first drift region and the second drift region is greater than the doping concentration of the first well region.

[0014] Optionally, the electrostatic discharge semiconductor device also includes: a field oxide layer, distributed between the first injection region and the second injection region of each well region of the electrostatic discharge semiconductor device; a gate oxide layer, located above the fourth well region, the field oxide layer between the fifth well region and the sixth well region and the gap between the fourth well region is in contact with the gate oxide layer; and a field plate layer, covering the surface of the gate oxide layer and a portion of the surface of the field oxide layer in contact with the gate oxide layer, the field plate layer being connected to the cathode.

[0015] Optionally, the electrostatic discharge semiconductor device is a dual-finger structure.

[0016] Optionally, the first doping type is P-type doping, and the second doping type is N-type doping.

[0017] According to another aspect of the present invention, a method for manufacturing an electrostatic discharge semiconductor device is provided, comprising: forming a substrate having a first doping type and a buried layer having a second doping type located in an upper portion of the substrate; forming an epitaxial layer located above the substrate, the epitaxial layer covering the buried layer; forming a first well region having the first doping type extending inward from the surface of the epitaxial layer and extending to the surface of the buried layer; forming a second well region and a third well region having the second doping type extending inward from the surface of the epitaxial layer and extending to the surface of the buried layer, the second well region and the third well region being located on both sides of the first well region and being separated from the first well region; forming a fourth well region having the first doping type extending inward from the surface of the first well region and being separated from the buried layer; forming a fourth well region extending inward from the surface of the first well region and being separated from the buried layer; A first drift region and a second drift region with a first doping type, the first drift region and the second drift region are symmetrically distributed on both sides of the fourth well region and separated from the fourth well region; a fifth well region and a sixth well region with a first doping type are formed in the first drift region and the second drift region respectively; a plurality of spaced field oxide layers are formed on the upper part and the outside of the epitaxial layer; and a plurality of spaced first injection regions and second injection regions are formed in each well region with the field oxide layers as intervals, the first injection region and the second injection region have a first doping type and a second doping type, respectively, wherein the second well region and the second injection region in the third well region and the first injection region in the fifth well region and the sixth well region are connected to a cathode, and the first injection region and the second injection region in the fourth well region are connected to an anode.

[0018] According to another aspect of the present invention, there is provided an integrated circuit, comprising: the electrostatic discharge semiconductor device described above.

[0019] The electrostatic discharge semiconductor device and its manufacturing method provided by the present invention only set the second injection area in the second well area and the third well area, and do not set the first injection area, so that a resistor structure in the SCR structure can be omitted. In addition, an independent triode current discharge path (first current discharge path) is formed by setting the fifth well area connected to the cathode and the P+ injection area in the fifth well area, the sixth well area and the P+ injection area in the sixth well area. The first current discharge path is very easy to open, and the trigger voltage of the device is low, which forms a good protection effect for the device. The device itself also has a lateral SCR discharge path (second current discharge path), and the maintenance voltage of the device is improved by the cooperation of the two current discharge paths. In addition, the avalanche breakdown voltage between the well areas can be adjusted by adjusting the distance between the fifth well area and the sixth well area and the fourth well area to adjust the trigger voltage of the device. Thereby improving the electrostatic protection capability of the electrostatic discharge semiconductor device, reducing the device size, and simplifying the manufacturing process. Furthermore, the shorter the distance between the fifth well region and the sixth well region and the fourth well region, the smaller the avalanche breakdown voltage and the trigger voltage of the electrostatic discharge semiconductor device, the better the device protection performance, and it is suitable for electrostatic protection in the low voltage range (5V-50V).

[0020] Furthermore, the electrostatic discharge semiconductor device of this embodiment adds a first drift region and a second drift region, so that the ion doping concentration between the fifth well region and the sixth well region and the fourth well region is further adjusted, reducing the carrier migration efficiency on the device surface, further reducing the current amplification factor, and increasing the holding voltage. The distance between the fifth well region and the sixth well region and the fourth well region also has a wider adjustment range, so that the adjustment range of the avalanche breakdown voltage and the trigger voltage of the electrostatic discharge semiconductor device is wider, which can be applied to electrostatic protection of higher voltage (0V-100V).

[0021] Furthermore, a heavily doped buried layer is formed on the upper part of the substrate of the electrostatic discharge semiconductor device, so that a longitudinal SCR current discharge path (third current discharge path) can be formed on the basis of the original SCR lateral current discharge path (second current discharge path) and the independent triode current discharge path (first current discharge path). The longitudinal SCR current discharge path can increase the SCR conduction maintenance voltage. Since the buried layer is heavily doped, the longitudinal third current discharge path gradually becomes the dominant current discharge path, realizing current discharge inside the device and avoiding the accumulation of discharge heat on the surface of the device. Moreover, the buried layer and the substrate, as well as the second well region and the third well region and the epitaxial layer provide good internal and external isolation for the device to prevent leakage.

[0022] Furthermore, the first current discharge path is opened before the second and third discharge paths, and the path is shorter, and the trigger voltage of the device is lower, so that the current can be discharged faster when the electrostatic pulse comes, protecting the device. Using the third current discharge path as the main discharge path can extend the current discharge path and increase the holding voltage of the device.

[0023] Furthermore, a field plate layer connected to the cathode is provided, so that the electric field distribution in the fourth well region is improved, and the peak electric field below the field plate layer changes more smoothly, thereby improving the reliability and forward withstand voltage of the device.

[0024] Furthermore, the electrostatic discharge semiconductor device adopts a dual-finger structure to achieve layout symmetry, which increases the failure current of the device and improves the electrostatic protection performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0026] Figure 1 A cross-sectional schematic diagram showing a prior art thyristor electrostatic protection semiconductor device;

[0027] Figure 2 Shown corresponding to Figure 1 Schematic diagram of the circuit structure of the SCR structure;

[0028] Figure 3 A schematic cross-sectional view of an electrostatic discharge semiconductor device according to an embodiment of the present invention is shown;

[0029] Figure 4 Shown corresponding to Figure 3 Schematic diagram of the circuit structure of the SCR structure;

[0030] Figure 5a-5d Schematic cross-sectional views showing various stages of a method for manufacturing an electrostatic discharge semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0032] When describing the structure of a device, when a layer or a region is referred to as being "on" or "above" another layer or another region, it may mean being directly above the other layer or another region, or having other layers or regions between it and the other layer or another region. Furthermore, if the device is turned over, the layer or the region will be "below" or "beneath" the other layer or another region. In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.

[0033] Unless otherwise specified below, the various layers or regions of the semiconductor device can be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si and Ge. The gate conductor and electrode layer can be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni 3 Si, Pt, Ru, W, and combinations of the various conductive materials.

[0034] Figure 3 FIG. 4 is a schematic cross-sectional view of an electrostatic discharge semiconductor device according to an embodiment of the present invention, Figure 4 Shown corresponding to Figure 3 Schematic diagram of the circuit structure of the SCR structure.

[0035] like Figure 3 As shown, the electrostatic discharge semiconductor device 100 of this embodiment includes a substrate 101 and a buried layer 102 located in the upper part of the substrate 101, and an epitaxial layer 103 located above the substrate 101. The substrate 101 has a first doping type, the buried layer 102 has a second doping type, the buried layer 102 is located inside the substrate 101 and on the top of the substrate 101, and the upper surface of the buried layer 102 is flush with the upper surface of the substrate 101. In this embodiment, the first doping type can be P-type doping, and the second doping type can be N-type doping. Of course, in other embodiments, the first doping type can also be N-type doping, and the second doping type can also be P-type doping. The epitaxial layer 103 covers the buried layer 102, and the epitaxial layer 103 can be P-type doping or N-type doping. In this embodiment, the epitaxial layer 103 is, for example, P-type doping.

[0036] Furthermore, the epitaxial layer 103 is provided with a first well region 104, a second well region 105, and a third well region 106. The first well region 104, the second well region 105, and the third well region 106 all extend from the upper surface of the epitaxial layer 103 to the inside, and the bottom is in contact with the buried layer 102, that is, the implantation depth of the first well region 104, the second well region 105, and the third well region 106 is the same as the thickness of the epitaxial layer 103. The first well region 104 has a first doping type, for example, P-type doping, and the second well region 105 and the third well region 106 have a second doping type, for example, N-type doping, that is, the first well region 104 is a P-type well region, and the second well region 105 and the third well region 106 are N-type well regions. Moreover, in the lateral direction, the first well region 104 is distributed in the middle of the epitaxial layer 103, and the second well region 105 and the third well region 106 are distributed on both sides of the first well region 104 and are separated from the first well region 104 by a certain distance. The second well region 105 and the third well region 106 are symmetrically distributed on both sides of the first well region 104, for example.

[0037] Furthermore, the first well region 104 also includes a fourth well region 107, a fifth well region 108, and a sixth well region 109. The fourth well region 107, the fifth well region 108, and the sixth well region 109 all extend from the upper surface of the first well region 104 to the inside, and the bottom is separated from the buried layer 102, that is, the injection depths of the fourth well region 107, the fifth well region 108, and the sixth well region 109 are all less than the injection depth of the first well region 104. Moreover, the injection depths of the fourth well region 107, the fifth well region 108, and the sixth well region 109 can be the same. In this embodiment, the fourth well region 107 has a second doping type, such as N-type doping, and the fifth well region 108 and the sixth well region 109 have a first doping type, such as P-type doping, that is, the fifth well region 108 and the sixth well region 109 are P-type well regions, and the fourth well region 107 is an N-type well region. Moreover, in the lateral direction, the fourth well region 107 is distributed in the middle of the first well region 104, and the fifth well region 108 and the sixth well region 109 are distributed on both sides of the fourth well region 107 and are separated from the fourth well region 107 by a certain distance. The fifth well region 108 and the sixth well region 109 are, for example, symmetrically distributed on both sides of the fourth well region 107.

[0038] A first injection region and a second injection region are distributed in the fourth well region 107, and the first injection region and the second injection region have a first doping type and a second doping type, respectively, that is, the first injection region can be a P+ injection region, and the second injection region can be an N+ injection region. For example, a P+ injection region 122, an N+ injection region 112, and a P+ injection region 123 are distributed in the fourth well region 107 at intervals. An N+ injection region 111 is distributed in the second well region 105, and an N+ injection region 113 is distributed in the third well region 106. A P+ injection region 121 is distributed in the fifth well region 108, and a P+ injection region 124 is distributed in the sixth well region 109. The injection regions are all formed on the upper part of each well region, and can be formed by injecting from the surface of the well region to the inside. A plurality of field oxide layers are also distributed between the gaps between each well region and the injection region, such as field oxide layer 181, field oxide layer 182, field oxide layer 183, field oxide layer 184, field oxide layer 185, field oxide layer 186, field oxide layer 187 and field oxide layer 188, and the plurality of field oxide layers sequentially separate the plurality of injection regions. In addition, the N+ injection region 111 in the second well region 105, the N+ injection region 113 in the third well region 106, the P+ injection region 121 in the fifth well region 108 and the P+ injection region 124 in the sixth well region 109 are all connected to the cathode, and the P+ injection region 122, the N+ injection region 112 and the P+ injection region 123 in the fourth well region 107 are all connected to the anode.

[0039] The presence of the fifth well region 108 and the sixth well region 109 can increase the ion doping concentration in the first well region 104 outside the fourth well region 107, reduce the carrier migration efficiency on the device surface, reduce the current amplification factor, and increase the holding voltage. By adjusting the distance between the fifth well region 108 and the sixth well region 109 and the fourth well region 107, the avalanche breakdown voltage between the well regions and the trigger voltage when the SCR is turned on can also be adjusted. Specifically, the avalanche breakdown voltage between the fifth well region 108 and the sixth well region 109 and the fourth well region 107 and the trigger voltage of the device decrease as the distance between them decreases. That is, the greater the distance between the fifth well region 108 and the sixth well region 109 and the fourth well region 107, the higher the avalanche breakdown voltage and the higher the device trigger voltage. Conversely, the smaller the distance between the fifth well region 108 and the sixth well region 109 and the fourth well region 107, the lower the avalanche breakdown voltage and the lower the device trigger voltage. Therefore, the electrostatic discharge semiconductor device can be applied to different voltage ports, for example, it can be suitable for a low voltage protection environment of 5V-50V.

[0040] Further, in order to expand the voltage protection range of the device, the electrostatic discharge semiconductor device 100 of the present embodiment further includes a first drift region 131 and a second drift region 132. The first drift region 131 has a first doping type, is located in the first well region 104, surrounds the fifth well region 108 and is separated from the fourth well region 107 by a certain distance. The second drift region 132 has a first doping type, is located in the first well region 104, surrounds the sixth well region 109 and is separated from the fourth well region 107 by a certain distance. In this embodiment, the doping concentrations of all first injection regions may be the same, and the doping concentrations of all second injection regions may be the same. Moreover, among all regions with the first doping type (including well regions, injection regions, drift regions and substrates, etc.), the doping concentration of the first injection region is the largest, and among all regions with the second doping type (including well regions, injection regions, buried layers and epitaxial layers, etc.), the doping concentration of the second injection region is also the largest. Specifically, for example, the doping concentration of the P+ injection region 121 in the fifth well region 108 and the P+ injection region 124 in the sixth well region 109 is greater than the doping concentration of the fifth well region 108 and the sixth well region 109, the doping concentration of the fifth well region 108 and the sixth well region 109 is greater than the doping concentration of the first drift region 131 and the second drift region 132, and the doping concentration of the first drift region 131 and the second drift region 132 is greater than the doping concentration of the first well region 104. Further, the doping concentration of the buried layer 102 located in the substrate 101 is second only to the one with the larger doping concentration between the first injection region and the second injection region. That is, the doping concentration of the buried layer 102 is second only to the injection region with the largest doping concentration.

[0041] The distance between the first drift region 131 and the second drift region 132 and the fourth well region 107 is BVsp. The avalanche breakdown voltage between the first drift region 131 and the second drift region 132 and the fourth well region 107 and the trigger voltage of the electrostatic discharge semiconductor device 100 decrease as the distance BVsp between the first drift region and the second drift region and the fourth well region decreases, and the upper limit of the trigger voltage is further increased at this time. In addition, the arrangement of the first drift region 131 and the second drift region 132 can further increase the ion doping concentration in the first well region 104 outside the fourth well region 107, reduce the carrier migration efficiency on the device surface, further reduce the current amplification factor and increase the holding voltage. The first drift region 131 and the second drift region 132 have the same doping type as the fifth well region 108 and the sixth well region 109, all of which are P-type doping. The existence of the first drift region 131 and the second drift region 132 makes the adjustable range of the distance between the fifth well region 108 and the sixth well region 109 and the fourth well region 107 larger and the ion concentration within the range higher, so that it can be used in a higher high voltage range, for example, in a port with a voltage range of 0V-100V.

[0042] Further, the electrostatic discharge semiconductor device 100 of the present embodiment further includes a gate oxide layer 141, a gate oxide layer 142, a field plate layer 151 and a field plate layer 152. The gate oxide layers 141 and 142 are both located above the fourth well region 107, the field oxide layer 183 between the fifth well region 108 and the fourth well region 107 is in contact with the gate oxide layer 141, and the field oxide layer 186 between the sixth well region 109 and the fourth well region 107 is in contact with the gate oxide layer 142. The field plate layer 151 covers the surface of the gate oxide layer 141 and the partial surface of the field oxide layer 183 in contact with the gate oxide layer 141, the field plate layer 152 covers the surface of the gate oxide layer 142 and the partial surface of the field oxide layer 186 in contact with the gate oxide layer 142, and the field plate layers 151 and 152 can both be polysilicon layers, and the field plate layers 151 and 152 are also connected to the cathode. The field plate layer is connected to the cathode, which can change the electric field in the fourth well region 107, so that the peak electric field below the field plate layer changes more gradually, thereby improving the reliability of the device.

[0043] In this embodiment, the electrostatic discharge semiconductor device 100 uses a double-finger structure to achieve layout symmetry, thereby enhancing the failure current. Then the electrostatic discharge semiconductor device 100 of this embodiment can be symmetrically distributed around the fourth well region 107 or around the N+ injection region 112.

[0044] Figure 4 Shows Figure 3 The corresponding SCR circuit structure is a dual-finger device, so in this embodiment, the right side is first described. Figure 4 As shown, when a positive pulse comes, a positive voltage is generated on the anode, and the electrostatic discharge semiconductor device 100 forms a PNP parasitic transistor PNP1 by the P+ injection region 123 in the fourth well region 107, the fourth well region 107 and the first well region 104 (the second drift region 132). A PNP parasitic transistor PNP2 is formed by the P+ injection region 123 in the fourth well region 107, the fourth well region 107, the first well region 104, the second drift region 132, the sixth well region 109 and the P+ injection region 124 in the sixth well region 109. The fourth well region 107, the first well region 104, the epitaxial layer 103, the third well region 106 and the N+ injection region 113 in the third well region 106 form an NPN parasitic transistor NPN1, or the fourth well region 107, the first well region 104, the sixth well region 109, the epitaxial layer 103, the third well region 106 and the N+ injection region 113 in the third well region 106 form an NPN parasitic transistor NPN1. A parasitic well resistor Rn is generated in the fourth well region 107. The forward voltage on the anode raises the voltage across the resistor Rn, turns on PNP2 and PNP1, raises the base current of NPN1, and NPN1 is also turned on.

[0045] That is, when the semiconductor device is working, the triode structure PNP2 composed of the P+ injection region 123 in the fourth well region 107, the fourth well region 107, the first well region 104, the second drift region 132, the sixth well region 109, and the P+ injection region 124 in the sixth well region 109 is turned on to form a first current discharge path P1 from the anode to the cathode. Then, the thyristor structure composed of the P+ injection region 123 in the fourth well region 107, the fourth well region 107, the first well region 104, (the second drift region 132,) the epitaxial layer 103, the third well region 106, and the N+ injection region 113 in the third well region 106 is turned on to form a PNPN SCR current discharge path from the anode to the cathode. That is Figure 4 The solid arrow in the middle shows the second current discharge path P2 from the anode to the cathode. When there is an electrostatic pulse on the cathode, a diode path from the cathode to the anode can be formed from the P+ injection region 124, the sixth well region 109, the second drift region 132, the first well region 104, the fourth well region 107 and the N+ injection region 112 to achieve the purpose of reverse withstand voltage, without the need to set up an additional diode. In this embodiment, since there is only an N+ injection region in the third well region 106, but no P+ injection region, relative to Figure 2 The SCR structure shown can save a well resistor Rp, thereby reducing the device size and lowering the manufacturing cost.

[0046] Due to the existence of the fifth well region 108, the sixth well region 109, the P+ injection region 121 and the P+ injection region 124, the parasitic transistor PNP2 becomes an independent first current discharge path P1, and the first current discharge path P1 is very easy to open, the trigger voltage of the device is low, and a good protection effect is formed for the device.

[0047] Furthermore, since a buried layer 102 is also formed in the substrate 101, the buried layer 102 provides a basis for a longitudinal current discharge path. The fourth well region 107, the first well region 104, the buried layer 102, the third well region 106 and the N+ injection region 113 in the third well region 106 form an NPN parasitic transistor NPN2. When there is an electrostatic pulse at the anode, the thyristor structure composed of the P+ injection region 123 in the fourth well region 107, the fourth well region 107, the first well region 104, the buried layer 102, the third well region 106 and the N+ injection region 113 in the third well region 106 can also be turned on to form a third current discharge path P3 from the anode to the cathode, that is, Figure 3The current discharge path shown by the dotted arrow. Since the doping concentration of the buried layer 102 is second only to the first injection region or the second injection region with the highest doping concentration, the third current discharge path P3 can be called the dominant discharge path. Then in this embodiment, the first current discharge path P1 and the second current discharge path P2 are both lateral paths, and the third current discharge path P3 is a longitudinal path. The lateral path provides base current for the longitudinal path. After PNP2 is turned on, the base current of NPN1 and NPN2 is raised. The current amplification factor of NPN2 is less than that of NPN1, so that the longitudinal path is turned on last and is the dominant path. Since a longitudinal dominant discharge path is newly added, current discharge is realized inside the device to avoid the accumulation of discharge heat on the surface of the device.

[0048] That is, when the electrostatic discharge semiconductor device 100 receives an electrostatic pulse, the first current discharge path P1 is opened before the second current discharge path P2, and the second current discharge path P2 is opened before the third current discharge path P3. After being turned on, the base current amplification factor of the parasitic transistor NPN1 is greater than that of the parasitic transistor NPN2, so the current on the second current discharge path P2 is less than the current on the third current discharge path P3, so that the third current discharge path P3 becomes the dominant current discharge path, the current path is extended, and therefore the device's holding voltage is also higher.

[0049] The above examples are all based on the structure of the right side of the semiconductor device. Since the electrostatic discharge semiconductor device 100 has a symmetrical structure, the left side actually also forms a Figure 4 The same circuit structure, in Figure 3 The corresponding current discharge path is shown in FIG. 8 , and will not be described again here.

[0050] Furthermore, the buried layer 102 and the substrate 101, the second well region 105 and the external epitaxial layer 103, and the third well region 106 and the external epitaxial layer 103 provide internal and external isolation of the device, so that the device has a good electrostatic protection effect and prevents leakage.

[0051] In summary, the electrostatic discharge semiconductor device of this embodiment forms a first current discharge path by connecting to the fifth well region of the cathode and the P+ injection region in the fifth well region, the sixth well region and the P+ injection region in the sixth well region, and the first current discharge path is very easy to open, the trigger voltage of the device is low, and a good protection effect is formed for the device. Moreover, by adjusting the distance between the first drift region and the second drift region and the fourth well region, the avalanche breakdown voltage between the well regions and the holding voltage of the device can be adjusted, so that the device can be applied to ports with different voltage ranges, and the two risks of high trigger voltage causing premature breakdown of the circuit and low holding voltage causing the device to enter latch can be effectively avoided. At the same time, due to the presence of the heavily doped buried layer, a longitudinal third current discharge path can also be formed. The third current discharge path is an internal current path and a dominant path, thereby avoiding the concentration of discharge heat on the surface of the device, which increases the failure current of the device. The field plate layer connected to the cathode can also improve the electric field distribution in the fourth well region, thereby improving the forward withstand voltage and reliability of the device.

[0052] Figure 5a-5d Schematic cross-sectional views of various stages of a method for manufacturing an electrostatic discharge semiconductor device according to an embodiment of the present invention are shown. Figure 5a-5d The process steps to produce Figure 3 To further enhance the electrostatic protection capability of the semiconductor device, the following is combined with Figure 5a-5d A method for manufacturing an electrostatic discharge semiconductor device according to an embodiment of the present application is introduced.

[0053] like Figure 5aAs shown, firstly, a substrate 101 having a first doping type and a buried layer 102 having a second doping type located at the upper part of the substrate 101 are formed. Specifically, the substrate 101 is, for example, a P-type doped silicon substrate P-SUB. A buried layer 102 is formed in the substrate 101, and the buried layer 102 is an N-type doped layer structure NBL, located at the upper part of the substrate 101, and the upper surface of the buried layer 102 is, for example, flush with the upper surface of the substrate 101. Next, an epitaxial layer is formed above the substrate 101, and the epitaxial layer 103 covers the buried layer 102. The epitaxial layer 103 can be N-type doped or P-type doped, and the P-type doped epitaxial layer 103 (PEPI) is taken as an example here. Then, a well region is implanted along the surface of the epitaxial layer 101 to form a first well region 104 (DPW) having a first doping type extending from the surface of the epitaxial layer 103 to the inside and extending to the surface of the buried layer 102. A second well region 105 (DNW) and a third well region 106 (DNW) having a second doping type are formed, which extend from the surface of the epitaxial layer 103 to the inside and extend to the surface of the buried layer 102. That is, the depths of the first well region 104, the second well region 105, and the third well region 106 can be consistent and the same as the thickness of the epitaxial layer 103. The first well region 104 is distributed in the middle position, and the second well region 105 and the third well region 106 are respectively located on both sides of the first well region 104 and are separated from the first well region 104 by a certain distance. In order to achieve layout symmetry, the electrostatic discharge semiconductor structure of this embodiment can use a double-finger structure to enhance the failure current. Here, the second well region 105 and the third well region 106 are symmetrically distributed on both sides of the first well region 104, and the lateral widths of the second well region 105 and the third well region 106 are smaller than the lateral width of the first well region 104.

[0054] Furthermore, if Figure 5bAs shown, well region implantation is performed starting from the surface of the first well region 104, and a fourth well region 107 (NW) having a second doping type extending from the surface of the first well region 104 to the inside and separated from the buried layer 102 is formed in the first well region 104. A first drift region 131 (PDRF) and a second drift region 132 (PDRF) having a first doping type extending from the surface of the first well region 104 to the inside and separated from the buried layer 102 are also formed, and the first drift region 131 and the second drift region 132 are symmetrically distributed on both sides of the fourth well region 107 and separated from the fourth well region 107. The implantation depths of the first drift region 131 and the second drift region 132 are greater than the implantation depth of the fourth well region 107. Next, a fifth well region 108 (PW) and a sixth well region 109 (PW) having the first doping type are formed in the first drift region 131 and the second drift region 132, respectively, and the injection depths of the fifth well region 108 and the sixth well region 109 are less than the injection depths of the first drift region 131 and the second drift region 132. The fourth well region 107 to the sixth well region 109 are all distributed in the first well region 104, and the bottoms of the three well regions are separated from the buried layer 102 by a certain distance, that is, the injection depths of the fourth well region 107 to the sixth well region 109 are less than the injection depth of the first well region 104. The fourth well region 107 is distributed in the middle, and the fifth well region 108 and the sixth well region 109 are symmetrically distributed on both sides of the fourth well region 107 and separated from the fourth well region 107 by a certain distance.

[0055] Then, if Figure 5cAs shown, a plurality of spaced-apart field oxide layers are formed on the upper part and the outer part of the epitaxial layer 103. Specifically, field oxygen isolation is performed on the surface of the epitaxial layer 103, that is, a plurality of mutually isolated field oxide layers are formed, such as field oxide layer 181, field oxide layer 182, field oxide layer 183, field oxide layer 184, field oxide layer 185, field oxide layer 186, field oxide layer 187 and field oxide layer 188. The field oxide layer is formed by conventional processes, for example, an oxide layer is deposited on the surface of the epitaxial layer 103, a hard mask is deposited, etching is performed using the mask, and finally field oxygen is grown at a high temperature, and then the hard mask is removed. The specific process is not described in detail. Next, a gate oxide layer 141 and a gate oxide layer 142 are formed on the surface of the fourth well region 107, the gate oxide layer 141 is adjacent to the field oxide layer between the fourth well region 107 and the fifth well region 108, and the gate oxide layer 142 is adjacent to the field oxide layer between the fourth well region 107 and the sixth well region 109. That is, the gate oxide layer 141 is adjacent to the field oxide layer 183, and the gate oxide layer 142 is adjacent to the field oxide layer 186. Field plate layers 151 and 152 are formed on the surfaces of the gate oxide layer 141 and the gate oxide layer 142, respectively. The field plate layers 151 and 152 are, for example, both polysilicon layers. The field plate layer 151 covers the gate oxide layer 141 and a portion of the field oxide layer 183, and the field plate layer 152 covers the gate oxide layer 142 and a portion of the field oxide layer 186. The process for forming the gate oxide layer and the polysilicon layer is a conventional process. The polysilicon layer is formed by, for example, chemical vapor deposition, which is not limited in detail here.

[0056] Then, if Figure 5d As shown, a plurality of first and second injection regions are formed in each well region with intervals and distributions with the plurality of field oxide layers as intervals, and the first injection region (P+ injection region) and the second injection region (N+ injection region) have a first doping type and a second doping type, respectively. Specifically, P+ or N+ injection is performed in each well region along the gaps of the plurality of field oxide layers to form a plurality of P+ injection regions or N+ injection regions. For example, an N+ injection region 111 is formed in the second well region 105 (DNW), a P+ injection region 121 is formed in the fifth well region 108 (PW), a P+ injection region 122, an N+ injection region 112 and a P+ injection region 123 are formed in the fourth well region 107 (NW), a P+ injection region 124 is formed in the sixth well region 109 (PW), and an N+ injection region 113 is formed in the third well region 106 (DNW).

[0057] In this embodiment, the doping concentrations of all P+ implantation regions may be the same, and the doping concentrations of all N+ implantation regions may be the same. Moreover, among all regions with the first doping type (including well regions, implantation regions, drift regions, and substrates, etc.), the doping concentration of the P+ implantation region is the largest, and among all regions with the second doping type (including well regions, implantation regions, buried layers, and epitaxial layers, etc.), the doping concentration of the N+ implantation region is also the largest. The doping concentration of the buried layer 102 located in the substrate 101 is second only to the larger doping concentration of the P+ implantation region and the N+ implantation region.

[0058] Further, the anode and cathode of the semiconductor device are formed, wherein the N+ injection region 111 in the second well region 105, the N+ injection region 113 in the third well region 106, the field plate layer 151, the field plate layer 152, the P+ injection region 121 in the fifth well region 108, and the P+ injection region 124 in the sixth well region 109 are all connected to the cathode. The P+ injection region 122 and the P+ injection region 123 in the fourth well region 107 and the N+ injection region 112 are all connected to the anode to form Figure 3 The process of manufacturing the electrode layer above each injection region is omitted here.

[0059] In addition, the present invention also provides an integrated circuit, which includes the electrostatic discharge semiconductor device described in the above embodiment.

[0060] In summary, the electrostatic discharge semiconductor device and its manufacturing method and integrated circuit of the embodiment of the present invention are used, and only the second injection area is set in the second well area and the third well area, and the first injection area is not set, so that a resistor structure in the SCR structure can be omitted, and the device size is reduced. In addition, a triode lateral current discharge path (first current discharge path) is formed by setting the fifth well area connected to the cathode and the P+ injection area in the fifth well area, the sixth well area and the P+ injection area in the sixth well area. The first current discharge path is opened before the second discharge path, the path is shorter, and the trigger voltage of the device is low, so that the current can be discharged faster when the electrostatic pulse comes, protecting the device.

[0061] Further, the fifth well region and the sixth well region are set, and the avalanche breakdown voltage between the well regions is adjusted by adjusting the distance between the fifth well region and the sixth well region and the fourth well region, so as to adjust the trigger voltage of the device and enhance the electrostatic protection capability of the electrostatic discharge semiconductor device. The shorter the distance between the fifth well region and the sixth well region and the fourth well region, the smaller the avalanche breakdown voltage and the trigger voltage of the electrostatic discharge semiconductor device, the better the device protection performance, and the electrostatic protection under the low voltage range (5V-50V). Moreover, the first drift region and the second drift region are added, so that the ion doping concentration between the fifth well region and the sixth well region and the fourth well region is further adjusted, the carrier migration efficiency on the surface of the device is reduced, the current amplification factor is further reduced, and the holding voltage is increased. And the distance between the first drift region and the second drift region and the fourth well region has a wider adjustment range, so that the adjustment range of the avalanche breakdown voltage and the trigger voltage of the electrostatic discharge semiconductor device is wider, which can be applied to electrostatic protection under high voltage (0-100V).

[0062] Furthermore, a heavily doped buried layer is formed on the upper part of the substrate of the electrostatic discharge semiconductor device, so that a longitudinal SCR current discharge path (third current discharge path) can be formed on the basis of the original SCR lateral current discharge path (second current discharge path) and the independent triode current discharge path (first current discharge path), and the longitudinal SCR current discharge path can increase the SCR conduction maintenance voltage. Since the buried layer is heavily doped, the longitudinal third current discharge path gradually becomes the dominant current discharge path, realizing current discharge inside the device and avoiding the accumulation of discharge heat on the device surface.

[0063] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. An electrostatic discharge semiconductor device, comprising: a substrate having a first doping type; an epitaxial layer located above the substrate; a first well region having a first doping type and extending from a surface of the epitaxial layer to a surface of the substrate; A second well region and a third well region, having a second doping type, extending from the surface of the epitaxial layer to the surface of the substrate, and respectively located on both sides of the first well region and separated from the first well region; a fourth well region, having a second doping type, extending inwardly from a surface of the first well region and spaced apart from the substrate; A fifth well region and a sixth well region, having a first doping type, extending from the surface of the first well region to the inside and separated from the substrate, the fifth well region and the sixth well region being symmetrically distributed on both sides of the fourth well region and separated from the fourth well region; A first implantation region, distributed in upper portions of the fourth well region, the fifth well region and the sixth well region, having a first doping type; as well as The second implantation region is distributed in the upper part of the second well region, the third well region and the fourth well region and has a second doping type. The second injection region in the second well region and the third well region and the first injection region in the fifth well region and the sixth well region are all connected to the cathode, and the first injection region and the second injection region in the fourth well region are both connected to the anode.

2. The electrostatic discharge semiconductor device according to claim 1, further comprising: a first drift region having a first doping type, located in the first well region, surrounding the fifth well region and separated from the fourth well region; as well as The second drift region has a first doping type, is located in the first well region, surrounds the sixth well region and is separated from the fourth well region.

3. The electrostatic discharge semiconductor device according to claim 2, wherein: An avalanche breakdown voltage between the first drift region, the second drift region and the fourth well region and a trigger voltage of the electrostatic discharge semiconductor device decrease as a distance separating the first drift region, the second drift region and the fourth well region decreases.

4. The electrostatic discharge semiconductor device according to claim 1, wherein: When the semiconductor device is working, the triode structure composed of the first injection region in the fourth well region, the fourth well region, the first well region, the fifth well region and the sixth well region, and the first injection region in the fifth well region and the sixth well region is turned on to form a first current discharge path from the anode to the cathode.

5. The electrostatic discharge semiconductor device according to claim 4, wherein: When the electrostatic discharge semiconductor device is in operation, the thyristor structure consisting of the first injection region, the fourth well region, the first well region, the second well region and the third well region in the fourth well region and the second injection region in the second well region and the third well region is turned on to form a second current discharge path from the anode to the cathode.

6. The electrostatic discharge semiconductor device according to claim 5, further comprising: A buried layer having a second doping type is located in the upper part of the substrate and is in contact with the first well region to the third well region. The first injection region has the highest doping concentration among all regions having the first doping type, and the second injection region has the highest doping concentration among all regions having the second doping type. The doping concentration of the buried layer is second only to the larger one of the first injection region and the second injection region.

7. The electrostatic discharge semiconductor device according to claim 6, wherein: When the electrostatic discharge semiconductor device is working, the thyristor structure composed of the first injection region in the fourth well region, the fourth well region, the first well region, the buried layer, the second well region and the third well region, and the second injection region in the second well region and the third well region is turned on to form a third current discharge path from the anode to the cathode.

8. The electrostatic discharge semiconductor device according to claim 7, wherein: When the electrostatic discharge semiconductor device receives an electrostatic pulse, the first current discharge path is opened before the second current discharge path and the third current discharge path, and the second current discharge path is opened before the third current discharge path; and the current on the first current discharge path is smaller than the current on the second current discharge path, and the current on the second current discharge path is smaller than the current on the third current discharge path.

9. The electrostatic discharge semiconductor device according to claim 2, wherein: The doping concentration of the first injection region in the fifth well region and the sixth well region is greater than the doping concentration of the fifth well region and the sixth well region, the doping concentration of the fifth well region and the sixth well region is greater than the doping concentration of the first drift region and the second drift region, and the doping concentration of the first drift region and the second drift region is greater than the doping concentration of the first well region.

10. The electrostatic discharge semiconductor device according to claim 1, further comprising: A field oxide layer, distributed between the first injection region and the second injection region of each well region of the electrostatic discharge semiconductor device; A gate oxide layer is located above the fourth well region, and the field oxide layer between the fifth well region and the interval between the sixth well region and the fourth well region is in contact with the gate oxide layer; as well as A field plate layer covers a surface of the gate oxide layer and a portion of the surface of the field oxide layer that is in contact with the gate oxide layer, and the field plate layer is connected to the cathode.

11. The electrostatic discharge semiconductor device according to claim 1, wherein: The electrostatic discharge semiconductor device is a dual-finger structure.

12. The electrostatic discharge semiconductor device according to claim 1, wherein: The first doping type is P-type doping, and the second doping type is N-type doping.

13. A method for manufacturing an electrostatic discharge semiconductor device, comprising: forming a substrate having a first doping type and a buried layer having a second doping type located in an upper portion of the substrate; forming an epitaxial layer located above the substrate, wherein the epitaxial layer covers the buried layer; forming a first well region having a first doping type extending inward from a surface of the epitaxial layer and extending to a surface of the buried layer; forming a second well region and a third well region having a second doping type extending from the surface of the epitaxial layer to the inside and extending to the surface of the buried layer, wherein the second well region and the third well region are respectively located on both sides of the first well region and are separated from the first well region; forming a fourth well region having a second doping type extending from a surface of the first well region to the inside and separated from the buried layer; forming a first drift region and a second drift region having a first doping type extending from a surface of the first well region to the inside and separated from the buried layer, wherein the first drift region and the second drift region are symmetrically distributed on both sides of the fourth well region and separated from the fourth well region; forming a fifth well region and a sixth well region having a first doping type in the first drift region and the second drift region respectively; forming a plurality of spaced-apart field oxide layers located on and outside the epitaxial layer; and A plurality of first and second injection regions are formed at intervals with the field oxide layer and are located in each well region, wherein the first and second injection regions have a first doping type and a second doping type, respectively. The second injection region in the second well region and the third well region and the first injection region in the fifth well region and the sixth well region are all connected to the cathode, and the first injection region and the second injection region in the fourth well region are both connected to the anode.

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