Sensor protection for glass-free wafer level optical sensor package

Abstract

The invention relates to sensor protection for a glass-free wafer level optical sensor package. A glass-free wafer level optical sensor semiconductor package is provided. An example method of manufacturing a glass-free wafer level optical sensor package includes forming one or more dams on a wafer that at least partially surround one or more optical sensors; supporting the wafer on a carrier substrate via the one or more dams; a wafer level optical sensor integrated circuit for each of the one or more optical sensors is formed on a wafer by performing a through silicon via process on the wafer; forming an isolation layer on the wafer; and performing a passivation operation on the wafer; removing the wafer from the carrier substrate; and singulating each wafer level optical sensor integrated circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 507,345, filed on June 9, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Example embodiments of the present disclosure relate generally to optical sensor packaging, and more particularly, to apparatus and methods for protecting optical sensors in glass-free wafer-level packaging. Background Art

[0004] As new technologies requiring semiconductors are developed, the demand for semiconductors continues to increase. In addition, as electronic devices are developed, smaller and thinner form factors have become increasingly desirable and achievable. Semiconductor packages for electronic devices continue to shrink in size and are placed closer together. These semiconductor packages and other components of electronic devices have some parameters of their size determined by features other than the underlying semiconductor chip.

[0005] As technology enables semiconductor chips to become smaller in all dimensions, the limiting factor in semiconductor packaging is no longer the chip, but instead the components attached to the chip that form the semiconductor package. New systems, devices, and methods for semiconductor packaging are needed. The inventors have identified many areas of improvement in existing technologies and processes that are the subject of the embodiments described herein. Through hard work, ingenuity, and innovation, many of these deficiencies, challenges, and problems have been addressed by developing solutions included in the embodiments of the present disclosure, some examples of which are described in detail herein. Summary of the invention

[0006] Various embodiments described herein relate to semiconductor packaging, and more particularly, to glass-free wafer-level optical sensor packaging in a manner that protects the sensor.

[0007] According to some embodiments of the present disclosure, an example method is provided. The embodiments provided herein include a method of manufacturing a glass-free wafer-level optical sensor package, the method comprising: forming one or more dams on a wafer that at least partially surround one or more optical sensors; supporting the wafer on a carrier substrate via the one or more dams; forming a wafer-level optical sensor integrated circuit for each of the one or more optical sensors on the wafer by the following steps: performing a through-silicon via process on the wafer; forming an isolation layer on the wafer; and performing a passivation operation on the wafer; removing the wafer from the carrier substrate; and singulating each wafer-level optical sensor integrated circuit.

[0008] According to some embodiments, forming one or more dams on the wafer that at least partially surround the one or more optical sensors includes forming the one or more dams using at least one of patterned photolithography, polymer deposition, or photo-masked epoxy. According to certain embodiments, forming the one or more dams using at least one of patterned photolithography, polymer deposition, or photo-masked epoxy includes forming the one or more dams to a height between 30 microns and 60 microns above the surface of the wafer. The carrier substrate of the example embodiment includes a glass carrier substrate, wherein the glass carrier substrate is configured to enable testing of the one or more optical sensors using light received at the one or more optical sensors that passes through the glass carrier substrate.

[0009] According to some embodiments, forming the wafer-level optical sensor integrated circuits further comprises forming at least one redistribution layer on the wafer. In some embodiments, forming the wafer-level optical sensor integrated circuits from the wafer comprises performing a silicon thinning operation on the wafer before performing a through-silicon via process on the wafer. According to certain embodiments, forming the wafer-level optical sensor integrated circuits from the wafer further comprises attaching one or more solder balls to one or more signal pads of the wafer-level optical sensor integrated circuits. According to some embodiments, singulating each wafer-level optical sensor integrated circuit comprises separating a first wafer-level optical sensor integrated circuit from a second wafer-level optical sensor integrated circuit using at least one of a mechanical saw, a laser, or a die cut.

[0010] Embodiments provided herein include a glass-free wafer-level optical sensor package, comprising: a silicon wafer; an optical sensor disposed on the silicon wafer; a dam supported on the silicon wafer and at least partially surrounding the optical sensor; and a circuit system attached to the optical sensor formed using a through-silicon via process to the wafer. According to some embodiments, the glass-free wafer-level optical sensor package further includes an isolation layer on the wafer opposite the optical sensor; and a passivation layer on the isolation layer. According to some embodiments, the dam is formed on the silicon wafer by at least one of patterned photolithography, polymer deposition, or photomasked epoxy.

[0011] According to some embodiments, the dam is formed to a height between 30 microns and 60 microns above the surface of the wafer. Some embodiments of the glass-free wafer-level optical sensor package also include one or more redistribution layers located on the passivation layer. Some embodiments of the glass-free wafer-level optical sensor package have an overall thickness between approximately 120 microns and 180 microns. Some embodiments of the glass-free wafer-level optical sensor package have an overall thickness of less than 200 microns. Some embodiments of the glass-free wafer-level optical sensor package include a fan-in wafer-level package.

[0012] Embodiments provided herein include a system for producing a glass-free wafer-level optical sensor package, the system comprising: a glass carrier substrate; a silicon wafer supported on the glass carrier substrate; an optical sensor disposed on the silicon wafer and facing the glass carrier substrate; and a dam formed on the silicon wafer and supporting the silicon wafer above the glass carrier substrate, wherein the dam substantially surrounds the optical sensor. According to some embodiments, the system also includes a through-silicon via process for connecting the circuit system to the optical sensor. According to certain embodiments, the dam is formed using at least one of the following methods: patterned photolithography, polymer deposition, or photomasked epoxy. The height of the dam in some embodiments is between 30 microns and 60 microns above the surface of the silicon wafer.

[0013] The above overview is provided only to summarize some example embodiments to provide a basic understanding of some aspects of the present disclosure. Thus, it will be appreciated that the above embodiments are merely examples and should not be interpreted as narrowing the scope or spirit of the present disclosure in any way. It will also be appreciated that the scope of the present disclosure encompasses many potential embodiments in addition to those summarized here, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Having thus generally described certain example embodiments of the present disclosure, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0015] Figure 1 illustrates a top view of a semiconductor package according to an example embodiment of the present disclosure;

[0016] Figure 2 illustrates a cross-sectional view of a wafer-level optical sensor package with and without a glass layer according to an example embodiment of the present disclosure;

[0017] Figure 3 illustrates a cross-sectional view of a glass-free wafer-level optical sensor package in a shipping package according to an example embodiment of the present disclosure;

[0018] Figure 4 illustrates a cross-sectional view of a glass-free wafer-level optical sensor package including one or more dams to protect the optical sensor according to an example embodiment of the present disclosure;

[0019] Figure 5 illustrates a bottom view of a glass-free wafer level optical sensor package including one or more dams to protect the optical sensor according to an example embodiment of the present disclosure;

[0020] Figure 6 illustrates a cross-sectional view of a glass-free wafer level optical sensor package including one or more dams to protect the optical sensor in a shipping package according to an example embodiment of the present disclosure;

[0021] Figures 7A-7C illustrates a manufacturing process for a glass-free wafer-level optical sensor package including one or more dams to protect the optical sensor according to an example embodiment of the present disclosure;

[0022] Figures 8A-8C further illustrates a manufacturing process for a glass-free wafer-level optical sensor package including one or more dams to protect the optical sensor according to an example embodiment of the present disclosure; and

[0023] Fig. 9 is a flow chart of a method of manufacturing a glass-free wafer level optical sensor package including one or more dams to protect the optical sensor according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Some embodiments of the present disclosure will now be described more fully herein with reference to the accompanying drawings, in which some but not all embodiments of the present disclosure are shown. In fact, the various embodiments of the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure satisfies applicable legal requirements. Like reference numerals refer to like elements throughout.

[0025] As used herein, the term "comprising" means including but not limited to and should be interpreted in the manner in which it is commonly used in a patent context. The use of broader terms such as including, comprising, and having should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and consisting essentially of.

[0026] The phrases "in various embodiments," "in one embodiment," "according to one embodiment," "in some embodiments," etc. generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0027] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0028] If the specification states that a component or feature "may", "can", "might", "should", "will", "preferably", "likely", "usually", "optionally", "for example", "often" or "may" (or other such language) be included or have a feature, then the particular component or feature is not required to be included or have that feature. Such a component or feature may optionally be included in some embodiments or may be excluded.

[0029] The use of the term "circuitry" as used herein with respect to components of a system or device should be understood to include specific hardware configured to perform functions associated with a particular circuitry as described herein. The term "circuitry" should be broadly understood to include hardware, and in some embodiments, software for configuring the hardware. For example, in some embodiments, "circuitry" may include processing circuitry, communication circuitry, input / output circuitry, etc. In some embodiments, other elements may provide or supplement the functionality of a particular circuitry.

[0030] Various embodiments of the present disclosure are directed to improved systems, devices, and methods for semiconductor packaging, and in particular to improved packaging for optical sensors. Optical sensors require a line of sight (whether direct or indirect) to the optical sensor for sensing light of any frequency. Conventionally, packaging for optical sensors includes a glass layer above the optical sensor. However, as technology improves, as semiconductor chips have achieved extremely small overall sizes, including a glass layer significantly increases the overall thickness of the semiconductor package by up to 400%. The embodiments described herein provide a package such as a wafer-level optical sensor package that omits the glass layer while still providing protection for the optical sensor to reduce the possibility of damage during transportation. In addition, in addition to the significant reduction in overall thickness, omitting the glass layer also provides additional improvements to the wafer-level package. The lack of a glass layer improves optical performance because when light passes through any medium, there is a certain degree of loss in fidelity, and denser media such as glass potentially cause a certain degree of refraction, reflection, or absorption. The production of glass-free wafer-level packages further improves manufacturing efficiency because there is no opportunity for glass defects such as occlusion that would impair the functionality of the optical sensor. This results in less manufacturing waste, improved production efficiency, and reduced production costs. Additionally, the lack of a glass layer eliminates components in the wafer level package, thereby reducing the overall cost of materials used in the production of the wafer level package.

[0031] Semiconductor packages continue to shrink in size and are used in environments with increasing size constraints, such as in mobile phones, portable electronics, etc. Shrinking semiconductor packages requires that all components of the entire package be reduced in size, some of which have physical limitations in size due to one or more of existing manufacturing techniques, production costs, structural requirements, etc. An effective way to reduce the overall size of a semiconductor package is to eliminate components if it is possible to provide the functionality of the eliminated component in other ways.

[0032] Wafer-level packaging provides an efficient manufacturing process by which integrated circuits are manufactured and components of the integrated circuits are attached to the integrated circuits before the integrated circuits are singulated into individual circuits. Components such as the top and bottom layers of the package and solder bumps are attached to the integrated circuits by a process that does not require handling of individual integrated circuits. This process enables efficient and consistent package assembly of integrated circuits without requiring handling and alignment of individual integrated circuits in order to assemble components thereon. Fan-out wafer-level packaging uses similar technology; however, the integrated circuits are singulated before at least some of the components of the wafer-level package are attached to the integrated circuits. Fan-out wafer-level packaging enables certain portions of the entire semiconductor package to be larger than the integrated circuit itself (e.g., a die-cut wafer). The embodiments described herein can be used in wafer-level packaging and fan-out wafer-level packaging, with some modifications to the manufacturing process. However, the final product remains essentially unchanged.

[0033] Wafer-level packaging enables integrated circuits to be manufactured in a simplified and efficient process while producing integrated circuits with highly compact overall dimensions. Various types of sensors are produced as wafer-level packages; however, wafer-level optical sensors are unique in that they require visibility to the optical sensor's environment, either directly or indirectly. For example, wafer-level optical sensors can be used for light sensors (e.g., infrared), biometric authentication sensors, environmental sensing, and cameras. Each of these types of sensors requires the wafer-level optical sensor to have a line of sight to the target of the optical sensor, either directly or through an optical device. This requirement determines the packaging of wafer-level optical sensors within terminal devices (such as mobile phones).

[0034] Electronic devices such as mobile phones are very portable and are often carried by users all day. Therefore, the size of mobile phones or other portable electronic devices is crucial for the portability and use of such devices. These electronic devices have a very high level of functionality and require a robust design to withstand frequent use and often unintentional abuse and wear. Therefore, the structure of these electronic devices requires a certain degree of rigidity while maintaining a small form factor. The substantially rigid chassis of the electronic device carrying its hardware components (e.g., sensors, communication modules, speakers, cameras, screens, etc.) becomes an important component of the overall size, which limits the available space for the hardware components. Competing hardware components need to be sized to fit the small form factor, otherwise the components will be omitted, which will have an adverse effect on the functionality and desirability of the electronic device. Therefore, it is highly desirable to have a small form factor for wafer-level packaging of one or more sensors, and smaller components enable the form factor of the electronic device to become smaller and / or enable the electronic device to include more components to increase the functionality of the electronic device.

[0035] Wafer-level packaging has improved integrated circuits in many ways, including the relative thickness of integrated circuits. Wafer-level packaging enables integrated circuits to be manufactured in very compact form factors, less than 100 microns thick.

[0036] Wafer-level optical sensors generally include an optical glass layer located above the sensing components of the optical sensor to protect the optical sensor while also allowing light to reach the sensor. This glass becomes an integral component of the wafer-level optical sensor and often represents a significant portion of the thickness of the wafer-level optical sensor. Wafer-level optical sensors can be as thin as about 80 microns. Including an optical glass layer above the sensor can increase the overall thickness of the wafer-level optical sensor by more than 300 microns. Although the optical glass layer provides a certain degree of protection for the optical sensor, the substantial increase in thickness runs counter to the significant benefits of wafer-level packaging as a whole (i.e., overall package thickness). Devices such as mobile phones use a relatively thin form factor, and a large portion of the thickness of the device is dedicated to the front and rear layers and structural elements that need to be robust to accommodate frequent use. Therefore, the thickness of all components within such a device is critical to the overall package dimensions.

[0037] While it is possible to produce wafer-level optical sensors without an optical glass layer, the optical sensor of the wafer-level optical sensor is exposed and susceptible to damage. Embodiments of the present disclosure provide a process for producing a wafer-level optical sensor without an optical glass layer while increasing protection of the sensor outside of the sensor's line of sight.

[0038] Embodiments provided herein include glass-free wafer-level optical sensors that significantly reduce the overall thickness of the optical sensor, thereby improving packaging efficiency within electronic devices. In addition, embodiments provide a mechanism by which the optical sensor is protected to mitigate damage during production, transportation, and final assembly within the electronic device.

[0039] Wafer-level optical sensors without a glass layer have several benefits compared to wafer-level optical sensors that include an optical glass layer. The overall package thickness of a wafer-level optical sensor without an optical glass layer can reduce the overall thickness of the sensor package from approximately 300-400 microns to approximately 100-150 microns. This significant reduction in thickness is significant, especially from the perspective of packaging for compact form factor devices. The optical sensor performance of a wafer-level optical sensor without an optical glass is improved because the removal of the optical glass layer reduces refraction, reflection, and potential defects in the glass layer that adversely affect the performance of the optical sensor. The manufacturing cost of a wafer-level optical sensor without an optical glass layer is reduced in two ways. The lack of an optical glass layer reduces costs by reducing the materials required to produce a wafer-level optical sensor. In addition, the likelihood of defects in the manufactured wafer-level optical sensor is also reduced because the glass layer is a potential source of defects such as blemishes, scratches, and cracks.

[0040] Because the removal of the optical glass layer increases the fragility of the optical sensor, the embodiments provided herein provide a method of manufacturing a wafer-level optical sensor that includes a degree of protection for the optical sensor. The wafer-level optical sensor includes a dam that surrounds the optical sensor outside the line of sight of the optical sensor, rather than a glass layer above the optical sensor. This dam helps shield the optical sensor from damage.

[0041] Figure 1 A top view of an example embodiment of a semiconductor package according to one or more embodiments of the present disclosure is illustrated. The semiconductor package 100 may include a dielectric layer 110, a ground plane 120, a plurality of signal pads 130, and a plurality of solder balls (such as ground plane solder balls 122 and signal pad solder balls 132). The dielectric layer may be a polyimide (PI) and / or polybenzoxazole (PBO) material. Figure 1 Also depicted is section line AA, which represents the section line of various embodiments through which cross-sectional views of subsequent figures are taken.

[0042] It is readily appreciated that although only a few of the signal pads 130 and signal pad balls 132 are labeled with numbers, the semiconductor package 100 may include multiple of each, such as Figure 1. Each signal pad 130 may be separated from the ground plane 120 by one or more layers of dielectric material and / or portions of dielectric material (e.g., dielectric layer 110). When semiconductor package 100 is used in an electronic device, a plurality of solder balls (e.g., ground plane solder balls 122 and signal pad solder balls 132) may connect the semiconductor package to other circuitry of the electronic device. Although semiconductor package 100 is shown as a rectangle, it will be readily appreciated that semiconductor package 100 may take other shapes and / or dimensions, particularly as required by the electronic device. Figure 1 The semiconductor package 100 is an example of views of various semiconductor configurations as described herein, such that further figures will be described using views taken along section line AA, while the cross-sectional views may depict different embodiments of the semiconductor package 100 .

[0043] Figure 2 Two cross-sectional views of a semiconductor package in the form of an optical sensor wafer level package are shown, along the Figure 1 . The first optical sensor wafer-level package 200 is shown to include a semiconductor chip 210, which can be, for example, a silicon chip. The first optical sensor wafer-level package 200 also includes an optical sensor 215 extending across a portion of the semiconductor chip 210. Opposite the optical sensor 215 is a dielectric layer 235 along with a signal pad 230 and a signal pad solder ball 232. The first optical sensor wafer-level package 200 also includes a glass layer 205 covering and protecting the optical sensor 215.

[0044] Figure 2 Also illustrated is a cross-sectional view of a second optical sensor wafer-level package 220 including a semiconductor chip 210, a dielectric layer 235, a signal pad 230, and a signal pad solder ball 232. The second optical sensor wafer-level package 220 lacks the glass layer of the first optical sensor wafer-level package 210, which exposes the optical sensor 215 to sensor damage 225, such as by impact. The optical sensor 315 of the second optical wafer-level package 220 may be damaged due to various reasons from the production to the final assembly of the electrical device to which the package is installed. In addition, depending on the type of device and the exposure of the optical sensor to other elements, the optical sensor 315 may be damaged within the device. Although the second optical sensor wafer-level package 220 is susceptible to damage, the overall thickness 222 of the second optical sensor wafer-level package 220 is significantly less than the overall thickness 202 of the first optical sensor wafer-level package 200 including the glass layer 205.

[0045] Figure 3The second optical wafer level package 220 is illustrated packaged in a package 305 for shipping as a packaged semiconductor package 300. During the packaging operation of inserting the wafer level package into the package 305, damage may occur. Similarly, when the wafer level package is shipped, unpacked, and assembled, there is also the opportunity for sensor damage 225. An impact to the optical sensor 215 may compromise the integrity of the optical sensor and reduce or eliminate the functionality of the optical sensor 215.

[0046] As about Figure 2 As shown, while it is desirable to omit the glass layer from the wafer level package, doing so can make the optical sensor more susceptible to damage. The embodiments described herein mitigate the fragility to enable a glass-free wafer level optical sensor package to gain the benefits of a glass-free package while reducing the likelihood of damage to the optical sensor due to the fragility presented by the lack of a glass layer.

[0047] Embodiments described herein provide dams around some or all of the optical sensors of a glass-free wafer-level optical sensor package to protect the optical sensors by reducing the fragility of the wafer-level optical sensor package. Additionally, embodiments achieve the benefit of omitting a glass layer while retaining a degree of physical protection of the optical sensors.

[0048] Figure 4 An example embodiment of the present disclosure including a glass-free wafer-level optical sensor package 400 is illustrated, along the Figure 1 4 is a cross-sectional view of a semiconductor package shown in . Glass-free wafer-level optical sensor package 400 includes semiconductor chip 410, optical sensor 415, signal pad 430, and signal pad solder balls 432. Dams 440 on opposite sides of optical sensor 415 are also shown. These dams can form a continuous frame or border around optical sensor 415. However, in some embodiments, dams 440 can be discontinuous and extend only along a portion of one or more sides of optical sensor 415. According to embodiments where dams 440 are discontinuous, the dams can extend along a portion of each side of the optical sensor to maintain the protective function of the dams described herein.

[0049] Figure 4 The dam 440 shown in FIG. 4 protects the optical sensor 415 from impacts approaching the optical sensor from above and beside the optical sensor, which are the primary directions of destructive contact. The dam 440 also serves to prevent a portion of the package from contacting the optical sensor 415 by suspending the portion of the package above the optical sensor via the dam. For example, a portion of the package assembly contacting two dams will span the two dams and be suspended above the optical sensor 415 because the dams are at a higher height than the optical sensor 415.

[0050] Figure 5 Picture shows Figure 4 4 shows a top view of a glass-free wafer level optical sensor package 400, illustrating an example embodiment of how a dam 440 may surround an optical sensor 415. The dam 440 may be spaced apart from the optical sensor 415, or may be adjacent to the optical sensor 415. Adjacent to the dam may provide additional or better protection for the sensor; however, in some embodiments, such positioning may adversely affect the field of view of the optical sensor. Additionally, although Figure 5 The dam 440 has rounded corners, but embodiments may include sharp corners, particularly if the dam 440 abuts the optical sensor 415 .

[0051] Figure 6 The glass-free wafer-level optical sensor package 400 is illustrated within a package 450. As shown, dams 440 help prevent damaging impacts from reaching optical sensor 415. The outer edges of dams 440 are generally contacted first by any impact 425 so that optical sensor 415 itself is not contacted and therefore not damaged by impacts that might otherwise damage the optical sensor (such as in Figure 3 It should be readily appreciated that embodiments of the systems and devices described herein (particularly with respect to the shape and size of the dam formed around the optical sensor) may be configured in a variety of additional and alternative ways beyond those explicitly described herein.

[0052] Figures 7A-7C and Figures 8A-8C A manufacturing process for producing an embodiment of a glass-free wafer-level optical sensor package described herein is illustrated. Although the manufacturing method shown and described is not the only possible manufacturing method, the embodiments described herein may employ embodiments of the manufacturing process disclosed below.

[0053] Fig. 7A A silicon wafer 510 is illustrated including two optical sensors 515 and a dam 540 formed therebetween. The dam 540 can be deposited by various mechanisms depending on the material used for the dam. For example, the entire wafer 510 including the optical sensor 515 can be covered with a photocurable epoxy, wherein a mask is applied to shield areas that are not cured (e.g., non-dam areas including the optical sensor). Light can be exposed to the shielded photocurable epoxy so that the epoxy in the unshielded dam area is cured. The remaining uncured epoxy can be washed away so that only traces of the cured epoxy in the form of the dam 540 are exposed. Other materials known in the art can be used by processes such as dry etching materials, polymer deposition, photolithography, etc. Depending on the method of forming the dam 540, the top surface of the dam can be machined to obtain a substantially planar surface of the dam element.

[0054] Figure 7BThe next operation in the manufacturing process is illustrated, where the silicon wafer 510 is mounted to a carrier substrate 550 of a carrier handling material at the top surface of the dam 540. A cross section of the silicon wafer is shown, similar to Figure 1 The cross-sectional line AA of FIG. 5 is a cross-sectional line AA of FIG. 5. The carrier handling material in the exemplary embodiment is a glass material. Using a glass material for the carrier substrate 550 allows the optical sensor 515 to be tested by providing light to the sensor through the glass carrier substrate 550 during the manufacturing process. The silicon wafer is thinned to a final thickness by processes such as grinding and / or polishing, which may be approximately 80-150 microns, for example. The silicon wafer 510 is then ready for processing using TSV (through silicon vias). Figure 7C The TSV process is performed as shown in , and vertical electrical connections shown at 512 are created through the silicon wafer 510 to form interconnects. The TSV process eliminates wire bonding and enables higher density interconnects while retaining a small package size. This process forms a connection between the optical sensor 515 and the sensor pad 530. An isolation process is then performed using an isolation layer deposited on the surface of the silicon wafer 510 outside the sensor pad 530. At this stage, a redistribution layer (RDL) can be used to position the sensor pad at an appropriate location for the intended use.

[0055] Fig. 8A Deposition of a passivation layer 535 is illustrated above the wafer except for the location of the sensor pads 530. This creates a shield applied as a micro-coating so that the surface of the wafer-level optical sensor package is less susceptible to environmental impact or corrosion. Sensor solder balls 532 are applied to the sensor pads 530 to serve as connection points to the optical sensor 515.

[0056] Figure 8B The wafer level optical sensor package is shown separated from the carrier substrate and singulated to form individual glass-free wafer level optical sensor packages 500. The singulated glass-free wafer level optical sensor packages 500 are then packaged into packages 555.

[0057] As noted above, the use of glass carrier substrate 550 facilitates the manufacturing process because the optical sensors can be tested during the manufacturing process prior to singulating the sensor packages. This allows testing of the optical sensors to begin as early as after the TSV process to ensure functionality and proper connections are achieved before subsequent operations are performed. Sensor testing can be further performed prior to singulation, allowing the sensor packages to be functionally tested prior to final packaging to ensure that all sensor packages function properly when shipped to their destination for assembly into electronic devices.

[0058] The glass-free wafer-level optical sensor of the example embodiments provided herein provides substantial advantages over wafer-level optical sensors that employ glass layers. A substantial advantage of the glass-free wafer-level optical sensor is that the overall thickness of the sensor package is substantially reduced. The thickness of the wafer-level optical sensor itself can be about 80 microns to about 150 microns, while the glass layer can increase the overall thickness by 300 microns or more. Removing the glass layer enables the wafer-level optical sensor to have a total thickness of about 120 to 180 microns with or without solder balls, and more specifically a total thickness of about 130 to 160 microns. The thickness of the dam described herein can generally be in the range of about 30-60 microns. The reduction in sensor thickness by more than 300 microns is a major advancement in the production of wafer-level optical sensors, and achieving this with a glass-free wafer-level optical sensor that retains a degree of protection for the optical sensor is another major development using the embodiments described herein. This reduction in overall thickness can significantly reduce the amount of space such a sensor occupies within an electronic device, thereby providing greater design freedom for the electronic device and enabling a smaller, thinner overall device size, which has proven to be very desirable in portable electronic devices.

[0059] In addition to size advantages, embodiments of the glass-free wafer-level optical sensor packages described herein have superior optical performance relative to embodiments that employ a glass layer. When light travels through any medium, there is the possibility of refraction, reflection, and absorption into the medium. Light travels most efficiently in a vacuum, but it can also travel efficiently in an ambient air environment. Dense materials make efficient travel of light more challenging, causing materials such as glass to reflect, refract, and absorb light, thereby reducing the efficiency of light traveling through the glass and reaching the optical sensor. Therefore, omitting the glass layer is inherently more efficient than having a glass layer.

[0060] In addition to size and efficiency, improvements include reducing waste in sensor production. Glass manufacturing has become efficient, and the glass layers used in optical sensors are generally of very high quality. However, even high-quality glass layers may include obstructions, gaps, dirt, debris, or other issues that reduce the effectiveness of optical sensors. Optical sensors produced with defective glass are less accurate and may not meet minimum quality standards. Therefore, wafer-level optical sensor packages produced with defective glass may be rejected and become waste, reducing the efficiency of producing sensor packages.

[0061] In addition to these benefits, the absence of a glass layer also reduces the number of components in the sensor and saves on the cost of the sensor because no glass layer is required. This reduces the manufacturing cost of the optical sensor package, thereby improving the efficiency of manufacturing and production.

[0062] Fig. 9An example block diagram of an operational flow chart for manufacturing a glass-free wafer-level optical sensor package according to one or more embodiments of the present disclosure is illustrated. In various embodiments, one or more of the operations may be omitted or repeated. It will also be appreciated that other operations not described herein may also occur. According to the illustrated embodiment, one or more dams are formed at operation 610 to at least partially surround one or more optical sensors on a wafer. At 620, the wafer is supported on a carrier substrate via one or more dams. At 630, a wafer-level optical sensor integrated circuit is formed for each of the one or more optical sensors. This includes performing a through-silicon via process on the wafer at 640, forming an isolation layer on the wafer at 650, and performing a passivation operation on the wafer at 660. The wafer is removed from the carrier substrate at 670, and each wafer-level optical sensor is singulated at operation 680.

[0063] The operations and / or functions of the present disclosure have been described herein, such as in a flow chart or an accompanying drawing associated with the flow chart. Although the operations and / or functions are illustrated in a particular order, this should not be understood as requiring that such operations and / or functions be performed in the particular order shown or in a continuous order or that all the operations shown be performed to achieve the desired result. In some cases, it may be advantageous to employ operations and / or functions in an alternative order. In some cases, the actions set forth in the claims may be performed in a different order and still achieve the desired result. Therefore, although specific embodiments of the subject matter have been described, other embodiments are also within the scope of the following claims.

[0064] Although this specification includes many specific embodiments and implementation details, these should not be interpreted as limitations on any disclosed scope or claimable scope, but rather as descriptions of features specific to a specific disclosed embodiment. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments or in any suitable sub-combination, respectively. Moreover, although features may be described above as acting in certain combinations and even initially claimed, one or more features from the claimed combination may be deleted from the claimed combination in some cases, and the claimed combination may be directed to a sub-combination or a change in a sub-combination.

[0065] Although the detailed description has set forth some embodiments of the invention, the appended claims cover other embodiments of the invention according to various modifications and improvements that differ from the described embodiments.

[0066] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim, the claims are not intended to be interpreted under 35 USC §112, paragraph 6.

Claims

1. A method for manufacturing a glass-free wafer-level optical sensor package, comprising: forming one or more dams on the wafer at least partially surrounding the one or more optical sensors; supporting the wafer on a carrier substrate via the one or more dams; A wafer-level optical sensor integrated circuit is formed on a wafer for each of the one or more optical sensors by: performing a through silicon via process on the wafer; forming an isolation layer on the wafer; as well as performing a passivation operation on the wafer; removing the wafer from the carrier substrate; and Singulate each optical sensor IC at wafer level.

2. The method of claim 1 , wherein forming one or more dams on the wafer at least partially surrounding the one or more optical sensors comprises: The one or more dams are formed using at least one of patterned photolithography, polymer deposition, or photomasked epoxy.

3. The method of claim 2, wherein forming the one or more dams using at least one of patterned photolithography, polymer deposition, or photomasked epoxy comprises forming the one or more dams to a height between 30 microns and 60 microns above the surface of the wafer. 4 . The method of claim 1 , wherein the carrier substrate comprises a glass carrier substrate, wherein the glass carrier substrate is configured to enable testing of the one or more optical sensors using light received at the one or more optical sensors that passes through the glass carrier substrate.

5. The method of claim 1 , wherein forming a wafer-level optical sensor integrated circuit from a wafer further comprises: At least one redistribution layer is formed on the wafer.

6. The method of claim 1 , wherein forming a wafer-level optical sensor integrated circuit from a wafer further comprises: A silicon thinning operation is performed on the wafer before performing a through silicon via process on the wafer.

7. The method of claim 1 , wherein forming a wafer-level optical sensor integrated circuit from a wafer further comprises: One or more solder balls are attached to one or more signal pads of the wafer-level optical sensor integrated circuit.

8. The method of claim 1, wherein singulating each wafer-level optical sensor integrated circuit comprises separating a first wafer-level optical sensor integrated circuit from a second wafer-level optical sensor integrated circuit using at least one of a mechanical saw, a laser, or a die saw.

9. A glass-free wafer-level optical sensor package, comprising: Silicon wafer; Optical sensors, deployed on silicon wafers; a dam supported on the silicon wafer and at least partially surrounding the optical sensor; as well as The circuitry attached to the optical sensor is formed using a through silicon via process to the wafer.

10. The glass-free wafer-level optical sensor package of claim 9, further comprising: an isolation layer on the wafer opposite the optical sensor; as well as A passivation layer above the isolation layer.

11. The glass-free wafer level optical sensor package of claim 9, wherein the dams are formed on the silicon wafer by at least one of patterned photolithography, polymer deposition, or photomasked epoxy.

12. The glass-free wafer level optical sensor package of claim 11, wherein the dams are formed to a height between 30 microns and 60 microns above the surface of the wafer.

13. The glass-free wafer level optical sensor package of claim 9, further comprising one or more redistribution layers on the passivation layer.

14. The glass-free wafer level optical sensor package of claim 9, wherein an overall thickness of the glass-free wafer level optical sensor package is between approximately 120 microns and 180 microns.

15. The glass-free wafer level optical sensor package of claim 9, wherein the overall thickness of the wafer level optical sensor package is less than 200 microns.

16. The glass-free wafer level optical sensor package of claim 9, wherein the glass-free wafer level optical sensor package comprises a fan-in wafer level package.

17. A system for producing a glass-free wafer-level optical sensor package, comprising: glass carrier substrate; a silicon wafer supported on a glass carrier substrate; an optical sensor disposed on a silicon wafer and facing a glass carrier substrate; as well as A dam is formed on the silicon wafer and supports the silicon wafer above the glass carrier substrate, wherein the dam substantially surrounds the optical sensor.

18. The system of claim 17, further comprising: Through-silicon via (TSV) technology is used to connect the circuitry to the optical sensor.

19. The system of claim 17, wherein the dams are formed using at least one of: patterned photolithography, polymer deposition, or photomasked epoxy.

20. The system of claim 17, wherein the height of the dam is between 30 microns and 60 microns above the surface of the silicon wafer.

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