Light emitting diode with improved luminous efficiency and preparation method thereof

Abstract

The invention provides a light emitting diode with improved luminous efficiency and a preparation method thereof, and belongs to the technical field of photoelectron manufacturing. The light-emitting diode comprises a first semiconductor layer, an active layer and a second semiconductor layer which are stacked in sequence, the active layer comprises a plurality of stacked light-emitting stacked layers, each light-emitting stacked layer comprises a quantum barrier layer, a low-temperature insertion layer and a quantum well layer which are stacked in sequence, and the low-temperature insertion layer and the quantum well layer are InGaN layers. The light emitting efficiency of the light emitting diode can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode with improved luminous efficiency and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is an extremely influential new product in the optoelectronics industry. It has the characteristics of small size, long service life, rich colors and low energy consumption. It is widely used in lighting, display screens, signal lights, backlight sources, toys and other fields.

[0003] In the related art, a light emitting diode generally comprises: an n-type layer, an active layer and a p-type layer stacked in sequence. The active layer comprises a plurality of quantum well layers and quantum barrier layers stacked alternately, the quantum well layer is generally an InGaN layer, and the quantum barrier layer is generally a GaN layer.

[0004] The In concentration of the quantum well layer prepared in the related art is low, and the In concentration has a great influence on the luminous efficiency of the active layer. Therefore, in order to improve the luminous efficiency of the light-emitting diode, it is necessary to increase the In concentration of the quantum well layer. Summary of the invention

[0005] The embodiment of the present disclosure provides a light emitting diode with improved luminous efficiency and a method for manufacturing the same, which can improve the luminous efficiency of the light emitting diode. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes a first semiconductor layer, an active layer, and a second semiconductor layer stacked in sequence, the active layer includes a plurality of stacked light-emitting stacks, each of the light-emitting stacks includes a quantum barrier layer, a low-temperature insertion layer, and a quantum well layer stacked in sequence, and the low-temperature insertion layer and the quantum well layer are both InGaN layers.

[0007] Optionally, the In concentration of the low temperature insertion layer is 1.2×10 3 / cm 3 to 1.2×10 5 / cm 3 .

[0008] Optionally, the C content of the low temperature insertion layer is 3.6×10 16 / cm 3 Up to 6×10 16 / cm 3 .

[0009] Optionally, the low-temperature insertion layer includes a first low-temperature InGaN layer and a second low-temperature InGaN layer stacked in sequence, and a growth temperature of the first low-temperature InGaN layer is lower than a growth temperature of the second low-temperature InGaN layer.

[0010] On the other hand, the embodiment of the present disclosure also provides a method for preparing a light-emitting diode, the preparation method comprising: forming a first semiconductor layer; forming an active layer on the surface of the first semiconductor layer, the active layer comprising a plurality of stacked light-emitting stacks, each of the light-emitting stacks comprising a quantum barrier layer, a low-temperature insertion layer and a quantum well layer stacked in sequence, the low-temperature insertion layer and the quantum well layer are both InGaN layers, the growth temperature of the low-temperature insertion layer is lower than the growth temperature of the quantum well layer; forming a second semiconductor layer on the surface of the active layer.

[0011] Optionally, forming each of the light-emitting stacks comprises: introducing TMGa, TEGa, TMIn and NH 3 , using nitrogen and hydrogen as carrier gas, doping SiH 4 , control the pressure in the reaction chamber to be 150 torr to 250 torr, control the growth temperature to be 800°C to 910°C, grow a GaN layer to obtain the quantum barrier layer; control the growth temperature to be lowered to 700°C to 780°C, grow an InGaN layer to obtain the low-temperature insertion layer; control the growth temperature to be raised to 800°C to 910°C, grow an InGaN layer to obtain the quantum well layer.

[0012] Optionally, controlling the growth temperature to drop to 700°C to 780°C to grow an InGaN layer to obtain the low-temperature insertion layer includes: controlling the growth temperature to 700°C to 750°C to grow a first low-temperature InGaN layer; controlling the growth temperature to rise to 750°C to 780°C to grow a second low-temperature InGaN layer to obtain the low-temperature insertion layer, the growth temperature of the first low-temperature InGaN layer is lower than the growth temperature of the second low-temperature InGaN layer.

[0013] Optionally, the In concentration of the low temperature insertion layer is 1.2×10 3 / cm 3 to 1.2×10 5 / cm 3 The C content of the low temperature insertion layer is 3.6×10 16 / cm 3 Up to 6×10 16 / cm 3 .

[0014] Optionally, before forming the first semiconductor layer, the method includes placing a substrate in a reaction chamber, controlling the temperature in the reaction chamber to grow to 1000° C. to 1200° C., introducing hydrogen into the reaction chamber, and controlling the pressure in the reaction chamber to 150 torr to 250 torr for 5 to 10 minutes.

[0015] Optionally, forming the first semiconductor layer includes: introducing TMGa and NH 3 , using nitrogen and hydrogen as carrier gases, controlling the pressure in the reaction chamber to be 150 torr to 200 torr, and controlling the growth temperature to be 820° C. to 1140° C., to grow the first semiconductor layer.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] The active layer of the light-emitting diode provided in the embodiment of the present disclosure includes a plurality of stacked light-emitting stacks, wherein a low-temperature insertion layer is inserted between the quantum barrier layer and the quantum well layer in the light-emitting stack, and the low-temperature insertion layer is an InGaN layer. Since the lower the temperature is when the quantum well layer is grown, the easier it is for In to be incorporated into the quantum well layer, and the efficiency of incorporation becomes higher, the InGaN layer in the low-temperature insertion layer can obtain a high concentration of In content. At the same time, the lower the temperature is, the less likely the methyl group is to be detached, and it will be brought into GaN by Ga atoms, thereby increasing the C content in the low-temperature insertion layer. As the In concentration increases and the C content increases, the luminous efficiency of the light-emitting stack increases. Therefore, adding a low-temperature insertion layer between the quantum barrier layer and the quantum well layer can effectively improve the luminous efficiency of the active layer and enhance the luminous brightness of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure;

[0020] Figure 2 is a temperature variation diagram of a growing light-emitting stack provided by an embodiment of the present disclosure;

[0021] Figure 3 It is a structural schematic diagram of a light emitting diode provided in an embodiment of the present disclosure.

[0022] The descriptions of the marks in the figure are as follows:

[0023] 10. Substrate;

[0024] 20. a first semiconductor layer;

[0025] 30. Active layer;

[0026] 310, light-emitting stack; 311, quantum barrier layer;

[0027] 312, low temperature insertion layer; 3121, first low temperature InGaN layer; 3122, second low temperature InGaN layer;

[0028] 313, quantum well layer;

[0029] 40. A second semiconductor layer. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0031] Figure 1 FIG. 1 is a flow chart of a method for preparing a light emitting diode provided by an embodiment of the present disclosure. Figure 1 As shown, the preparation method comprises:

[0032] Step S11: forming a first semiconductor layer.

[0033] Step S12: forming an active layer on the surface of the first semiconductor layer.

[0034] The active layer includes a plurality of stacked light-emitting layers, each of which includes a quantum barrier layer, a low-temperature insertion layer and a quantum well layer stacked in sequence. Both the low-temperature insertion layer and the quantum well layer are InGaN layers, and the growth temperature of the low-temperature insertion layer is lower than the growth temperature of the quantum well layer.

[0035] Step S13: forming a second semiconductor layer on the surface of the active layer.

[0036] In the preparation method, a low-temperature insertion layer is inserted between the quantum barrier layer and the quantum well layer when preparing the active layer, and the low-temperature insertion layer is an InGaN layer. Since the lower the temperature is when growing the quantum well layer, the easier it is for In to be incorporated into the quantum well layer, and the efficiency of incorporation becomes higher, the InGaN layer in the low-temperature insertion layer can obtain a high concentration of In content. At the same time, the lower the temperature, the less likely the methyl group will be to detach, and it will be brought into GaN by Ga atoms, thereby increasing the C content in the low-temperature insertion layer. Since the greater the In concentration and the higher the C content, the higher the luminous efficiency of the light-emitting stack. Therefore, adding a low-temperature insertion layer between the quantum barrier layer and the quantum well layer can effectively improve the luminous efficiency of the active layer and enhance the luminous brightness of the light-emitting diode.

[0037] The step S11 may include: growing a first semiconductor layer on a substrate.

[0038] Exemplarily, the substrate is a sapphire substrate, a silicon substrate or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0039] As an example, in the embodiment of the present disclosure, the substrate is a sapphire substrate. The sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it can be a patterned sapphire substrate or a sapphire flat sheet substrate.

[0040] In step S11, the substrate can be placed in a reaction chamber, the temperature in the reaction chamber is controlled to grow to 1000° C. to 1200° C., hydrogen is introduced into the reaction chamber, and the pressure in the reaction chamber is controlled to be 150 torr to 250 torr for 5 to 10 minutes. This process can bake and clean the substrate surface and the graphite disk.

[0041] In step S11, the sapphire substrate may be pre-treated by placing the sapphire substrate in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate is baked for 15 minutes.

[0042] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0043] It should be noted that the first semiconductor layer may also be grown on an AlN layer or a composite substrate, which is not limited in the embodiments of the present disclosure.

[0044] For example, when the first semiconductor layer is grown on the AlN layer, the thickness of the AlN layer can be controlled to be 160 angstroms to 220 angstroms.

[0045] Exemplarily, the AlN layer is deposited by magnetron sputtering using a physical vapor deposition (PVD) device.

[0046] The growth temperature in the PVD equipment is 400°C to 800°C, the sputtering power is 3000W to 5000W, the pressure is 1mtorr to 20mtorr, and the AlN layer deposition thickness is 10nm to 50nm.

[0047] In the embodiment of the present disclosure, before growing the first semiconductor layer, the process may include: sequentially growing a nucleation layer and a non-doped GaN layer on the substrate.

[0048] Specifically, the method may include: first, placing the substrate coated with the buffer layer in an MOCVD system to grow a nucleation layer. The temperature of the MOCVD reaction chamber is 1030°C to 1100°C, the pressure of the reaction chamber is controlled at 150 torr to 500 torr, and the thickness of the nucleation layer is 0.3 μm to 2 μm under the mixed atmosphere of nitrogen, hydrogen and ammonia. Then, a non-doped GaN layer is grown on the nucleation layer.

[0049] In the embodiment of the present disclosure, an undoped GaN layer is also grown between the nucleation layer and the n-type layer. Compared with the substrate, since the crystal structure of the undoped GaN layer is similar to that of the n-type layer, the crystal quality of the subsequent epitaxial layer can be improved by providing the undoped GaN layer as a transition layer.

[0050] The thickness of the non-doped GaN layer is 0.5 μm to 3 μm. For example, the thickness of the non-doped GaN layer is 2 μm.

[0051] Specifically, the undoped GaN buffer recovery layer is grown by MOCVD. In an MOCVD system, the temperature is adjusted to 1000° C. to 1150° C., and the growth pressure is 100 Torr to 500 Torr, and a non-doped GaN layer with a thickness of 0.5 μm to 3 μm is grown.

[0052] The step S11 of forming the first semiconductor layer may include: introducing TMGa and NH 3 , using nitrogen and hydrogen as carrier gases, controlling the pressure in the reaction chamber to be 150 torr to 200 torr, controlling the growth temperature to be 820° C. to 1140° C., and growing the first semiconductor layer.

[0053] Alternatively, the first semiconductor layer may be an n-type layer.

[0054] For example, the n-type layer may be an n-type GaN layer, the thickness of the n-type layer is 4 μm to 6 μm, and the dopant of the n-type layer is silane.

[0055] Specifically, in the MOCVD system, the temperature was adjusted to 1000°C and the growth pressure was 200 Torr. An n-type doped GaN layer with a thickness of 5 μm was grown. The concentration of Si doped in the n-type GaN layer was 1×10 18 cm -3 Up to 1×10 19 cm -3 .

[0056] For example, the flow rate of TMGa in the n-type layer may be controlled to be between 700 sccm and 2000 sccm.

[0057] Step S12 may include the following steps:

[0058] First, TMGa, TEGa, TMIn and NH 3 , using nitrogen and hydrogen as carrier gas, doping SiH 4 , control the pressure in the reaction chamber to be 150 torr to 250 torr, control the growth temperature to be 800° C. to 910° C., grow a GaN layer, and obtain a quantum barrier layer.

[0059] Specifically, it may include: introducing TMGa, TEGa, TMIn and NH into the reaction chamber 3 , using nitrogen and hydrogen as carrier gas, doping SiH 4 , control the pressure in the reaction chamber to 200torr, control the growth temperature to 850℃, grow the GaN layer, and obtain the quantum barrier layer

[0060] Exemplarily, the flow rate of TEGa may be 260 sccm to 330 sccm, and the flow rate of TMIn may be 800 sccm to 3000 sccm.

[0061] Then, the growth temperature is controlled to be lowered to 700° C. to 780° C., and an InGaN layer is grown to obtain a low-temperature insertion layer.

[0062] In the embodiment of the present disclosure, the low-temperature insertion layer may include a first low-temperature InGaN layer and a second low-temperature InGaN layer grown sequentially.

[0063] The growth temperature of the first low-temperature InGaN layer is lower than the growth temperature of the second low-temperature InGaN layer.

[0064] Optionally, growing the low-temperature insertion layer may specifically include:

[0065] In the first step, the growth temperature is controlled to be 700° C. to 750° C. to grow a first low-temperature InGaN layer.

[0066] Exemplarily, the growth temperature is controlled to be 740° C. to grow the first low-temperature InGaN layer.

[0067] Figure 2 is a temperature variation diagram of a growing light-emitting stack provided by an embodiment of the present disclosure. Figure 2 As shown, A in the figure shows the stage of growing the quantum barrier layer, B in the figure shows the stage of growing the first low-temperature InGaN layer, C in the figure shows the stage of growing the second low-temperature InGaN layer, and D in the figure shows the stage of growing the quantum well layer.

[0068] like Figure 2 As shown, from the completion of the quantum barrier layer growth to the growth of the first low-temperature InGaN layer, the temperature first drops to below 800°C, and then gradually decreases. When the temperature drops to the lowest (740°C), the first low-temperature InGaN layer begins to grow.

[0069] This way of controlling temperature changes can have a positive effect on improving the growth quality of the quantum barrier layer and quantum well layer interface, reducing non-radiative recombination centers. At the same time, it is also particularly important for the aggregation of In concentration and C content, so that the first low-temperature InGaN layer can obtain a high concentration of In and C content.

[0070] In the second step, the growth temperature is controlled to rise to 750° C. to 780° C. to grow a second low-temperature InGaN layer to obtain a low-temperature insertion layer.

[0071] Exemplarily, the growth temperature is controlled to rise to 770° C. to grow the second low-temperature InGaN layer.

[0072] like Figure 2 As shown, after the first low-temperature InGaN layer is grown, the growth temperature is controlled to rise at a uniform rate, and when the growth temperature reaches 770° C., the second low-temperature InGaN layer begins to grow.

[0073] In the above implementation, when growing the low-temperature insertion layer, the temperature is first lowered to 740°C to reach the minimum to grow the first low-temperature InGaN layer. The purpose is to have a positive effect on improving the growth quality of the quantum barrier layer and the quantum well layer interface and reduce non-radiative recombination centers.

[0074] Subsequently, the growth temperature is controlled to rise back to 770°C to grow the second low-temperature InGaN layer, with the aim of growing the InGaN layer at a lower growth temperature. As the temperature is lower, In is more easily incorporated into the quantum well, making the efficiency of In incorporation higher, so a high concentration of In can be obtained; at the same time, the lower the temperature, the less likely the methyl group will be detached, and it will be brought into GaN by Ga atoms, resulting in an increase in the C content. As a result, a higher concentration of In and C content is obtained in the local area of ​​the quantum well layer. Since the In content of the InGaN material has a greater influence on the luminous efficiency, a higher In concentration in the local area is obtained, which can restrain electrons from escaping and improve the luminous efficiency. At the same time, increasing the C content in the local area can reduce the carrier lifetime, increase the ability to bind electrons, and have a positive effect on In formation, which can also achieve the purpose of improving the luminous efficiency, thereby enhancing the luminous brightness of the light-emitting diode.

[0075] Optionally, the In concentration of the low temperature insertion layer is 1.2×10 3 / cm 3 to 1.2×10 5 / cm 3 For example, the In concentration of the low temperature insertion layer is 1.2×10 3 / cm 3 .

[0076] Optionally, the C content of the low temperature insertion layer is 3.6×10 16 / cm3 to 6×10 16 / cm 3 Exemplarily, the C content of the low-temperature insertion layer is 3.6×10 16 / cm 3 .

[0077] Next, control the growth temperature to rise to 800 °C to 910 °C, grow the InGaN layer, and obtain the quantum well layer.

[0078] As Figure 2 shown, after growing the second low-temperature InGaN layer, control the growth temperature to rise uniformly. When the growth temperature is not lower than 800 °C, start growing the quantum well layer.

[0079] Exemplarily, the quantum well layer can be an InGaN layer.

[0080] Exemplarily, the thickness of the light-emitting stack can be 0.3 μm to 0.4 μm.

[0081] Step S13 may include forming a second semiconductor layer on the surface of the active layer.

[0082] Exemplarily, the first semiconductor layer can be a p-type layer.

[0083] Among them, the p-type layer includes a low-temperature p-type AlGaN layer, a p-type electron blocking layer, a high-temperature p-type GaN layer, and a p-type contact layer that are sequentially stacked on the active layer.

[0084] Exemplarily, the p-type electron blocking layer can be a p-type Al k Ga 1-k N(0.1 < k < 0.5) layer, and the thickness of the p-type electron blocking layer can be 10 nm to 100 nm.

[0085] In the embodiments of the present disclosure, both the low-temperature p-type AlGaN layer and the high-temperature p-type GaN layer are doped with Mg.

[0086] Exemplarily, the low-temperature p-type AlGaN layer includes an Al w Ga 1-w N layer, 0.1 < w < 0.3.

[0087] The Mg doping concentration of the low-temperature p-type AlGaN layer is 5×10 20 cm -3 to 1×10 21 cm -3 , and the Mg doping concentration of the high-temperature p-type GaN layer is 1×10 18 cm -3 to 1×10 20 cm -3 .

[0088] Among them, the thickness of the low-temperature p-type AlGaN layer can be 10 nm to 100 nm. For example, the thickness of the low-temperature p-type AlGaN layer can be 80 nm.

[0089] Among them, the thickness of the high-temperature p-type GaN layer can be 10 nm to 100 nm. For example, the thickness of the low-high-temperature p-type GaN layer can be 50 nm.

[0090] When growing the low-temperature p-type AlGaN layer, adjust the growth temperature to 700 °C to 800 °C, and grow the low-temperature p-type AlGaN layer under the growth pressure of 200 Torr to 500 Torr, with a thickness of 10 nm to 100 nm.

[0091] When growing the p-type electron blocking layer, adjust the growth temperature to 800 °C to 1000 °C, and under the growth pressure of 100 Torr to 300 Torr, the p-type electron blocking layer can be an Al k Ga 1-k N layer, where 0.2 < k < 0.5 and the thickness is 10 nm to 100 nm.

[0092] When growing the high-temperature p-type GaN layer, control the growth pressure in the environment of 200 Torr to 600 Torr, the growth temperature is 800 °C to 1000 °C, and grow the p-type GaN layer with a thickness of 10 nm to 100 nm.

[0093] When growing the p-type contact layer, control the growth temperature to 850 °C to 1000 °C, control the growth pressure to 100 Torr to 300 Torr, and grow the p-type contact layer with a thickness of 1 nm to 30 nm.

[0094] Among them, the Mg doping concentration in the p-type contact layer is 1×10 20 to 1×10 21 cm -3 .

[0095] After step S13, the preparation method may further include: annealing the light-emitting diode.

[0096] After the epitaxial growth is completed, lower the temperature of the reaction chamber to 650 °C to 850 °C, and perform annealing treatment in an N 2 atmosphere for 5 min to 15 min, and then gradually lower it to room temperature. Subsequently, the chip is made through subsequent processing technologies such as cleaning, deposition, photolithography, and etching.

[0097] In specific implementation, the embodiments of the present disclosure may use high-purity H 2 or / and N 2 as the carrier gas, use TEGa or TMGa as the Ga source, TmIn as the In source, SiH 4As n-type dopant, TMAl as aluminum source, ammonia as N source, Cp 2 Mg acts as a p-type dopant.

[0098] Figure 3 Schematic diagram of the structure of a light emitting diode provided by an embodiment of the present disclosure. Figure 3 As shown, the light-emitting diode includes a first semiconductor layer 20, an active layer 30 and a second semiconductor layer 40 stacked in sequence, the active layer 30 includes a plurality of stacked light-emitting stacks 310, each light-emitting stack 310 includes a quantum barrier layer 311, a low-temperature insertion layer 312 and a quantum well layer 313 stacked in sequence, and the low-temperature insertion layer 312 and the quantum well layer 313 are both InGaN layers.

[0099] The active layer 30 of the light-emitting diode provided in the embodiment of the present disclosure includes a plurality of stacked light-emitting stacks 310, wherein a low-temperature insertion layer 312 is inserted between the quantum barrier layer 311 and the quantum well layer 313 in the light-emitting stack 310, and the low-temperature insertion layer 312 is an InGaN layer. Since the lower the temperature is when the quantum well layer 313 is grown, the easier it is for In to be incorporated into the quantum well layer 313, and the efficiency of incorporation becomes higher, the InGaN layer in the low-temperature insertion layer 312 can obtain a high concentration of In content. At the same time, the lower the temperature is, the less likely the methyl group is to be detached, and it will be brought into GaN by Ga atoms, so that the C content in the low-temperature insertion layer 312 is also increased. Since the greater the In concentration and the higher the C content, the higher the luminous efficiency of the light-emitting stack 310. Therefore, adding a low-temperature insertion layer 312 between the quantum barrier layer 311 and the quantum well layer 313 can effectively improve the luminous efficiency of the active layer 30 and enhance the luminous brightness of the light-emitting diode.

[0100] Optionally, the low-temperature insertion layer 312 includes a first low-temperature InGaN layer 3121 and a second low-temperature InGaN layer 3122 which are sequentially stacked.

[0101] The growth temperature of the first low-temperature InGaN layer 3121 is lower than the growth temperature of the second low-temperature InGaN layer 3122 .

[0102] Exemplarily, the growth temperature of the first low-temperature InGaN layer 3121 is 7405° C., and the growth temperature of the second low-temperature InGaN layer 3122 is 770° C.

[0103] In the process from the completion of the growth of the quantum barrier layer 311 to the growth of the first low-temperature InGaN layer 3121 , when the growth temperature is reduced to 740° C., the growth of the first low-temperature InGaN layer 3121 begins.

[0104] Such a method of controlling temperature change can have a positive effect on improving the interface growth quality of the quantum barrier layer 311 and the quantum well layer 313, and reduce non-radiative recombination centers. At the same time, it is also particularly important for the aggregation of In concentration and C content, so that the first low-temperature InGaN layer 3121 can obtain a high concentration of In and C content.

[0105] In the implementation of the present disclosure, after the first low-temperature InGaN layer 3121 is grown, the growth temperature is controlled to grow to 770° C., and then the second low-temperature InGaN layer 3122 is started to grow.

[0106] In the above implementation, when growing the low-temperature insertion layer 312, the temperature is first reduced to 740°C to reach the minimum to grow the first low-temperature InGaN layer 3121, with the purpose of having a positive effect on improving the interface growth quality of the quantum barrier layer 311 and the quantum well layer 313 and reducing non-radiative recombination centers.

[0107] Subsequently, the growth temperature is controlled to rise back to 770°C to grow the second low-temperature InGaN layer 3122, with the purpose of growing the InGaN layer at a lower growth temperature. Since the lower the temperature, the easier it is for In to be incorporated into the quantum well, the higher the efficiency of In incorporation, so a high concentration of In can be obtained; at the same time, the lower the temperature, the less likely the methyl group will be detached, and it will be brought into GaN by Ga atoms, resulting in an increase in the C content. As a result, a higher concentration of In and C content is obtained in the local area of ​​the quantum well layer 313. Since the In content of the InGaN material has a greater influence on the luminous efficiency, a higher In concentration in the local area is obtained, which can bind electrons to escape and improve the luminous efficiency. At the same time, increasing the C content in the local area can reduce the carrier lifetime, increase the ability to bind electrons, and have a positive effect on In formation, which can also achieve the purpose of improving the luminous efficiency, thereby enhancing the luminous brightness of the light-emitting diode.

[0108] Optionally, the In concentration of the low temperature insertion layer 312 is 1.2×10 3 / cm 3 to 1.2×10 5 / cm 3 For example, the In concentration of the low temperature insertion layer 312 is 1.2×10 3 / cm 3 .

[0109] Optionally, the C content of the low temperature insertion layer 312 is 3.6×10 16 / cm 3 Up to 6×10 16 / cm 3 For example, the C content of the low temperature insertion layer 312 is 3.6×10 16 / cm 3 .

[0110] Optionally, the quantum barrier layer 311 may be a GaN layer, and the quantum well layer 313 may be an InGaN layer.

[0111] Optionally, as Figure 3 shown, the light-emitting diode may further include a substrate 10, which is a substrate for carrying an epitaxial layer. The first semiconductor layer 20, the active layer 30, and the second semiconductor layer 40 are sequentially stacked on the substrate 10.

[0112] Exemplarily, the substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate. The substrate may be a flat substrate or a patterned substrate.

[0113] As an example, in the embodiments of the present disclosure, the substrate is a sapphire substrate. The sapphire substrate is a commonly used substrate with mature technology and low cost. Specifically, it may be a patterned sapphire substrate or a sapphire flat substrate.

[0114] In the embodiments of the present disclosure, the first semiconductor layer 20 may be an n-type layer, and the second semiconductor layer 40 may be a p-type layer.

[0115] Optionally, the n-type layer may be an n-type GaN layer. The thickness of the n-type layer is 2 μm to 6 μm.

[0116] Among them, the dopant of the n-type layer is silane, and the concentration of doped silane may be 5×10 18 cm -3 to 5×10 19 cm -3 .

[0117] Optionally, the p-type layer further includes a low-temperature p-type AlGaN layer, a p-type electron blocking layer, a high-temperature p-type GaN layer, and a p-type contact layer. The low-temperature p-type AlGaN layer, the p-type electron blocking layer, the high-temperature p-type GaN layer, and the p-type contact layer are sequentially stacked on the active layer 30.

[0118] Exemplarily, the p-type electron blocking layer may be a p-type Al k Ga 1-k N layer, where 0.1 < k < 0.5, and the thickness of the p-type electron blocking layer may be 10 nm to 100 nm.

[0119] If the thickness of the p-type electron blocking layer is too thin, the blocking effect on electrons will be reduced. If the thickness of the p-type electron blocking layer is too thick, the absorption of light by the p-type electron blocking layer will increase, resulting in a decrease in the light emission efficiency of the LED.

[0120] In the embodiments of the present disclosure, both the low-temperature p-type AlGaN layer and the high-temperature p-type GaN layer are Mg-doped.

[0121] The Mg doping concentration of the low-temperature p-type AlGaN layer is 5×10 20 cm-3 Up to 1×10 21 cm -3 The Mg doping concentration of the high temperature p-type GaN layer is 1×10 18 cm -3 Up to 1×10 20 cm -3 .

[0122] The thickness of the low-temperature p-type AlGaN layer may be 10 nm to 100 nm. For example, the thickness of the low-temperature p-type AlGaN layer may be 80 nm.

[0123] The thickness of the high temperature p-type GaN layer may be 10 nm to 100 nm. For example, the thickness of the high temperature p-type GaN layer may be 50 nm.

[0124] Optionally, the thickness of the p-type contact layer may be 1 nm to 30 nm. As an example, in the embodiment of the present disclosure, the thickness of the p-type contact layer is 20 nm.

[0125] The p-type contact layer is a p-type GaN layer, and the Mg doping concentration of the p-type GaN layer is 1×10 20 cm -3 Up to 1×10 21 cm -3 .

[0126] If the thickness of the p-type contact layer is too thin, it will affect the current contact between the epitaxial layer and the electrode. If the thickness of the p-type contact layer is too thick, the p-type contact layer will increase its absorption of light, thereby reducing the luminous efficiency of the LED.

[0127] Alternatively, if Figure 3 As shown, a buffer layer, a nucleation layer and a non-doped GaN layer are further included between the substrate 10 and the n-type layer. The buffer layer, the nucleation layer and the non-doped GaN layer are sequentially stacked on the substrate 10 .

[0128] In the embodiment of the present disclosure, the buffer layer may be an AlN layer, and the AlN layer is an AlN layer grown at a temperature between 400° C. and 800° C.

[0129] The thickness of the buffer layer may be 10 nm to 50 nm. For example, the thickness of the buffer layer may be 20 nm.

[0130] By setting the thickness of the buffer layer within the above range, it is possible to avoid the buffer layer being too thin, thereby reducing the crystal quality of the epitaxial layer grown on the thinner buffer layer; it is also possible to avoid the buffer layer being too thick, thereby increasing the buffer layer's absorption of light, thereby reducing the luminous efficiency of the light-emitting diode.

[0131] Alternatively, the nucleation layer may be a three-dimensional GaN nucleation layer.

[0132] Exemplarily, the three-dimensional GaN nucleation layer may be grown to a thickness of 0.3 μm to 0.5 μm.

[0133] In the embodiment of the present disclosure, an undoped GaN layer is also grown between the three-dimensional GaN nucleation layer and the n-type layer. Compared with the substrate, since the crystal structure of the undoped GaN layer is similar to that of the n-type layer, the crystal quality of the subsequent epitaxial layer can be improved by providing the undoped GaN layer as a transition layer.

[0134] The thickness of the non-doped GaN layer is 0.5 μm to 3 μm. For example, the thickness of the non-doped GaN layer is 2 μm.

[0135] By setting the thickness of the undoped GaN layer within the above range, it is possible to avoid the undoped GaN layer being too thin, which would not play a transition role and reduce the crystal quality of the grown epitaxial layer; it is also possible to avoid the undoped GaN layer being too thick, which would increase the absorption of light by the undoped GaN layer and thus reduce the luminous efficiency of the light-emitting diode.

[0136] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises a first semiconductor layer (20), an active layer (30) and a second semiconductor layer (40) stacked in sequence, the active layer (30) comprising a plurality of stacked light emitting stacks (310), each of the light emitting stacks (310) comprising a quantum barrier layer (311), a low temperature insertion layer (312) and a quantum well layer (313) stacked in sequence, and both the low temperature insertion layer (312) and the quantum well layer (313) are InGaN layers.

2. The light emitting diode according to claim 1, characterized in that: The In concentration of the low temperature insertion layer (312) is 1.2×10 3 / cm 3 to 1.2×10 5 / cm 3 .

3. The light emitting diode according to claim 1, characterized in that: The C content of the low temperature insertion layer (312) is 3.6×10 16 / cm 3 Up to 6×10 16 / cm 3 .

4. The light emitting diode according to any one of claims 1 to 3, characterized in that: The low-temperature insertion layer (312) comprises a first low-temperature InGaN layer (3121) and a second low-temperature InGaN layer (3122) stacked in sequence, and the growth temperature of the first low-temperature InGaN layer (3121) is lower than the growth temperature of the second low-temperature InGaN layer (3122).

5. A method for preparing a light emitting diode, characterized in that: The preparation method comprises: forming a first semiconductor layer; An active layer is formed on the surface of the first semiconductor layer, wherein the active layer includes a plurality of stacked light-emitting stacks, each of which includes a quantum barrier layer, a low-temperature insertion layer and a quantum well layer stacked in sequence, wherein both the low-temperature insertion layer and the quantum well layer are InGaN layers, and the growth temperature of the low-temperature insertion layer is lower than the growth temperature of the quantum well layer; A second semiconductor layer is formed on a surface of the active layer.

6. The preparation method according to claim 5, characterized in that: Forming each of the light-emitting stacks comprises: Introduce TMGa, TEGa, TMIn and NH3 into the reaction chamber, use nitrogen and hydrogen as carrier gas, dope SiH4, control the pressure in the reaction chamber to be 150 torr to 250 torr, control the growth temperature to be 800° C. to 910° C., grow a GaN layer, and obtain the quantum barrier layer; Controlling the growth temperature to drop to 700° C. to 780° C., growing an InGaN layer, and obtaining the low-temperature insertion layer; The growth temperature is controlled to rise to 800° C. to 910° C. to grow an InGaN layer to obtain the quantum well layer.

7. The preparation method according to claim 6, characterized in that: Controlling the growth temperature to decrease to 700° C. to 780° C., growing an InGaN layer, and obtaining the low-temperature insertion layer comprises: Controlling the growth temperature to be 700° C. to 750° C. to grow a first low-temperature InGaN layer (3121); The growth temperature is controlled to rise to 750°C to 780°C, and a second low-temperature InGaN layer (3122) is grown to obtain the low-temperature insertion layer. The growth temperature of the first low-temperature InGaN layer (3121) is lower than the growth temperature of the second low-temperature InGaN layer (3122).

8. The preparation method according to any one of claims 5 to 7, characterized in that: The In concentration of the low temperature insertion layer is 1.2×10 3 / cm 3 to 1.2×10 5 / cm 3 ; The C content of the low temperature insertion layer is 3.6×10 16 / cm 3 Up to 6×10 16 / cm 3 .

9. The preparation method according to any one of claims 5 to 7, characterized in that: Before forming the first semiconductor layer, the method includes: The substrate is placed in a reaction chamber, the temperature in the reaction chamber is controlled to grow to 1000° C. to 1200° C., hydrogen is introduced into the reaction chamber, and the pressure in the reaction chamber is controlled to be 150 torr to 250 torr for 5 to 10 minutes.

10. The preparation method according to any one of claims 5 to 7, characterized in that: Forming the first semiconductor layer includes: TMGa and NH3 are introduced into the reaction chamber, nitrogen and hydrogen are used as carrier gases, the pressure in the reaction chamber is controlled to be 150 torr to 200 torr, and the growth temperature is controlled to be 820° C. to 1140° C. to grow the first semiconductor layer.

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