Trigger, filter, analog-to-digital converter, motor control system and vehicle

Abstract

The invention provides a trigger, a filter, an analog-to-digital converter, a motor control system and a vehicle, the trigger comprises a first selection circuit and a second selection circuit, the first selection circuit receives a plurality of first peripheral trigger signals and selects one from the plurality of first peripheral trigger signals for output, and the second selection circuit receives at least one third peripheral trigger signal and selects one from the plurality of first peripheral trigger signals for output. The trigger signals output by the first selection circuit are further received, one of the received trigger signals is selected as the enable signal to be output, due to the fact that the two selection circuits receive the peripheral trigger signals, more peripheral trigger signals can be received, the types of the received peripheral trigger signals are increased, and the problem that the peripheral trigger signals are limited and inflexible is solved.

Description

Technical Field

[0001] The present application relates to the field of digital signal processing, and in particular to a trigger, a filter, an analog-to-digital converter, a motor control system and a vehicle. Background Art

[0002] Digital signal processing technology continues to develop and progress, but many things are essentially analog signals. Digital circuits cannot directly process these analog signals and need to convert them into digital signals that are discrete in time and amplitude.

[0003] Currently, analog signals can be converted into digital signals through an analog-to-digital converter, but the analog-to-digital converter needs to be triggered by a trigger signal to work.

[0004] Since the trigger can only be connected to a few fixed peripheral modules, it can only receive a few fixed peripheral trigger signals and cannot obtain peripheral trigger signals from other modules, resulting in limited and inflexible trigger signals. Summary of the invention

[0005] The present application provides a trigger, a filter, an analog-to-digital converter, a motor control system and a vehicle, so as to solve the problem that the trigger can only receive fixed peripheral trigger signals, resulting in limited and inflexible trigger signals.

[0006] Some embodiments of the present application provide a trigger, the trigger comprising:

[0007] A first selection circuit, wherein an input end of the first selection circuit receives a plurality of first peripheral trigger signals, and an output end of the first selection circuit outputs a second peripheral trigger signal; the second peripheral trigger signal is one of the plurality of first peripheral trigger signals;

[0008] The second selection circuit has a first input end connected to the output end of the first selection circuit, a second input end of the second selection circuit receives at least one third peripheral trigger signal, and outputs an enable signal from the output end.

[0009] Some embodiments of the present application provide a filter, including: a third selection circuit and at least one first filtering circuit,

[0010] The input end of the third selection circuit is used to receive the digital signal, and the input end of each first filter circuit is connected to the output end of the third selection circuit;

[0011] The first filter circuit is used to filter the received signal; the third selection circuit is used to adjust the number of the first filter circuits involved in the filtering.

[0012] Some embodiments of the present application provide a filter, the filter comprising:

[0013] A first filtering circuit, wherein an input end of the first filtering circuit receives a digital signal and filters the digital signal;

[0014] A second extraction circuit, wherein an input end of the second extraction circuit is connected to an output end of the first filter circuit, and the second extraction circuit is used to extract a part of the digital signal;

[0015] The second filter circuit has an input end connected to the output end of the second extraction circuit to receive the digital signal, and the second filter circuit filters the received digital signal.

[0016] Some embodiments of the present application provide an analog-to-digital converter, comprising the trigger involved in the above embodiments.

[0017] Some embodiments of the present application provide a motor control system, comprising the analog-to-digital converter involved in the above embodiments.

[0018] Some embodiments of the present application provide a vehicle, including a power system of the vehicle, wherein the power system includes a motor body and a control system of the motor involved in the above embodiments.

[0019] The trigger, filter, analog-to-digital converter, motor control system and vehicle provided in the present application include a first selection circuit and a second selection circuit. The input end of the first selection circuit receives multiple first peripheral trigger signals, and the first selection circuit selects an output from the multiple first peripheral trigger signals. The second selection circuit is used to select one from the second peripheral trigger signal and at least one third peripheral trigger signal as an enable signal output. In this way, by selecting one from the multiple first peripheral trigger signals and at least one third peripheral trigger signal as an enable signal, the number of selected peripheral trigger signals can be increased, thereby adapting to more trigger scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A schematic diagram of the structure of a trigger provided in one embodiment of the present application;

[0022] Figure 2 A schematic diagram of the structure of a trigger provided in another embodiment of the present application;

[0023] Figure 3 A schematic diagram of the structure of a modulator provided in one embodiment of the present application;

[0024] Figure 4 for Figure 3 The schematic diagram of the working principle of the modulator shown;

[0025] Figure 5 A schematic diagram of the structure of a modulator provided in one embodiment of the present application;

[0026] Figure 6 for Figure 5 The schematic diagram of the working principle of the modulator shown;

[0027] Figure 7 A schematic diagram of the working principle of a modulator provided in one embodiment of the present application;

[0028] Figure 8 A schematic diagram of the structure of an analog-to-digital converter provided in another embodiment of the present application;

[0029] Fig. 9 A schematic diagram of the structure of a sampler provided in one embodiment of the present application;

[0030] Fig.10 A schematic diagram of the structure of another filter provided in another embodiment of the present application;

[0031] Fig.11 A schematic diagram of the structure of a modulator provided in one embodiment of the present application.

[0032] Reference numerals:

[0033] 10. trigger; 101. first selection circuit; 102. second selection circuit; 1011. first switch; 1012. second switch; 30. filter; 31. first filter circuit; 32. first extraction circuit; 33. third selection circuit; 34. second filter circuit; 35. fourth selection circuit; 311. first integration circuit; 312. first comb circuit; 36. second extraction circuit; 20. sampler; 40. modulator; 50. integrator; 60. shift circuit; SEL1. first selection signal; SEL2. second selection signal; SEL3. third selection signal; INTER_RUN. first enable signal; DSADC_EN. second enable signal; SEL_S1. first selection sub-signal; SEL_S2. second selection sub-signal; SEL_S 3. The third selection sub-signal; SEL_S4, the fourth selection sub-signal; MUX1, the first multiplexer; MUX2, the second multiplexer; MUX3, the third multiplexer; MUX4, the fourth multiplexer; MUX5, the fifth multiplexer; MUX6, the sixth multiplexer; MUX7, the seventh multiplexer; MUX8, the eighth multiplexer; MUX9, the ninth multiplexer; MUX10, the tenth multiplexer; MUX11, the eleventh multiplexer; MUX12, the twelfth multiplexer; MUX13, the thirteenth multiplexer; SEL9, the ninth selection signal; SEL10, the tenth selection signal; SEL11, the eleventh selection signal; SEL12, the twelfth selection signal; SEL13, the thirteenth selection signal; 21. The fifth selection circuit; 22. The sixth selection circuit; 23. The differential amplifier. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] Digital signal processing technology continues to develop and progress, but many things are essentially analog signals. Digital circuits cannot directly process these analog signals and need to convert them into digital signals that are discrete in time and amplitude.

[0036] The analog-to-digital converter is a commonly used analog signal processing circuit that can convert analog signals into digital signals.

[0037] At present, analog signals can be converted into digital signals through analog-to-digital converters, but analog-to-digital converters need to be triggered by trigger signals to work. Since the trigger can only be connected to a few fixed peripheral modules, it can only receive a few fixed peripheral trigger signals and cannot obtain peripheral trigger signals from other modules, resulting in limited and inflexible trigger signals.

[0038] More specifically, since there is usually only one multiplexer in the trigger for receiving the peripheral trigger signal, and due to the limitation on the number of the input terminals of the multiplexer, it can only be connected to a few fixed peripheral modules, and thus can only receive a few fixed peripheral trigger signals.

[0039] To this end, the present application proposes a trigger, which includes two selection circuits. The first selection circuit is used to receive multiple first peripheral trigger signals, and the second selection circuit is used to receive at least one second peripheral trigger signal. In this way, more peripheral trigger signals can be received, solving the problem of limited and inflexible peripheral trigger signals.

[0040] The technical solution of the present application is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0041] Figure 1 The trigger 10 provided in some embodiments of the present application is as follows: Figure 1 As shown, some embodiments of the present application provide a trigger 10, and the trigger 10 includes a first selection circuit 101 and a second selection circuit 102. The input end of the first selection circuit 101 receives multiple first peripheral trigger signals, and outputs a second peripheral trigger signal from the output end. The second peripheral trigger signal is one of the multiple first peripheral trigger signals. The first input end of the second selection circuit 102 is connected to the output end of the first selection circuit 101, and the second input end of the second selection circuit 102 receives at least one third peripheral trigger signal, and outputs an enable signal from the output end.

[0042] The first selection circuit 101 is used to select one of the plurality of first peripheral trigger signals as a second peripheral trigger signal for output. The first input end of the second selection circuit 102 receives the second peripheral trigger signal, the second input end of the second selection circuit 102 receives at least one third peripheral trigger signal, and the second selection circuit 102 is used to select one of the second peripheral trigger signal and the at least one third peripheral trigger signal as an enable signal for output.

[0043] In the above technical solution, the trigger 10 includes two selection circuits, the first selection circuit 101 is used to select an output from multiple first peripheral trigger signals, and the second selection circuit 102 is used to select one from the second peripheral trigger signal and at least one third peripheral trigger signal as an enable signal output. In this way, by selecting one from multiple first peripheral trigger signals and at least one third peripheral trigger signal as an enable signal, the number of selected peripheral trigger signals can be increased, thereby adapting to more trigger scenarios.

[0044] In some embodiments, continue to refer to Figure 1 The first selection circuit 101 is further provided with a control terminal, and the control terminal of the first selection circuit 101 receives a first selection signal SEL1, and the first selection signal SEL1 is used to represent the selected first peripheral trigger signal. In this way, the first selection circuit 101 selects an output from a plurality of first peripheral trigger signals under the control of the first selection signal SEL1.

[0045] In some embodiments, continue to refer to Figure 1 The second selection circuit 102 further includes a first output terminal and a second output terminal, and the enable signal includes a first enable signal INTER_RUN and a second enable signal DSADC_EN. The first output terminal outputs the first enable signal INTER_RUN, and the second output terminal outputs the second enable signal DSADC_EN. In this way, the trigger 10 can output two enable signals.

[0046] In some embodiments, the first enable signal INTER_RUN is one of the second peripheral trigger signal and at least one third peripheral trigger signal. More specifically, the second selection circuit 102 is used to select a trigger signal from the second peripheral trigger signal and at least one third peripheral trigger signal, use the selected trigger signal as the first enable signal INTER_RUN, and output it at the first output terminal of the second selection circuit 102.

[0047] In some embodiments, the second enable signal DSADC_EN is one of the second peripheral trigger signal and at least one third peripheral trigger signal. More specifically, the second selection circuit 102 is used to select a trigger signal from the second peripheral trigger signal and the at least one third peripheral trigger signal, and use the selected trigger signal as the second enable signal DSADC_EN, and output it at the second output terminal of the second selection circuit 102.

[0048] In some embodiments, continue to refer to Figure 1The second selection circuit 102 includes a first control terminal, the first control terminal of the second selection circuit 102 receives a second selection signal SEL2, and the second selection signal SEL2 is used to control the output signal of the first output terminal of the second selection circuit 102. Under the control of the second selection signal SEL2, the second selection circuit 102 selects a trigger signal from the second peripheral trigger signal and at least one third peripheral trigger signal received at the input terminal, uses the selected trigger signal as the first enable signal INTER_RUN, and outputs it at the first output terminal of the second selection circuit 102.

[0049] The second selection signal SEL2 corresponds to a plurality of states, each state corresponds to a peripheral trigger signal, and the selection configuration of the peripheral trigger signal is realized by changing the state corresponding to the second selection signal SEL2.

[0050] In some embodiments, continue to refer to Figure 1 The second selection circuit 102 includes a second control terminal, and the second control terminal of the second selection circuit 102 receives a third selection signal SEL3, and the third selection signal SEL3 is used to control the output signal of the second output terminal of the second selection circuit 102. Under the control of the third selection signal SEL3, the second selection circuit 102 selects a trigger signal from the second peripheral trigger signal and at least one third peripheral trigger signal received at the input terminal, and uses the selected trigger signal as the second enable signal DSADC_EN, and outputs it at the second output terminal of the second selection circuit 102.

[0051] The third selection signal SEL3 corresponds to a plurality of states, each state corresponds to a peripheral trigger signal, and the selection configuration of the peripheral trigger signal is realized by changing the state corresponding to the third selection signal SEL3.

[0052] In some embodiments, the second selection circuit 102 includes a second multiplexer MUX2, a first input terminal of the second multiplexer MUX2 receives a second peripheral trigger signal, a second input terminal of the second multiplexer MUX2 receives at least one third peripheral trigger signal, a first control terminal of the second multiplexer MUX2 receives a second selection signal SEL2, a second control terminal of the second multiplexer MUX2 receives a third selection signal SEL3, a first output terminal of the second multiplexer MUX2 outputs a first enable signal INTER_RUN, and a second output terminal of the second multiplexer MUX2 outputs a second enable signal DSADC_EN.

[0053] The first control terminal of the second multiplexer MUX2 is used to control the output signal of the first output terminal of the second multiplexer MUX2, and the second control terminal of the second multiplexer MUX2 is used to control the output signal of the second output terminal of the second multiplexer MUX2. The selection of the peripheral trigger signal is achieved by configuring different states of the second selection signal SEL2 and the third selection signal SEL3.

[0054] In some embodiments, reference Figure 2 The second selection circuit 102 further includes a third input terminal, the third input terminal of the second selection circuit 102 receives the internal trigger signal, and the enable signal is one of the second peripheral trigger signal, the internal trigger signal, and at least one third peripheral trigger signal. More specifically, the second selection circuit 102 is used to select a trigger signal from the second peripheral trigger signal, the internal trigger signal, and at least one third peripheral trigger signal for output.

[0055] In some embodiments, continue to refer to Figure 2 The second selection circuit 102 further includes a first output terminal and a second output terminal, the enable signal includes a first enable signal INTER_RUN and a second enable signal DSADC_EN, the first output terminal outputs the first enable signal INTER_RUN, and the second output terminal outputs the second enable signal DSADC_EN. In this way, the trigger 10 can output two enable signals.

[0056] In some embodiments, the first enable signal INTER_RUN is one of the second peripheral trigger signal, at least one internal trigger signal, and at least one third peripheral trigger signal. More specifically, the second selection circuit 102 selects a trigger signal from the second peripheral trigger signal, at least one internal trigger signal, and at least one third peripheral trigger signal, and outputs it at the first output terminal as the first enable signal INTER_RUN.

[0057] In some embodiments, the second enable signal DSADC_EN is one of the second peripheral trigger signal, at least one internal trigger signal, and at least one third peripheral trigger signal. More specifically, the second selection circuit 102 selects a trigger signal from the second peripheral trigger signal, at least one internal trigger signal, and at least one third peripheral trigger signal, and outputs it at the second output terminal as the second enable signal DSADC_EN.

[0058] In some embodiments, the second selection circuit 102 includes a first control terminal, the first control terminal of the second selection circuit 102 receives a fourth selection signal, and the fourth selection signal is used to control the output signal of the first output terminal of the second selection circuit 102. Under the control of the fourth selection signal, the second selection circuit 102 selects a trigger signal from the second peripheral trigger signal, the at least one internal trigger signal, and the at least one third peripheral trigger signal, and uses the selected trigger signal as the first enable signal INTER_RUN, and outputs it at the first output terminal of the second selection circuit 102.

[0059] The fourth selection signal corresponds to a plurality of states, each state corresponds to a peripheral trigger signal, and the selection configuration of the peripheral trigger signal is realized by changing the state corresponding to the fourth selection signal.

[0060] In some embodiments, the second selection circuit 102 includes a second control terminal, and the second control terminal of the second selection circuit 102 receives a fifth selection signal, and the fifth selection signal is used to control the output signal of the second output terminal of the second selection circuit 102. Under the control of the fifth selection signal, the second selection circuit 102 selects a trigger signal from the second peripheral trigger signal, the at least one internal trigger signal, and the at least one third peripheral trigger signal, and uses the selected trigger signal as the second enable signal DSADC_EN, and outputs it at the second output terminal of the second selection circuit 102.

[0061] The fifth selection signal corresponds to a plurality of states, each state corresponds to a peripheral trigger signal, and the selection configuration of the peripheral trigger signal is realized by changing the state corresponding to the fifth selection signal.

[0062] In some embodiments, continue to refer to Figure 2 The second selection circuit 102 includes a third multiplexer MUX3. The third multiplexer MUX3 is provided with a plurality of input terminals, one of which receives the second peripheral trigger signal, and the remaining input terminals of the third multiplexer MUX3 receive the third peripheral trigger signal one by one.

[0063] When there are multiple third peripheral trigger signals, the remaining input terminals of the third multiplexer MUX3 receive the third peripheral trigger signals one by one, which means that one input terminal of the third multiplexer MUX3 receives one third peripheral trigger signal.

[0064] The first control terminal of the third multiplexer MUX3 receives the first selection sub-signal SEL_S1, and the first output terminal of the third multiplexer MUX3 outputs the fourth peripheral trigger signal under the control of the first selection sub-signal SEL_S1. The fourth peripheral trigger signal is used to generate the first enable signal INTER_RUN, and the fourth peripheral trigger signal is one of the second peripheral trigger signal and at least one third peripheral trigger signal. By setting the third multiplexer MUX3, the third multiplexer MUX3 selects one from the second peripheral trigger signal and at least one third peripheral trigger signal under the control of the first selection sub-signal SEL_S1 as the fourth peripheral trigger signal, and outputs it at the first output terminal of the third multiplexer MUX3. The fourth peripheral trigger signal is used to generate the first enable signal INTER_RUN, for example: one of the fourth peripheral trigger signal and the internal trigger signal can be selected as the first enable signal INTER_RUN.

[0065] In some embodiments, the second control terminal of the third multiplexer MUX3 receives the third selection signal SEL3, and the third multiplexer MUX3 outputs the fifth peripheral trigger signal at the second output terminal under the control of the second selection sub-signal SEL_S2. The fifth peripheral trigger signal is used to generate the second enable signal DSADC_EN, and the fifth peripheral trigger signal is one of the second peripheral trigger signal and at least one third peripheral trigger signal. By setting the third multiplexer MUX3, the third multiplexer MUX3 selects one from the second peripheral trigger signal and at least one third peripheral trigger signal as the fifth peripheral trigger signal under the control of the second selection sub-signal SEL_S2, and outputs it at the second output terminal of the third multiplexer MUX3. The fifth peripheral trigger signal is used to generate the second enable signal DSADC_EN, for example: one of the fifth peripheral trigger signal and the internal trigger signal can be selected as the second enable signal DSADC_EN.

[0066] In some embodiments, the second selection circuit 102 further includes a fourth multiplexer MUX4, a first input terminal of the fourth multiplexer MUX4 receives the internal trigger signal, a second input terminal of the fourth multiplexer MUX4 is connected to the first output terminal of the third multiplexer MUX3, a control terminal of the fourth multiplexer MUX4 receives the third selection sub-signal SEL_S3, and an output terminal of the fourth multiplexer MUX4 outputs the first enable signal INTER_RUN. More specifically, a first input terminal of the fourth multiplexer MUX4 receives the internal trigger signal, a second input terminal of the fourth multiplexer MUX4 receives the fourth peripheral trigger signal, and the fourth multiplexer MUX4 is used to select one of the internal trigger signal and the fourth peripheral trigger signal as the first enable signal INTER_RUN under the control of the third selection sub-signal SEL_S3, and output it at the output terminal of the fourth multiplexer MUX4.

[0067] In some embodiments, the second selection circuit 102 further includes a fifth multiplexer MUX5, a first input terminal of the fifth multiplexer MUX5 receives an internal trigger signal, a second input terminal of the fifth multiplexer MUX5 is connected to an output terminal of the third multiplexer MUX3, a control terminal of the fifth multiplexer MUX5 receives a fourth selection sub-signal SEL_S4, and an output terminal of the fifth multiplexer MUX5 outputs a second enable signal DSADC_EN. A first input terminal of the fifth multiplexer MUX5 receives an internal trigger signal, a second input terminal of the fifth multiplexer MUX5 receives a fifth peripheral trigger signal, and the fifth multiplexer MUX5 is used to select one from the internal trigger signal and the fifth peripheral trigger signal as the second enable signal DSADC_EN under the control of the fourth selection sub-signal SEL_S4, and output it at the output terminal of the fifth multiplexer MUX5.

[0068] In some embodiments, the internal trigger signal received by the fourth multiplexer MUX4 is different from the internal trigger signal received by the fifth multiplexer MUX5.

[0069] In some embodiments, the second selection circuit 102 further includes a first switch 1011, the first switch 1011 is connected between the first output terminal of the third multiplexer MUX3 and the second input terminal of the fourth multiplexer MUX4, and the control terminal of the first switch 1011 also receives a first control signal. The first switch 1011 is closed or opened under the control of the first control signal, so that whether the third multiplexer MUX3 outputs the fourth peripheral trigger signal to the fourth multiplexer MUX4 can be controlled.

[0070] Among them, when the first switch 1011 is disconnected, the third multiplexer MUX3 stops outputting the fourth peripheral trigger signal to the fourth multiplexer MUX4, and the fourth multiplexer MUX4 selects the internal trigger signal for output. When the first switch 1011 is closed, the third multiplexer MUX3 outputs the fourth peripheral trigger signal to the fourth multiplexer MUX4, and the fourth multiplexer MUX4 selects the internal trigger signal and the fourth peripheral trigger signal for output, thereby realizing the selection of one from the plurality of first peripheral trigger signals, the second peripheral trigger signal and the internal trigger signal as the first enable signal INTER_RUN for output.

[0071] In some embodiments, the second selection circuit 102 further includes a second switch 1012, the second switch 1012 is connected between the second output terminal of the third multiplexer MUX3 and the second input terminal of the fifth multiplexer MUX5, and the control terminal of the second switch 1012 also receives a second control signal. The second switch 1012 is closed or opened under the control of the second control signal, so that the third multiplexer MUX3 can be controlled to output the fifth peripheral trigger signal to the fifth multiplexer MUX5.

[0072] When the second switch 1012 is disconnected, the third multiplexer MUX3 stops outputting the fifth peripheral trigger signal to the fifth multiplexer MUX5, and the fifth multiplexer MUX5 selects the internal trigger signal for output. When the second switch 1012 is closed, the third multiplexer MUX3 outputs the fifth peripheral trigger signal to the fifth multiplexer MUX5, and the fifth multiplexer MUX5 selects the internal trigger signal and the fifth peripheral trigger signal for output, thereby realizing the selection of one of the plurality of first peripheral trigger signals, the second peripheral trigger signal, and the internal trigger signal as the second enable signal DSADC_EN for output.

[0073] In some embodiments, the enable signal is an enable signal of an analog-to-digital converter.

[0074] In some embodiments, the first enable signal INTER_RUN is an enable signal of an integrator in the analog-to-digital converter, and the second enable signal DSADC_EN is an enable signal of a modulator of the analog-to-digital converter.

[0075] Among them, since the existing trigger can only receive peripheral trigger signals output by a few fixed peripheral modules, these peripheral trigger signals may not be able to trigger the modulator 50 and the integrator 50 at the same time, resulting in the current prohibition of the modulator 50 and the integrator 50 from using the same trigger source. Since the trigger 10 provided in the embodiment of the present application can receive more peripheral trigger signals, there may be a certain trigger signal that can trigger the modulator 50 and the integrator 50 at the same time, thereby solving the problem that the existing modulator 50 and the integrator 50 are prohibited from using the same trigger source.

[0076] In some embodiments, the first peripheral trigger signal may, for example, include at least one of a timer (TIMER) trigger signal, a pulse width modulation (PWM) trigger signal, a successive approximation analog-to-digital converter trigger signal, a comparator (CMP) trigger signal, a general-purpose input output (GPIO) trigger signal, a generic timer (GTM) trigger signal, and a system control unit (SCU) trigger signal, including but not limited to the above trigger signals.

[0077] In some embodiments, the third peripheral trigger signal is a pin trigger signal, and the pin trigger signal may be a pin trigger signal ITR0 or a pin trigger signal ITR1. The pin trigger signal may be, for example, a high level signal or a low level signal.

[0078] In some embodiments, the internal trigger signal is a start trigger signal (START) and an immediate enable trigger signal INTER_EN. The start trigger signal may be a trigger signal obtained by the controller from a register.

[0079] Continue to refer Figure 1 In the following, it is described by taking the example that the first selection circuit 101 includes the first multiplexer MUX1 and the second selection circuit 102 includes the second multiplexer MUX2.

[0080] An input end of the first multiplexer MUX1 is connected to a peripheral module, which outputs a first peripheral trigger signal. The peripheral module may include at least one of a timer, a pulse width modulation module, a successive approximation analog-to-digital converter, a comparator, a general input and output module, a general timer and a system control unit.

[0081] In practical applications, the first multiplexer MUX1 may include a control end, the control end of the first multiplexer MUX1 receives a first selection signal SEL1, the first multiplexer MUX1 selects a first peripheral trigger signal from the received multiple first peripheral trigger signals according to the first selection signal SEL1, and outputs it to the second multiplexer MUX2 through the output end of the first multiplexer MUX1. For example, the first selection signal SEL1 may carry an identifier, an address, etc. of a first peripheral trigger signal.

[0082] The first input end of the second multiplexer MUX2 receives the second peripheral trigger signal, the second input end of the second multiplexer MUX2 receives at least one third peripheral trigger signal, the first control end of the second multiplexer MUX2 receives the second selection signal SEL2, the second control end of the second multiplexer MUX2 receives the third selection signal SEL3, the first output end of the second multiplexer MUX2 outputs the first enable signal INTER_RUN, and the second output end of the second multiplexer MUX2 outputs the second enable signal DSADC_EN. In this way, the first enable signal INTER_RUN is one of the second peripheral trigger signal, at least one internal trigger signal, and at least one third peripheral trigger signal. The second enable signal DSADC_EN is one of the second peripheral trigger signal, at least one internal trigger signal, and at least one third peripheral trigger signal.

[0083] The first enable signal INTER_RUN is used as an enable signal of the integrator 50 in the analog-to-digital converter to control whether the integrator 50 is in a working state. After the enable end of the integrator 50 receives the first enable signal INTER_RUN, the integrator 50 can integrate the received digital signal.

[0084] The second enable signal DSADC_EN is used as an enable signal of the modulator 40 in the analog-to-digital converter to control whether the modulator 40 is in a working state. After the enable end of the modulator 40 receives the second enable signal DSADC_EN, the modulator enters an enabled state, and the modulator 40 can convert the analog signal Vin into a digital signal, and output the digital signal through the output end of the modulator 40.

[0085] Continue to refer Figure 2 In the following, it is described as an example that the first selection circuit 101 includes a first multiplexer MUX1, and the second selection circuit 102 includes a third multiplexer MUX3, a fourth multiplexer MUX4, and a fifth multiplexer MUX5.

[0086] The first multiplexer MUX1 selects a first peripheral trigger signal from the received multiple first peripheral trigger signals according to the first selection signal SEL1 and outputs it. The input end of the third multiplexer MUX3 is connected to the output end of the first multiplexer MUX1 to receive the second peripheral trigger signal. The first control end of the third multiplexer MUX3 receives the first selection sub-signal SEL_S1, and the third multiplexer MUX3 outputs the fourth peripheral trigger signal at the second output end under the control of the first selection sub-signal SEL_S1. The fifth peripheral trigger signal is one of the second peripheral trigger signal and at least one third peripheral trigger signal. The second control end of the third multiplexer MUX3 receives the second selection sub-signal SEL_S2, and the third multiplexer MUX3 outputs the fifth peripheral trigger signal at the second output end under the control of the second selection sub-signal SEL_S2. The fifth peripheral trigger signal is used to generate the second enable signal DSADC_EN, and the fifth peripheral trigger signal is one of the second peripheral trigger signal and at least one third peripheral trigger signal.

[0087] The first input end of the fourth multiplexer MUX4 receives the internal trigger signal, the second input end of the fourth multiplexer MUX4 is connected to the first output end of the third multiplexer MUX3, the control end of the fourth multiplexer MUX4 receives the third selection sub-signal SEL_S3, and the fourth multiplexer MUX4 is used to select one from the internal trigger signal and the fourth peripheral trigger signal as the first enable signal INTER_RUN under the control of the third selection sub-signal SEL_S3, and output it at the output end of the fourth multiplexer MUX4.

[0088] The first input end of the fifth multiplexer MUX5 receives the internal trigger signal, the second input end of the fifth multiplexer MUX5 is connected to the second output end of the third multiplexer MUX3, the control end of the fifth multiplexer MUX5 receives the fourth selection sub-signal SEL_S4, and the fifth multiplexer MUX5 is used to select one from the internal trigger signal and the fifth peripheral trigger signal as the second enable signal DSADC_EN under the control of the fourth selection sub-signal SEL_S4, and output it at the output end of the fifth multiplexer MUX5.

[0089] Considering that the digital signal is highly quantized, the digital signal has quantization noise, and the digital signal can be filtered through the filter 30 to reduce the quantization noise. Usually, the filter 30 is provided with a multi-stage filter circuit, and the stage configuration of the filter circuit in the filter 30 determines the attenuation and delay properties, so that the original data samples can be extracted at a configured extraction rate to achieve downsampling.

[0090] However, the number of stages of the filter circuit in the filter 30 is fixed and cannot be changed, so that the stopband attenuation range of the filter cannot be changed, and different filter frequency usage scenarios cannot be applied.

[0091] For this reason, Figure 3 As shown, some embodiments of the present application provide a filter 30 , and the filter 30 includes a third selection circuit 33 and at least one first filtering circuit 31 .

[0092] The input end of the third selection circuit 33 is used to receive the digital signal, and the input end of each first filter circuit 31 is connected to the output end of the third selection circuit 33. The first filter circuit 31 is used to filter the received signal, and the third selection circuit 33 is used to adjust the number of first filter circuits 31 involved in filtering.

[0093] The third selection circuit 33 adjusts the number of the first filter circuits 31 involved in filtering by controlling whether to output the digital signal to the input end of the first filter circuit 31 .

[0094] In the above technical solution, the third selection circuit 33 adjusts the number of the first filter circuits 31 participating in the filtering, so that the stopband attenuation range of the filter 30 can be adjusted to adapt to application scenarios with variable stopband attenuation requirements.

[0095] In some embodiments, a plurality of first filter circuits 31 are connected in cascade, and the third selection circuit 33 is provided with a plurality of output terminals, one of which is connected to an input terminal of a first filter circuit 31 .

[0096] The cascade connection of multiple first filter circuits 31 means that the output end of the first first filter circuit 31 is connected to the input end of the second first filter circuit 31, the output end of the second first filter circuit 31 is connected to the input end of the third first filter circuit 31, and so on, the output end of the second-to-last first filter circuit 31 is connected to the input end of the last first filter circuit 31. The third selection circuit 33 is provided with multiple output ends, and one output end is connected to the input end of one first filter circuit 31. By adjusting the output end of the third selection circuit 33 that outputs the digital signal, the first filter circuit 31 that receives the digital signal can be adjusted.

[0097] For example, the first output end of the third selection circuit 33 is connected to the input end of the first first filter circuit, the second output end of the third selection circuit 33 is connected to the input end of the second first filter circuit, and so on. If the second output end of the third selection circuit 33 outputs a digital signal, the input end of the second first filter circuit receives the digital signal, and the second first filter circuit can filter the digital signal and pass it to the input end of the third first filter circuit. The third first filter circuit filters the input digital signal and passes it to the input end of the fourth first filter circuit, and so on, until the last first filter circuit completes filtering and outputs.

[0098] For another example: if the third output terminal of the third selection circuit 33 outputs a digital signal, the input terminal of the third first filter circuit receives the digital signal, and the third first filter circuit can filter the digital signal and pass it to the input terminal of the fourth first filter circuit. The fourth first filter circuit filters the input digital signal and passes it to the input terminal of the fifth first filter circuit, and so on, until the last first filter circuit completes filtering and outputs. Compared with outputting a digital signal at the second first output terminal of the third selection circuit 33, outputting a digital signal at the third output terminal of the third selection circuit 33 reduces the number of first filter circuits 31 participating in filtering, so that the third selection circuit 33 can adjust the number of first filter circuits 31 participating in filtering.

[0099] In some embodiments, the control end of the third selection circuit 33 receives a sixth selection signal, and the sixth selection signal is used to select an output end from a plurality of output ends to output a digital signal. More specifically, the third selection circuit 33 selects an output end from a plurality of output ends to output a digital signal under the control of the sixth selection signal. The sixth selection signal corresponds to a plurality of states, and each state corresponds to outputting a digital signal at an output end. By configuring the state of the sixth selection signal, it is possible to configure which output end outputs the digital signal, thereby realizing the third selection circuit 33 adjusting the number of first filter circuits 31 participating in filtering.

[0100] In some embodiments, the third selection circuit 33 includes a sixth multiplexer MUX6, an input end of the sixth multiplexer MUX6 receives a digital signal, an output end of the sixth multiplexer MUX6 is connected to an input end of a first filter circuit 31, and a control end of the sixth multiplexer MUX6 receives a sixth selection signal. More specifically, the sixth selection signal is used to determine at which output end of the sixth multiplexer MUX6 the digital signal is output, and under the control of the sixth selection signal, the sixth multiplexer MUX6 outputs a digital signal at one of its output ends, so that the first filter circuit 31 connected to the output end receives the digital signal, filters the digital signal, and outputs it to the first filter circuit 31 of the next stage.

[0101] In some embodiments, the first filter circuit 31 includes a first integration circuit 311 and a first comb circuit 312, the output end of the first integration circuit 311 is connected to the input end of the first comb circuit 312, and the input end of each first integration circuit 311 is connected to the output end of the third selection circuit 33. More specifically, the first integration circuit 311 integrates the digital signal received at its input end, and the digital signal at its input end can be the digital signal output by the third selection circuit 33, or the digital signal output by the first filter circuit 31 of the previous stage. The first comb circuit 312 is used to filter the digital signal output by the first integration circuit 311. More specifically, the signal of a specific frequency is enhanced or suppressed, so as to filter the digital signal.

[0102] In some embodiments, each first integration circuit 311 outputs a signal that is a sum of the digital signal received in the current clock cycle and the digital signal received in the previous clock cycle, and each first comb circuit 312 outputs a signal that is a subtraction of the digital signal received in the current clock cycle and the digital signal received in the previous N clock cycles.

[0103] In some embodiments, the filter 30 further includes a first extraction circuit 32 , the input end of the first extraction circuit 32 is connected to the output end of the last-stage first filtering circuit 31 , and the output end of the first extraction circuit 32 is connected to the output end of a third selection circuit 33 .

[0104] In some embodiments, the first extraction circuit 32 is used to extract a digital signal of a partial clock cycle, and N is equal to the clock cycle extracted by the second extraction circuit 36 ​​and is an integer greater than 1.

[0105] The output end of the first extraction circuit 32 is connected to the output end of a third selection circuit 33 , so that the third selection circuit 33 can directly output the digital signal without passing through any first filtering circuit 31 .

[0106] Combine the following Figure 4 It is explained that the third selection circuit 33 adjusts the number of the first filter circuits 31 involved in filtering. Figure 3 In the embodiment, the first output terminal of the third selection circuit 33 is connected to the output terminal of the first extraction circuit 32, the second output terminal of the third selection circuit 33 is connected to the input terminal of the N-1th first filter circuit 31, the third output terminal of the third selection circuit 33 is connected to the input terminal of the N-2th first filter circuit 31, and so on. The Nth output terminal of the third selection circuit 33 is connected to the input terminal of the 1st first filter circuit 31.

[0107] When the digital signal is output from the first output terminal of the third selection circuit 33 , the digital signal is directly output without passing through any first filtering circuit 31 .

[0108] like Figure 4 In the first case shown, when the digital signal is outputted at the second output terminal of the third selection circuit 33, the digital signal is filtered by the N-1th first filter circuit 31, enters the first extraction circuit 32 for digital signal extraction and output. That is, there is only one first filter circuit 31 involved in the filtering.

[0109] like Figure 4 In the second case shown, when the third output terminal of the third selection circuit 33 outputs a digital signal, the digital signal is filtered by the N-2th first filter circuit 31, enters the N-1th first filter circuit 31 for filtering, and then enters the first extraction circuit 32 for digital signal extraction and output. That is, there are two first filter circuits 31 involved in filtering.

[0110] like Figure 4 In the third case shown, when the digital signal is outputted from the fourth output terminal of the third selection circuit 33, the digital signal is filtered by the N-3th first filter circuit 31, then enters the N-2th first filter circuit 31 for filtering, then enters the N-1th first filter circuit 31 for filtering, then enters the first extraction circuit 32 for digital signal extraction and output. That is, there are three first filter circuits 31 involved in filtering.

[0111] like Figure 4 In the fourth case shown, when the digital signal is output at the X+1th output terminal of the third selection circuit 33, the digital signal is filtered by the NXth first filter circuit 31, then enters the N-X+1th first filter circuit 31 for filtering, and then enters the N-X+2th first filter circuit 31 for filtering, and so on, after being filtered by the N-1th first filter circuit 31, it enters the first extraction circuit 32 for digital signal extraction and output. That is, there are X first filter circuits 31 involved in filtering.

[0112] In some embodiments, continue to refer to Figure 5The filter 30 further includes a fourth selection circuit 35 and at least one second filtering circuit 34 .

[0113] The input end of the fourth selection circuit 35 is connected to the output end of the last-stage first filter circuit 31, and the input end of each second filter circuit 34 is connected to the output end of the fourth selection circuit 35. The second filter circuit 34 is used to filter the signal at the input end of the second filter circuit 34; the fourth selection circuit 35 is used to adjust the number of second filter circuits 34 involved in filtering.

[0114] Wherein, when the filter 30 includes only one first filter circuit 31, the input end of the fourth selection circuit 35 is connected to the output end of the first filter circuit 31, and receives the digital signal output by the first filter circuit 31. When the filter 30 includes multiple first filter circuits 31, the input end of the fourth selection circuit 35 is connected to the output end of the last-stage first filter circuit 31, and receives the digital signal output by the last-stage first filter circuit 31.

[0115] The fourth selection circuit 35 adjusts the number of the second filter circuits 34 involved in filtering by controlling whether to output the digital signal to the input end of the second filter circuit 34 .

[0116] In some embodiments, multiple second filter circuits 34 are connected in cascade, and the fourth selection circuit 35 is provided with multiple output terminals, one of which is connected to the input terminal of a second filter circuit 34. The cascade connection of multiple second filter circuits 34 means that the output terminal of the first second filter circuit 34 is connected to the input terminal of the second second filter circuit 34, the output terminal of the second second filter circuit 34 is connected to the input terminal of the third second filter circuit 34, and so on, the output terminal of the second-to-last second filter circuit 34 is connected to the input terminal of the last second filter circuit 34. The fourth selection circuit 35 is provided with multiple output terminals, one of which is connected to the input terminal of a second filter circuit 34. By selecting the output terminal of the fourth selection circuit 35 that outputs the digital signal, the second filter circuit 34 that receives the digital signal can be selected.

[0117] For example, the first output end of the fourth selection circuit 35 is connected to the input end of the first second filter circuit, the second output end of the fourth selection circuit 35 is connected to the input end of the second second filter circuit, and so on. If the second output end of the fourth selection circuit 35 outputs a digital signal, the input end of the second second filter circuit receives the digital signal, and the second second filter circuit can filter the digital signal and pass it to the input end of the third second filter circuit. The third second filter circuit filters the input digital signal and passes it to the input end of the fourth second filter circuit, and so on.

[0118] For another example: if the third output terminal of the fourth selection circuit 35 outputs a digital signal, the input terminal of the third second filter circuit receives the digital signal, and the third second filter circuit can filter the digital signal and pass it to the input terminal of the fourth second filter circuit. The fourth second filter circuit filters the input digital signal and passes it to the input terminal of the fifth second filter circuit, and so on. Compared with outputting a digital signal at the second output terminal of the fourth selection circuit 35, outputting a digital signal at the third output terminal of the fourth selection circuit 35 reduces the number of second filter circuits 34 involved in filtering, so that the fourth selection circuit 35 can adjust the number of second filter circuits 34 involved in filtering.

[0119] In some embodiments, the control end of the fourth selection circuit 35 receives a seventh selection signal, and the seventh selection signal is used to select an output end from a plurality of output ends to output a signal. More specifically, the fourth selection circuit 35 selects an output end from a plurality of output ends to output a digital signal under the control of the seventh selection signal. The seventh selection signal corresponds to a plurality of states, and each state corresponds to outputting a digital signal at an output end. By configuring the state of the seventh selection signal, it is possible to configure which output end outputs the digital signal, thereby realizing the fourth selection circuit 35 adjusting the number of second filter circuits 34 involved in filtering.

[0120] In some embodiments, the filter 30 also includes a second extraction circuit 36, an input end of the second extraction circuit 36 ​​is connected to the output end of the first filter circuit 31 of the last stage, an input end of the fourth selection circuit 35 is connected to the output end of the second extraction circuit 36, and an output end of the third selection circuit 33 is connected to the output end of the second filter circuit of the last stage.

[0121] In some embodiments, the second extraction circuit 36 ​​is used to extract a digital signal of a partial clock cycle.

[0122] The fourth selection circuit 35 receives the digital signal extracted by the second extraction circuit 36, and transmits the extracted digital signal to each output terminal of the fourth selection circuit 35. One output terminal of the third selection circuit 33 is connected to the output terminal of the second filter circuit of the last stage, so that the third selection circuit 33 can directly output the digital signal without passing through any first filter circuit 31 and any second filter circuit 34.

[0123] In some embodiments, the fourth selection circuit 35 includes a seventh multiplexer MUX7, an output end of the seventh multiplexer MUX7 is connected to an input end of a second filter circuit 34, a control end of the seventh multiplexer MUX7 receives a seventh selection signal, and an output end of the sixth multiplexer MUX6 is also connected to an output end of the second filter circuit 34 of the last stage. More specifically, the seventh selection signal is used to determine at which output end of the seventh multiplexer MUX7 the digital signal is output, and the seventh multiplexer MUX7 outputs the digital signal at one of its output ends under the control of the seventh selection signal, so that the second filter circuit 34 connected to the output end receives the digital signal, filters the digital signal and outputs it to the second filter circuit 34 of the next stage.

[0124] In some embodiments, the first filter circuit 31 includes a second integration circuit, and the second filter circuit 34 includes a second comb circuit. More specifically, the second integration circuit integrates the digital signal received at its input end, and the digital signal at its input end can be the digital signal output by the third selection circuit 33, or the digital signal output by the second integration circuit of the previous stage. The second comb circuit filters the digital signal received at its input end, and the digital signal at its input end can be the digital signal output by the fourth selection circuit 35, or the digital signal output by the second comb circuit of the previous stage. More specifically, the signal of a specific frequency is enhanced or suppressed, thereby filtering the digital signal.

[0125] In some embodiments, each second integration circuit outputs a signal that adds the digital signal received in the current clock cycle and the digital signal received in the previous clock cycle. Each second comb circuit outputs a signal that subtracts the digital signal received in the current clock cycle from the digital signal received in the previous clock cycle.

[0126] In some embodiments, the number of first filter circuits 31 involved in filtering is the same as the number of second filter circuits 34 involved in filtering. By setting this, the filtering performance of the filter can be improved.

[0127] against Figure 5 The filter 30 shown in the figure continuously performs addition operations during calculation, resulting in a continuous increase in the word length of the data inside it. In order to prevent the word length from being set too short to cause overflow, the word length formula of the filter 30 is as follows:

[0128] B max =B in +X*log2D-1

[0129] Among them, B max is the maximum word length, B in is the output bit width of the quantizer, X is the order of the filter 30, and D is the decimation factor of the filter 30.

[0130] Combine the following Figure 6 It is explained that the third selection circuit 33 adjusts the number of the first filter circuits 31 participating in the filtering.

[0131] exist Figure 5 In the embodiment, the first output terminal of the third selection circuit 33 is connected to the output terminal of the first extraction circuit 32, the second output terminal of the third selection circuit 33 is connected to the input terminal of the N-1th first filter circuit 31, the third output terminal of the third selection circuit 33 is connected to the input terminal of the N-2th first filter circuit 31, and so on. The Nth output terminal of the third selection circuit 33 is connected to the input terminal of the 1st first filter circuit 31.

[0132] The first output terminal of the fourth selection circuit 35 is connected to the output terminal of the N-1th second filter circuit 34, the second output terminal of the fourth selection circuit 35 is connected to the input terminal of the N-1th second filter circuit 34, the third output terminal of the fourth selection circuit 35 is connected to the input terminal of the N-2th second filter circuit 34, and so on. The N-1th output terminal of the fourth selection circuit 35 is connected to the input terminal of the first second filter circuit 34.

[0133] When the digital signal is output from the first output terminal of the third selection circuit 33 , the digital signal is directly output without passing through any first filter circuit 31 and any second filter circuit 34 .

[0134] like Figure 6 In the first case shown, when the second output terminal of the third selection circuit 33 outputs a digital signal, the digital signal is filtered by the N-1th first filter circuit 31, enters the first extraction circuit 32 for digital signal extraction and then output. That is, there is one first filter circuit 31 involved in filtering. Correspondingly, the first output terminal of the fourth selection circuit 35 also outputs a digital signal, and the digital signal is filtered by the N-1th second filter circuit 34 and then output. That is, there is one second filter circuit 34 involved in filtering.

[0135] like Figure 6 In the second case shown, when the third output terminal of the third selection circuit 33 outputs a digital signal, the digital signal is filtered by the N-2 first filter circuit 31, then enters the N-1 first filter circuit 31 for filtering, and then enters the first extraction circuit 32 for digital signal extraction and output. That is, there are two first filter circuits 31 involved in filtering. Correspondingly, the second output terminal of the fourth selection circuit 35 also outputs a digital signal, and the digital signal is filtered by the N-2 second filter circuit 34, and then output by the N-1 second filter circuit 34. That is, there are two second filter circuits 34 involved in filtering.

[0136] like Figure 6 In the third case shown, when the digital signal is output from the fourth output terminal of the third selection circuit 33, the digital signal is filtered by the N-3rd first filter circuit 31, then enters the N-2nd first filter circuit 31 for filtering, then enters the N-1st first filter circuit 31 for filtering, then enters the first extraction circuit 32 for digital signal extraction and output. That is, there are three first filter circuits 31 involved in filtering. Correspondingly, the third output terminal of the fourth selection circuit 35 also outputs a digital signal, and the digital signal is filtered by the N-3rd second filter circuit 34, then filtered by the N-2nd second filter circuit 34, and then output by the N-1st second filter circuit 34. That is, there are three second filter circuits 34 involved in filtering.

[0137] like Figure 6 In the fourth case shown, when the digital signal is output at the X+1th output terminal of the third selection circuit 33, the digital signal is filtered by the NXth first filter circuit 31, then enters the N-X+1th first filter circuit 31 for filtering, and then enters the N-X+2th first filter circuit 31 for filtering, and so on, after being filtered by the N-1th first filter circuit 31, then enters the first extraction circuit 32 for digital signal extraction and output. That is, the number of first filter circuits 31 participating in the filtering is X. Correspondingly, the Xth output terminal of the fourth selection circuit 35 also outputs a digital signal, and the digital signal is filtered by the NXth second filter circuit 34, then filtered by the N-X+1th second filter circuit 34, then enters the N-X+2th second filter circuit 34 for filtering, and so on, and finally outputs through the N-1th second filter circuit 34. That is, the number of second filter circuits 34 participating in the filtering is X.

[0138] Need to explain, such as Figure 7 As shown, the first sidelobe level stopband attenuation of a single-stage cascade filter circuit is almost fixed at 13.46 dB, which does not meet the usual stopband attenuation requirements. A larger stopband attenuation can be achieved by cascading multiple filter circuits. For example, when the cascade number is X, the stopband attenuation is X times the single-stage attenuation. However, the cascade number of the cascade filter circuit is fixed, and its stopband attenuation is almost fixed at 13.46*X dB, which cannot be applied to application scenarios where the stopband attenuation requirements are variable. By setting the third selection circuit 33 and the fourth selection circuit 35, the number of the first filter circuits 31 involved in the filtering and the number of the second filter circuits 34 involved in the filtering are selected to adapt to application scenarios where the stopband attenuation requirements are variable.

[0139] It should be noted that the first extraction circuit 32 and the second extraction circuit 36 ​​mentioned above can be understood as the extraction factor D. The main factor controlling the cutoff frequency is the extraction factor D, which determines the position of the stopband attenuation. As the extraction factor D increases, the number of lobes of the cascade-comb filter 30 increases, and the signal attenuation in the passband of the cascade-comb filter 30 becomes more severe. Increasing the number of stages X will increase the attenuation of the stopband, but at the same time it will also increase the drop in the passband, so the number of stages and the extraction factor D need to be selected according to actual needs.

[0140] In the design process of filter implementation, sufficient passband characteristics are provided in the specified frequency range by selecting the decimation factor D and the cascaded level X of the filter circuit. The higher the level of the filter, the more obvious the stopband attenuation effect, but it will bring the problem of large passband attenuation. The larger the decimation factor, the smaller the cutoff frequency. It is necessary to flexibly switch the level to select the appropriate stopband attenuation and cutoff frequency according to different application scenarios.

[0141] Therefore, the above two filters 30 can not only filter out high-frequency noise, but also reduce the data output rate by setting different decimation factors D. The signal frequency is reduced to near the Nyquist frequency by decimation, and finally the required multi-bit digital signal is output.

[0142] Some embodiments of the present application provide a filter, the filter comprising a first filtering circuit and a first extraction circuit, the input end of the first filtering circuit receives a digital signal and filters the digital signal. The input end of the second extraction circuit is connected to the output end of the first filtering circuit, and the second extraction circuit is used to extract part of the digital signal.

[0143] In the above filter architecture, since the first extraction circuit is located at the end, all devices in the first filter circuit operate at the same clock frequency, and the overall power consumption is high. The first filter circuit contains N times of delay, and the increase in the number of cascade stages will introduce a large number of register requirements, increasing the difficulty of hardware implementation.

[0144] More specifically, the first filtering circuit includes a first integration circuit and a first comb circuit. The first integration circuit outputs a signal that is the sum of the digital signal received in the current clock cycle and the digital signal received in the previous clock cycle. Each first comb circuit outputs a signal that is the subtraction of the digital signal received in the current clock cycle and the digital signal received in the previous N clock cycles.

[0145] In some embodiments, the filter includes multiple first filter circuits, the output end of the first first filter circuit is connected to the input end of the second first filter circuit, the output end of the second first filter circuit is connected to the input end of the third first filter circuit, and so on, and the output end of the first filter circuit of the last stage is connected to the first extraction circuit.

[0146] In the above filter architecture, the first half of each first filter circuit is an integral part, the second half is a comb filter part, and finally N-fold extraction is performed. All devices work at the same clock frequency, and the overall power consumption is high. In addition, in the comb filter part, each stage contains N-fold delay. The increase in the number of cascade stages will introduce a large number of register requirements, increasing the difficulty of hardware implementation.

[0147] Some embodiments of the present application provide a filter, the filter comprising a first filter circuit, a second extraction circuit and a second filter circuit. The input end of the first filter circuit receives a digital signal and filters the digital signal. The input end of the second extraction circuit is connected to the output end of the first filter circuit, and the second extraction circuit is used to extract part of the digital signal. The input end of the second filter circuit is connected to the output end of the second extraction circuit, and the second filter circuit filters the received digital signal.

[0148] In the above technical solution, by arranging the second extraction circuit between the first filter circuit and the second filter circuit, the first filter circuit and the second filter circuit do not need to work at the same clock frequency, which can reduce power loss. In addition, no delay is required in the first filter circuit and the second filter circuit, which can reduce the use of registers and hardware.

[0149] In some embodiments, there are multiple first filter circuits and second filter circuits, multiple first filter circuits are cascaded to form at least one first filter circuit group, multiple second filter circuits are cascaded to form at least one second filter circuit group, and the second extraction circuit is arranged between the first filter circuit group and the second filter circuit group.

[0150] More specifically, the output end of the first first filter circuit is connected to the input end of the second first filter circuit, the output end of the second first filter circuit is connected to the input end of the third first filter circuit, and so on. The output end of the last first filter circuit is connected to the input end of the second extraction circuit, the output end of the second extraction circuit is connected to the input end of the first second filter circuit, the output end of the first second filter circuit is connected to the input end of the second second filter circuit, and so on. The output end of the last second filter circuit outputs a signal.

[0151] In some embodiments, the first filter circuit includes a second integration circuit, and the second filter circuit includes a second comb circuit. Each second integration circuit is used to output a signal that is a sum of a digital signal received in a current clock cycle and a digital signal received in a previous clock cycle. The second extraction circuit is used to extract a digital signal of a partial clock cycle. Each second comb circuit is used to output a signal that is a subtraction of a digital signal received in a current clock cycle and a digital signal received in a previous clock cycle.

[0152] In the above technical solution, the digital signal is integrated by the multi-stage second integration circuit and then output to the second extraction circuit. The second extraction circuit extracts the digital signal of a part of the period, and then the signal is filtered by multiple second comb circuits. Since there is no data with N times delay in the second integration circuit and the second comb circuit, the hardware requirements for the register are reduced. And since the second extraction circuit is arranged between the second integration circuit and the second comb circuit, the second integration circuit and the second comb circuit operate at different frequencies, which can reduce power loss.

[0153] Some embodiments of the present application provide an analog-to-digital converter, including the trigger 10 involved in the above embodiments.

[0154] In some embodiments, Figure 8 As shown, the analog-to-digital converter further includes a modulator 40, an enable terminal of the modulator 40 is connected to a trigger 10, and the trigger 10 outputs an enable signal to the modulator 40. The modulator 40 converts the received analog signal into a digital signal.

[0155] In some embodiments, Figure 8 As shown, the analog-to-digital converter further includes the filter 30 involved in the above embodiment, and the input end of the filter 30 is connected to the output end of the modulator 40. The filter 30 receives the digital signal output by the modulator 40, and outputs the digital signal after filtering. The enable end of the filter 30 is connected to the trigger 10, and the filter 30 performs filtering on the digital signal under the control of the enable signal.

[0156] In some embodiments, Figure 8 As shown, the analog-to-digital converter also includes an integrator 50, the input end of the integrator 50 is connected to the output end of the modulator 40, and the enable end of the integrator 50 is connected to the trigger 10. The enable end of the integrator 50 is connected to the trigger 10, and the integrator 50 performs integration processing on the digital signal under the control of the enable signal. In this way, the data output rate can be further reduced. Among them, the integrator 50 integrates the result values ​​generated during the defined integration window by adding a configurable number of values ​​to construct a final result value.

[0157] More specifically, the enable terminal of the integrator 50 is connected to the first output terminal of the trigger 10, the input terminal of the integrator 50 is connected to the output terminal of the filter 30, and the first output terminal of the trigger 10 outputs the first enable signal INTER_RUN. The integrator 50 is used to perform an integration operation on the digital signal output by the filter 30 when receiving the first enable signal INTER_RUN, and output the signal after the integration operation.

[0158] In the above embodiment, the trigger source of the modulator also adopts hardware external trigger and software internal trigger, and the trigger source of the integrator also adopts hardware external trigger and software internal trigger. Accordingly, the trigger includes a first multiplexer, a third multiplexer, a fourth multiplexer and a fifth multiplexer.

[0159] Among them, the hardware external trigger includes pin trigger signal ITR0, pin trigger signal ITR1, timer trigger signal, pulse width modulation trigger signal, successive approximation analog-to-digital converter trigger signal, comparator trigger signal, general input and output trigger signal, general timer trigger signal and system control unit trigger signal.

[0160] If the modulator selects hardware external trigger, when the first multiplexer detects that a certain peripheral module outputs a rising edge trigger signal, it outputs a trigger signal and outputs it to the modulator through the third multiplexer and the fourth multiplexer. The enable end of the modulator receives the rising edge trigger signal, and the modulator starts working. The modulator converts the analog signal into an N-bit digital signal output. The N-bit digital signal is filtered and output. The sixth multiplexer in the filter selects the number of the first filter circuits involved in the filtering, and the seventh multiplexer in the filter selects the number of the second filter circuits involved in the filtering.

[0161] If the integrator selects software triggering, a start signal is written, the fifth multiplexer outputs an enable signal, and the enable end of the integrator receives a rising edge trigger signal, so that the integrator starts working.

[0162] As described above, both the modulator and the integrator can obtain trigger signals from the first multiplexer, and the peripheral modules connected to the first multiplexer can be switched flexibly, thereby overcoming the problem that when triggering the modulator and the integrator, the same trigger source is prohibited from being used, which makes the limited trigger source selection method more restricted and inflexible.

[0163] In some embodiments, Figure 8 As shown, the analog-to-digital converter also includes a sampler 20, the output end of the sampler 20 is connected to the input end of the modulator 40, the sampler 20 is used to obtain an initial analog signal, and output an analog signal to the modulator 40 according to the initial analog signal. Oversampling is performed by the sampler 20 to improve the quality and accuracy of the signal.

[0164] In some examples, such as Fig. 9 As shown, the sampler 20 includes a fifth selection circuit 21, a sixth selection circuit 22 and a differential amplifier 23. The input terminals of the fifth selection circuit 21 and the sixth selection circuit 22 receive analog signals, and the fifth selection circuit 21 may have multiple input terminals, so as to receive multiple analog signals. Correspondingly, the sixth selection circuit 22 may have multiple input terminals, so as to receive multiple analog signals.

[0165] A first input terminal of the differential amplifier 23 is connected to an output terminal of the fifth selection circuit 21 , a second input terminal of the differential amplifier 23 is connected to an output terminal of the sixth selection circuit 22 , and an output terminal of the differential amplifier 23 serves as an output terminal of the sampler 20 .

[0166] When the control end of the fifth selection circuit 21 receives the fifth control signal, it selects a signal from the received reference signal DSVREF and at least one analog signal DSPA-DSPZ as the first analog signal according to the fifth control signal, and outputs the first analog signal through the output end of the fifth selection circuit 21. When the control end of the sixth selection circuit 22 receives the sixth control signal, it selects a signal from the received reference signal DSVREF and at least one analog signal DSNA-DSNZ as the second analog signal according to the sixth control signal, and outputs the second analog signal through the output end of the sixth selection circuit 22.

[0167] The differential amplifier 23 can perform differential processing on the first analog signal and the second analog signal, and amplify the differential result before outputting it to the modulator 40. The amplification factor of the differential amplifier 23 includes but is not limited to 1, 2, 4, 8, 16, etc.

[0168] As an implementation, the fifth selection circuit 21 includes a ninth multiplexer MUX9 and a tenth multiplexer MUX10, and the fifth control signal includes a ninth selection signal SEL9 and a tenth selection signal SEL10. The input end of the ninth multiplexer MUX9 receives at least one analog signal DSPA-DSPZ, and when the control end of the ninth multiplexer MUX9 receives the ninth selection signal SEL9, the ninth multiplexer MUX9 selects an analog signal PMUX according to the ninth selection signal SEL9, and outputs the analog signal PMUX to the tenth multiplexer MUX10 through the output end of the ninth multiplexer MUX9.

[0169] The input end of the tenth multiplexer MUX10 is connected to the output end of the ninth multiplexer MUX9, and the input end of the tenth multiplexer MUX10 is also used to receive the reference signal DSVREF. The output end of the tenth multiplexer MUX10 serves as the output end of the fifth selection circuit 21. When the control end of the tenth multiplexer MUX10 receives the tenth selection signal SEL10, the tenth multiplexer MUX10 selects a signal from the analog signal PMUX and the reference signal DSVREF according to the tenth selection signal SEL10 as the first analog signal, and outputs the first analog signal through the output end of the tenth multiplexer MUX10.

[0170] The sixth selection circuit 22 includes an eleventh multiplexer MUX11 and a twelfth multiplexer MUX12, and the sixth control signal includes an eleventh selection signal SEL11 and a twelfth selection signal SEL12. The input end of the eleventh multiplexer MUX11 receives at least one analog signal DSNA-DSNZ, and when the control end of the eleventh multiplexer MUX11 receives the eleventh selection signal SEL11, the eleventh multiplexer MUX11 selects an analog signal NMUX according to the eleventh selection signal SEL11, and outputs it to the twelfth multiplexer MUX12 through the output end of the eleventh multiplexer MUX11.

[0171] The input end of the twelfth multiplexer MUX12 is connected to the output end of the eleventh multiplexer MUX11, and the input end of the twelfth multiplexer MUX12 is also used to receive the reference signal DSVREF. The output end of the twelfth multiplexer MUX12 serves as the output end of the sixth selection circuit 22. When the control end of the twelfth multiplexer MUX12 receives the twelfth selection signal SEL12, the twelfth multiplexer MUX12 selects a signal from the analog signal NMUX and the reference signal DSVREF according to the twelfth selection signal SEL12 as the second analog signal, and outputs the second analog signal through the output end of the twelfth multiplexer MUX12.

[0172] For example, the reference signal DSVREF may include a high voltage reference signal DSVREFH, a low voltage reference signal DSVREFL, and a preset voltage reference signal DSVREFX, and the preset voltage may be determined according to actual conditions. The high voltage here may be a voltage greater than a preset value, and the low voltage may be a voltage lower than a preset value, and the preset value may be determined according to actual conditions.

[0173] In some examples, such as Fig. 9 As shown, the sampler 20 also includes a thirteenth multiplexer MUX13. The input end of the thirteenth multiplexer MUX13 receives reference signals of different voltages, for example, including 3 / 4DSVREFH, 1 / 2DSVREFH, 1 / 4DSVREFH, etc. The output end of the thirteenth multiplexer MUX13 is connected to the input end of the tenth multiplexer MUX10 and the input end of the twelfth multiplexer MUX12. When the control end of the thirteenth multiplexer MUX13 receives the thirteenth selection signal SEL13, the thirteenth multiplexer MUX13 can select a reference signal with a certain voltage value according to the thirteenth selection signal SEL13, and output it to the tenth multiplexer MUX10 and the twelfth multiplexer MUX12 through the output end of the thirteenth multiplexer MUX13. Among them, the reference signals of different voltages received by the thirteenth multiplexer MUX13 can be generated by the bias voltage generating circuit.

[0174] In some embodiments, in order to further reduce the sampling frequency, such as Fig.10As shown, the analog-to-digital converter further includes a shift circuit 60, the input end of which is connected to the output end of the filter 30. The shift circuit 60 is used to select valid data bits for the digital signal of each clock cycle output by the filter 30, and output the data bits after the valid data bits are selected.

[0175] For example, the shift length range is adjustable, and the shift length LEN calculation formula is:

[0176] LEN = ceil[log2(D)X]

[0177] Where D is the filter 30 decimation factor, X is the number of cascades, and ceil is rounded up.

[0178] As a way to achieve this, Fig.10 As shown, a fourth control switch 2039 can be set between the input end of the filter 30 and the output end of the shift circuit 60. The first end of the fourth control switch 2039 is connected to the input end of the filter 30, and the second end of the fourth control switch 2039 is connected to the output end of the shift circuit 60. The fourth control switch 2039 is used to control whether the filter 30 and the shift circuit 60 are working. For example, when the fourth control switch 2039 is in the on state, the filter 30 and the shift circuit 60 are working, and when the fourth control switch 2039 is in the off state, the filter 30 and the shift circuit 60 are not working.

[0179] In some embodiments, to further reduce the data output rate, such as Fig.10 As shown, the analog-to-digital converter includes an integrator 50 that integrates result values ​​generated during a defined integration window by adding a configurable number of values ​​to construct a final result value, which can further reduce the data output rate.

[0180] In some embodiments, Fig.11 As shown, the modulator 40 includes an integration circuit 2021, a quantization circuit 2022, and a feedback conversion circuit 2023. The input end of the integration circuit 2021 is used as the input end of the modulator 40 to receive the analog signal Vin; the input end of the quantization circuit 2022 is connected to the output end of the integration circuit 2021, and the output end of the quantization circuit 2022 is used as the output end of the modulator 40 to output a digital signal, such as N bit data; the input end of the feedback conversion circuit 2023 is connected to the output end of the quantization circuit 2022, and the output end of the feedback conversion circuit 2023 is connected to the input end of the integration circuit 2021. Based on this, the modulator 40 can realize the conversion of analog signals to digital signals.

[0181] The integration circuit 2021 is used to integrate the difference between the analog signal received in the current clock cycle and the feedback signal, and output the integrated signal to the quantization circuit 2022; the quantization circuit 2022 is used to convert the analog signal received in the current clock cycle into a digital signal, and output the digital signal; the feedback conversion circuit 2023 is used to convert the digital signal received in the current clock cycle into a feedback signal, and output the feedback signal to the integration circuit 2021, wherein the digital signal received by the feedback conversion circuit 2023 in the current clock cycle is the digital signal output by the quantization circuit 2022 in the previous clock cycle.

[0182] For example, the integration circuit 2021 may include a subtraction unit 2024 and an integration unit 2025, the input end of the subtraction unit 2024 serves as the input end of the integration circuit 2021, the output end of the subtraction unit 2024 is connected to the input end of the integration unit 2025, and the output end of the integration unit 2025 serves as the output end of the integration circuit 2021. The subtraction unit 2024 is used to subtract the analog signal received in the current clock cycle from the feedback signal, and output the difference signal to the integration unit 2025, and the integration unit 2025 integrates the difference signal and outputs the integrated signal to the quantization circuit 2022.

[0183] It should be noted that quantization will cause quantization noise. When the quantization circuit 2022 is multi-bit quantization, the quantization signal-to-noise ratio SNR is:

[0184] SNR=1.76+log(SOR)+6.02N

[0185] Where N is the number of quantization bits and OSR is the oversampling rate.

[0186] According to the quantization signal-to-noise ratio formula, the signal-to-noise ratio increases by 6.02 dB for each increase in the number of quantization bits. The quantization circuit 2022 may include an N-bit quantizer (N-bit analog-to-digital converter), and the signal-to-noise ratio may be improved by the N-bit quantizer. In practical applications, considering that multi-bit quantization will increase the complexity of the design of the post-stage filter 30 circuit and increase the area of ​​the digital circuit, the design may be combined with the engineering linearity requirements to reasonably select the number of quantization bits.

[0187] In some embodiments, considering that the digital signal is highly quantized and has quantization noise, the analog-to-digital converter also includes a filter 30, the input end of the filter 30 is connected to the output end of the modulator 40, and the filter 30 can filter the digital signal output by the modulator 40 to reduce the quantization noise, and output a signal after filtering the digital signal output by the modulator 40.

[0188] In addition, in order to achieve high-resolution conversion and reduce the amount of data and computational complexity, the filter 30 can also be used to reduce the sampling frequency. The attenuation and delay properties are determined by the configuration of the filter 30, and the original data samples are extracted at a configurable rate for downsampling.

[0189] Among them, the filter 30 can be a cascade integrator comb (CIC) filter 30, which can provide basic filtering functions and a decimation function with a configurable decimation rate. Different decimation factors can be set to reduce the data output rate, reduce the signal frequency to near the Nyquist frequency, and finally output the required multi-bit digital signal.

[0190] In some embodiments, a third control switch 2038 can be set between the filter 30 and the modulator 40, and the third control switch 2038 is used to control whether the filter 30 is working. For example, when the third control switch 2038 is in the on state, the filter 30 works to process the digital signal output by the modulator 40. When the third control switch 2038 is in the off state, the filter 30 does not work.

[0191] An embodiment of the present application also provides a control system for a motor, comprising the above-mentioned analog-to-digital converter.

[0192] An embodiment of the present application also provides a vehicle, including a vehicle drive system, wherein the vehicle drive system includes a motor and a control system of the motor.

[0193] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A trigger, characterized in that: The triggers include: a first selection circuit, wherein an input end of the first selection circuit receives a plurality of first peripheral trigger signals and an output end thereof outputs a second peripheral trigger signal; the second peripheral trigger signal is one of the plurality of first peripheral trigger signals; A second selection circuit, wherein a first input end of the second selection circuit is connected to an output end of the first selection circuit, a second input end of the second selection circuit receives at least one third peripheral trigger signal, and outputs an enable signal from an output end.

2. The trigger according to claim 1, wherein: The first selection circuit is further provided with a control end, and the control end of the first selection circuit receives a first selection signal, and the first selection signal is used to represent the selected first peripheral trigger signal.

3. The trigger according to claim 2, characterized in that The first selection circuit includes a first multiplexer, which is provided with multiple input terminals. One input terminal of the first multiplexer receives a first peripheral trigger signal, and a control terminal of the first multiplexer receives the first selection signal. The first multiplexer is used to select one of at least one of the first peripheral trigger signals as the second peripheral trigger signal output.

4. The trigger according to claim 1, wherein: The second selection circuit further includes a first output terminal and a second output terminal, and the enable signal includes a first enable signal and a second enable signal; The first output terminal outputs a first enable signal, and the second output terminal outputs a second enable signal.

5. The trigger according to claim 4, characterized in that The second selection circuit includes a first control terminal, the first control terminal of the second selection circuit receives a second selection signal, and the second selection signal is used to control the output signal of the first output terminal of the second selection circuit.

6. The trigger according to claim 5, characterized in that The second selection circuit includes a second control terminal, the second control terminal of the second selection circuit receives a third selection signal, and the third selection signal is used to control the output signal of the second output terminal of the second selection circuit.

7. The trigger according to claim 6, characterized in that The second selection circuit includes a second multiplexer, a first input terminal of the second multiplexer receives the second peripheral trigger signal, a second input terminal of the second multiplexer receives at least one third peripheral trigger signal, a first control terminal of the second multiplexer receives a second selection signal, a second control terminal of the second multiplexer receives a third selection signal, a first output terminal of the second multiplexer outputs the first enable signal, and a second output terminal of the second multiplexer outputs the second enable signal.

8. The trigger according to claim 1, wherein: The second selection circuit further includes a third input terminal, the third input terminal of the second selection circuit receives an internal trigger signal, and the enable signal is one of the second peripheral trigger signal, the internal trigger signal, and at least one of the third peripheral trigger signal.

9. The trigger according to claim 8, wherein: The second selection circuit further includes a first output terminal and a second output terminal, and the enable signal includes a first enable signal and a second enable signal; The first output terminal outputs a first enable signal, and the second output terminal outputs a second enable signal.

10. The trigger according to claim 9, wherein: The first enable signal is one of the second peripheral trigger signal, at least one internal trigger signal, and at least one third peripheral trigger signal.

11. The trigger according to claim 10, characterized in that The second enable signal is one of the second peripheral trigger signal, at least one internal trigger signal, and at least one third peripheral trigger signal.

12. The trigger according to claim 9, wherein: The second selection circuit includes a first control terminal. The first control terminal of the second selection circuit receives a fourth selection signal. The fourth selection signal is used to control an output signal of a first output terminal of the second selection circuit.

13. The trigger according to claim 12, wherein: The second selection circuit includes a second control terminal, the second control terminal of the second selection circuit receives a fifth selection signal, and the fifth selection signal is used to control the output signal of the second output terminal of the second selection circuit.

14. The trigger according to claim 13, wherein: The second selection circuit includes: a third multiplexer; The third multiplexer is provided with a plurality of input terminals, one of the input terminals of the third multiplexer receives the second peripheral trigger signal, and the remaining input terminals of the third multiplexer receive the third peripheral trigger signal in a one-to-one correspondence; The first control end of the third multiplexer receives the first selection sub-signal, and the first output end of the third multiplexer outputs a fourth peripheral trigger signal under the control of the first selection sub-signal, wherein the fourth peripheral trigger signal is used to generate the first enable signal, and the fourth peripheral trigger signal is one of the second peripheral trigger signal and at least one third peripheral trigger signal.

15. The trigger according to claim 14, characterized in that The second control end of the third multiplexer receives the second selection sub-signal, and the third multiplexer outputs a fifth peripheral trigger signal at the second output end under the control of the second selection sub-signal, wherein the fifth peripheral trigger signal is used to generate the second enable signal, and the fifth peripheral trigger signal is one of the second peripheral trigger signal and at least one third peripheral trigger signal.

16. The trigger according to claim 14, wherein: The second selection circuit also includes a fourth multiplexer, a first input end of the fourth multiplexer receives an internal trigger signal, a second input end of the fourth multiplexer is connected to the output end of the third multiplexer, a control end of the fourth multiplexer receives a third selection sub-signal, and an output end of the fourth multiplexer outputs the first enable signal.

17. The trigger according to claim 14, wherein: The second selection circuit also includes a fifth multiplexer, a first input end of the fifth multiplexer receives an internal trigger signal, a second input end of the fifth multiplexer is connected to the output end of the third multiplexer, a control end of the fifth multiplexer receives a fourth selection sub-signal, and an output end of the fifth multiplexer outputs the second enable signal.

18. The trigger according to claim 17, wherein: The internal trigger signal received by the fourth multiplexer is different from the internal trigger signal received by the fifth multiplexer.

19. The trigger according to claim 16, wherein: The second selection circuit further includes a first switch connected between the first output terminal of the third multiplexer and the second input terminal of the fourth multiplexer, and a control terminal of the first switch further receives a first control signal.

20. The trigger according to claim 17, wherein: The second selection circuit further includes a second switch connected between the first output terminal of the third multiplexer and the second input terminal of the fifth multiplexer, and a control terminal of the second switch further receives a second control signal.

21. The trigger according to any one of claims 1 to 20, characterized in that: The enable signal is an enable signal of the analog-to-digital converter.

22. The trigger according to claim 21, wherein: The first enable signal is an enable signal of an integrator in the analog-to-digital converter, and the second enable signal is an enable signal of a modulator in the analog-to-digital converter.

23. The trigger according to any one of claims 1 to 20, characterized in that: The first peripheral trigger signal is at least one of a timer trigger signal, a pulse width modulation trigger signal, a successive approximation analog-to-digital converter trigger signal, a comparator trigger signal, a general input and output trigger signal, a general timer trigger signal and a system control unit trigger signal.

24. The trigger according to claim 23, wherein: The second peripheral trigger signal is a pin trigger signal.

25. The trigger according to claim 24, wherein: Internal trigger signals include start trigger signal and immediate enable trigger signal.

26. A filter, characterized in that include: a third selection circuit and at least one first filtering circuit, The input end of the third selection circuit is used to receive a digital signal, and the input end of each of the first filter circuits is connected to the output end of the third selection circuit; The first filtering circuit is used to filter the received signal; the third selection circuit is used to adjust the number of the first filtering circuits involved in filtering.

27. The filter according to claim 26, characterized in that A plurality of first filter circuits are connected in cascade, and the third selection circuit is provided with a plurality of output terminals, one of which is connected to an input terminal of a first filter circuit.

28. The filter according to claim 26, characterized in that The control end of the third selection circuit receives a sixth selection signal, and the sixth selection signal is used to select an output end from a plurality of output ends to output the digital signal.

29. The filter according to claim 28, characterized in that The third selection circuit includes a sixth multiplexer, an input end of the sixth multiplexer receives the digital signal, an output end of the sixth multiplexer is connected to an input end of a first filter circuit, and a control end of the sixth multiplexer receives the sixth selection signal.

30. The filter according to any one of claims 26 to 29, characterized in that The first filtering circuit includes a first integrating circuit and a first comb circuit; The output end of the first integration circuit is connected to the input end of the first comb circuit, and the input end of each first integration circuit is connected to the output end of the third selection circuit.

31. The filter according to claim 30, characterized in that Each of the first integration circuits (2033) outputs a signal that is a sum of a digital signal received in a current clock cycle and a digital signal received in a previous clock cycle; Each of the first comb circuits outputs a signal obtained by subtracting a digital signal received in a current clock cycle from a digital signal received in the previous N clock cycles.

32. The filter according to claim 28, wherein The filter further includes a first extraction circuit, the input end of the first extraction circuit is connected to the output end of the first filtering circuit of the last stage, and the output end of the first extraction circuit is connected to an output end of the third selection circuit.

33. The filter according to claim 32, characterized in that The first extraction circuit is used to extract a digital signal of a partial clock cycle, and the extraction clock cycle of the first extraction circuit is N, where N is an integer greater than 1.

34. The filter according to claim 26, wherein The filter further includes a fourth selection circuit and at least one second filtering circuit; The input end of the fourth selection circuit is connected to the output end of the first filter circuit of the last stage, and the input end of each of the second filter circuits is connected to the output end of the fourth selection circuit; The second filtering circuit is used to filter the input signal; and the fourth selection circuit is used to adjust the number of the second filtering circuits involved in filtering.

35. The filter according to claim 34, characterized in that A plurality of second filter circuits are connected in cascade, and the fourth selection circuit is provided with a plurality of output terminals, one of which is connected to an input terminal of a second filter circuit.

36. The filter according to claim 35, characterized in that The control end of the fourth selection circuit receives a seventh selection signal, and the seventh selection signal is used to select an output end from a plurality of output ends to output a signal.

37. The filter according to claim 34, characterized in that The filter further includes a second extraction circuit, an input end of the second extraction circuit is connected to the output end of the first filter circuit of the last stage, and an input end of the fourth selection circuit is connected to the output end of the second extraction circuit.

38. The filter according to claim 37, characterized in that The second extraction circuit is used to extract a digital signal of a partial clock cycle.

39. The filter according to claim 34, characterized in that The fourth selection circuit includes a seventh multiplexer; An output end of the seventh multiplexer is connected to an input end of a second filter circuit, a control end of the seventh multiplexer receives a seventh selection signal, and an output end of the seventh multiplexer is also connected to an output end of the second filter circuit of the last stage.

40. The filter according to claim 34, wherein The first filtering circuit includes a second integrating circuit, and the second filtering circuit includes a second comb circuit.

41. The filter according to claim 40, characterized in that Each of the second integration circuits outputs a signal that is a sum of a digital signal received in a current clock cycle and a digital signal received in a previous clock cycle; Each of the second comb circuits outputs a signal obtained by subtracting a digital signal received in a current clock cycle from a digital signal received in a previous clock cycle.

42. A filter, characterized in that The filter comprises: a first filtering circuit, wherein an input end of the first filtering circuit receives a digital signal and filters the digital signal; a second extraction circuit, wherein an input end of the second extraction circuit is connected to an output end of the first filter circuit, and the second extraction circuit is used to extract part of the digital signal; A second filtering circuit, wherein an input end of the second filtering circuit is connected to an output end of the second extraction circuit to receive the digital signal, and the second filtering circuit filters the received digital signal.

43. The filter according to claim 42, characterized in that There are multiple first filter circuits and multiple second filter circuits; A plurality of the first filter circuits are cascaded to form at least one first filter circuit group, a plurality of the second filter circuits are cascaded to form at least one second filter circuit group, and the second extraction circuit is arranged between the first filter circuit group and the second filter circuit group.

44. The filter according to claim 43, characterized in that The first filtering circuit includes: second integration circuits, each of the second integration circuits is configured to output a signal that is a sum of a digital signal received in a current clock cycle and a digital signal received in a previous clock cycle; The second extraction circuit is used to extract a digital signal of a partial clock cycle; The second filtering circuit includes second comb circuits, and each of the second comb circuits is used to output a signal obtained by subtracting a digital signal received in a current clock cycle from a digital signal received in a previous clock cycle.

45. An analog-to-digital converter, characterized in that Comprising a trigger as claimed in any one of claims 1 to 25.

46. ​​The analog-to-digital converter according to claim 45, wherein: The analog-to-digital converter further includes a modulator, an enable terminal of the modulator is connected to the trigger, and the trigger outputs an enable signal to the modulator.

47. The analog-to-digital converter according to claim 46, wherein: The analog-to-digital converter further comprises a filter as claimed in any one of claims 26 to 41, wherein an input end of the filter is connected to an output end of the modulator.

48. The analog-to-digital converter according to claim 47, wherein: The analog-to-digital converter further includes an integrator, wherein an input end of the integrator is connected to an output end of the modulator, and an enable end of the integrator is connected to the trigger.

49. A motor control system, characterized in that: An analog-to-digital converter comprising the analog-to-digital converter of any one of claims 45 to 48.

50. A vehicle, characterized in that: A power system for a vehicle is provided, the power system comprising a motor body and a control system for the motor as claimed in claim 49.

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