Decoding method and device, electronic equipment and computer readable medium

Abstract

The invention provides a decoding method. The decoding method comprises the following steps: determining N unreliable positions in to-be-decoded data; m initial test sequences are determined according to the N unreliable bits, and the number of bits of the initial test sequences is N; p final test sequences are selected from the M initial test sequences according to the initial parity check bits, M is larger than P, the initial parity check bits are parity check bits corresponding to the first initial test sequence, and the P final test sequences comprise the P initial test sequences with the parity check bits being 1; and decoding the data to be decoded by using the P final test sequences. The invention further provides a decoding device, electronic equipment and a computer readable medium.

Description

Technical Field

[0001] The present disclosure relates to the field of communications, and in particular, to a decoding method, a decoding device, an electronic device, and a computer-readable medium. Background Art

[0002] In the field of communications, forward error correction code (FEC) can ensure the credibility of communication signals and achieve reliable transmission over long distances. The principle of FEC is to encode and preprocess the signal (data payload) to be processed according to a certain algorithm, add redundant codes (code block data for error correction) with the characteristics of the data payload itself, and send it to the transmission channel. Then, at the receiving end, the data is decoded according to the corresponding algorithm, the errors are found and corrected, and the original data payload is restored. FEC effectively resists the interference caused by the transmission channel at a very small cost of Over Head (the ratio of redundant code to payload is called overhead, abbreviated as OH), improves the reliability of the communication system, extends the transmission distance of the communication signal, and reduces the cost of the communication system.

[0003] When FEC is decoding, the error rate (SER, Symbol Error Rate) must be within the correctable range before the error can be corrected and the original payload data can be restored. For example, if N bits of payload are input, K bits of redundant code are generated according to the relevant algorithm, and then (N+K) bits of data are sent to the receiving end. During the transmission process, the payload and redundant code are easily affected by environmental factors and cause errors. If the error is within the correctable range, the receiving end can correct the error and restore the N bits of payload data after decoding. Hamming decoding uses FEC technology, and a large number of test sequences are required during decoding, which reduces the decoding efficiency. Summary of the invention

[0004] The embodiments of the present disclosure provide a decoding method, a decoding device, an electronic device and a computer-readable medium.

[0005] As a first aspect of the present disclosure, a decoding method is provided, comprising:

[0006] Determine N unreliable positions in the data to be decoded; determine M initial test sequences according to the N unreliable positions, wherein the number of bits of the initial test sequences is N; select P final test sequences from the M initial test sequences according to the initial parity check bits, wherein M>P, the initial parity check bits are the parity check bits corresponding to the first initial test sequence, and the P final test sequences include the P initial test sequences whose parity check bits are 1; and use the P final test sequences to decode the data to be decoded.

[0007] As a second aspect of the present disclosure, a decoding device is provided, comprising:

[0008] An unreliable position determination module, used to determine N unreliable positions in the data to be decoded;

[0009] A test sequence selection module, used to determine M initial test sequences according to N unreliable positions, and select P final test sequences from the M initial test sequences according to initial parity check bits, wherein the number of bits of the initial test sequences is N, M>P, the initial parity check bit is the parity check bit corresponding to the first initial test sequence, and the P final test sequences include the P initial test sequences whose parity check bits are 1;

[0010] A decoding module is used to decode the data to be decoded using the P final test sequences.

[0011] As a third aspect of the present disclosure, an electronic device is provided, including:

[0012] one or more processors;

[0013] A memory having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, the one or more processors implement the decoding method provided in the first aspect of the present disclosure.

[0014] As a fourth aspect of the present disclosure, a computer-readable medium is provided, on which a computer program is stored, and when the program is executed by a processor, the decoding method provided in the first aspect of the present disclosure is implemented.

[0015] In the decoding method provided in the present disclosure, an initial test sequence corresponding to a parity check bit of 1 is used as a final test sequence to decode the data to be decoded, thereby reducing the number of test sequences required in the decoding process, saving decoding resources, and simplifying the decoding method. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flowchart of an implementation method of the decoding method provided by the present disclosure;

[0017] Figure 2 is a flowchart of an implementation method of step S140;

[0018] Figure 3 is a flowchart of another implementation of the decoding method provided by the present disclosure;

[0019] Figure 4 It is a module schematic diagram of an implementation mode of the decoding device provided by the present disclosure;

[0020] Figure 5is a module schematic diagram of an implementation mode of an electronic device provided by the present disclosure;

[0021] Figure 6 It is a module diagram of the computer-readable medium provided by the present disclosure. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the decoding method, decoding device, electronic device and computer-readable medium provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0023] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0024] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0025] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0026] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0028] As a first aspect of the present disclosure, a decoding method is provided, such as Figure 1 As shown, the decoding method includes:

[0029] In step S110, N unreliable positions in the data to be decoded are determined;

[0030] In step S120, M initial test sequences are determined according to the N unreliable positions;

[0031] In step S130, P final test sequences are determined from M initial test sequences according to the initial parity bits;

[0032] In step S140, the to-be-decoded data are decoded using the P final test sequences.

[0033] In the present disclosure, M, N, and P are all positive integers, and M>P. The initial parity bit is the parity bit corresponding to the first initial test sequence, and the P final test sequences include P initial test sequences whose parity bits are 1.

[0034] In the present disclosure, the number of bits of the initial test sequence is N, which means that the number of bits of the final test sequence is also N. For the convenience of description, the initial test sequence and the final test sequence are collectively referred to as the test sequence, that is, the number of bits of the test sequence is N, and the N numbers in the test sequence correspond to N unreliable positions in the data to be decoded. 0 in the test sequence indicates that the bit at the corresponding position in the data to be decoded is not flipped, and 1 in the test sequence indicates that the bit at the corresponding position in the data to be decoded is flipped.

[0035] "Parity check" is a method of checking the correctness of code transmission. It is checked based on whether the number of "1" bits in a set of binary codes being transmitted is odd or even. From the algorithm, it can be seen that if the parity bit is 0, it means there is no error or there is more than one error. In the case where decoding is not required, there will be corresponding adjacent test sequences that complete the error correction output with the same result. In this case, the test sequence corresponding to "parity check bit is 0" is useless, so there is no need to put it in the test sequence for comparison. If there are multiple errors before flipping according to the test sequence, some errors can be corrected by soft decision (described below).

[0036] In the decoding method provided in the present disclosure, an initial test sequence corresponding to a parity check bit of 1 is used as a final test sequence to decode the data to be decoded, thereby reducing the number of test sequences required in the decoding process, saving decoding resources, and simplifying the decoding method.

[0037] In the present disclosure, the parity bits corresponding to the remaining M-1 initial test sequences can be determined according to the value of the initial parity bit, the data to be decoded, and M initial test sequences.

[0038] The “unreliable positions” mentioned above refer to the positions most likely to cause errors. The number of the positions most likely to cause errors in the data to be decoded and the corresponding positions can be determined according to a predetermined algorithm.

[0039] In the present disclosure, the specific value of P is related to N and the value of the initial parity bit.

[0040] For example, when the number of bits of the data to be decoded is 128, the number of unreliable positions is 6 (ie, N=6), the number of bits of each initial test sequence is 6, and the number M of initial test sequences is 42.

[0041] In the present disclosure, the initial parity bit can be determined by the data to be decoded and the first group of test sequences.

[0042] When the initial parity check bit is 1, an initial test sequence that needs to flip at least one bit in the to-be-decoded data whose bit number satisfies formula (1) is used as the final test sequence.

[0043] When the initial parity bit is 0, an initial test sequence that needs to flip at least one bit in the to-be-decoded data whose bit number satisfies formula (2) is used as the final test sequence.

[0044] S = 2i + 1 (1);

[0045] S = 2i (2);

[0046] Wherein, i is an integer and i≥0.

[0047] For example, when the initial parity bit is 1, an initial test sequence that needs to flip at least one of the first bit, the third bit, the fifth bit, ..., in the to-be-decoded data is used as the final test sequence.

[0048] In the case where the initial parity bit is 0, an initial test sequence that requires flipping one of the 0th bit, the 2nd bit, the 4th bit, ..., in the to-be-decoded data is used as the final test sequence.

[0049] In the present disclosure, step S140 is not particularly limited. As an optional implementation, Figure 2 As shown, step S140 may include:

[0050] In step S141, P groups of syndromes are generated according to the P final test sequences of the data to be decoded;

[0051] In step S142, the to-be-decoded data is decoded according to the P groups of syndromes.

[0052] The value of P is related to N and the initial parity bit. When the initial parity bit is 1, In the case where the initial parity bit is 0, Wherein, j is an integer.

[0053] Since the number of syndromes is different when the initial parity bit is 0 or 1, zero padding may be performed in step S142 in order to obtain a uniform output format.

[0054] As a possible implementation, the number of final test sequences obtained when the initial parity bit is 1 (for ease of description, it is assumed that when the initial parity bit is 1, P=A1) is greater than the number of final test sequences obtained when the initial parity bit is 0 (for ease of description, it is assumed that when the initial parity bit is 0, P=A2). In order to make the output format uniform, in step S142, the supplementary syndrome of the (A1-A2) group of all zeros is supplemented.

[0055] In the present disclosure, there is no special limitation on how to specifically perform step S142. Optionally, step S142 may include:

[0056] Determine the initial error position of the syndrome of group P;

[0057] Determine a target error position according to the correlation difference of the test sequence of group P and the initial error position;

[0058] Flipping the bit located at the target error position in the data to be decoded to obtain an initial decoding result;

[0059] The initial decoding results are reversed and the check bits are removed to obtain the final decoding results.

[0060] It should be pointed out that the “check bit” here includes both the parity check bit and other check bits besides the parity check bit.

[0061] In the present disclosure, the value of N is related to the number of bits of the data to be decoded, and the value of M is related to the value of N.

[0062] As an optional implementation, the number of bits of the data to be decoded is 128, in which case N = 6. That is, there are 6 unreliable positions in the data to be decoded, and the data at these 6 unreliable positions are most likely data with flip errors.

[0063] Correspondingly, when the initial parity bit is 1, an initial test sequence that needs to flip at least one of the first bit, the third bit, and the fifth bit in the to-be-decoded data is used as the final test sequence.

[0064] In the case where the initial parity bit is 0, an initial test sequence that needs to flip one of the 0th bit, the 2nd bit, and the 4th bit in the to-be-decoded data is used as the final test sequence.

[0065] It has been confirmed that the gain after flipping 4 / 5 / 6 bits is similar to the gain after flipping only 0 / 1 / 2 / 3 bits, but the test sequence data is doubled. Optionally, only a test sequence for flipping 0 / 1 / 2 / 3 bits can be set.

[0066] That is, when N=6, M=42. When the initial parity bit is 1, the final test sequence is the initial test sequence corresponding to flipping 1 / 3 bits, and when the initial parity bit is 0, the final test sequence is the initial test sequence corresponding to flipping 0 / 2 bits.

[0067] The following briefly introduces the case where the number of bits of the data to be decoded is 128, N=6, and M=42.

[0068] Table 1 shows a schematic diagram of an implementation of a test sequence 41 (ie, the last test sequence among the 42 test sequences).

[0069] Table 1

[0070]

[0071] Since the initial parity bit (in this disclosure, represented by p_o) is known, the last set of test sequences flips 3 bits, so the parity bit corresponding to this set of test sequences (in this disclosure, represented by p41) is also located at a certain position, p41 ==~p_o. If p_o==1'b1 is input at this time, then p41==1'b0. As described above, if the parity bit is 0, it means there is no error or there is more than one error, which will result in two results: decoding failure or no decoding. If no decoding is required, there will be corresponding adjacent test sequences, such as the 37th group (corresponding to flipping the fifth unreliable position and the sixth unreliable position) to complete the error correction output of the same result. At this time, the 41st group of test sequences will not be used, so there is no need to put it into the test sequence for comparison. If there are multiple errors before the flip sequence, it may be corrected by soft decision so that the data can complete the Hamming decoding operation. In the entire Hamming soft decoding process, at most 3 bits can be changed by soft information, and 1 bit can be corrected by Hamming decoding. In the case where the initial parity bit is 0, an initial test sequence with 1 or 3 bits flipped may become the best test case (ie, the final test sequence described above).

[0072] In the case where the initial even parity bit is 1, an initial test sequence with 0 or 2 bits flipped may become the best test sequence (ie, the final test sequence described above).

[0073] Similar to the case where the initial parity bit p_o==1'b0, when the initial parity bit p_o==1'b1 is input, all initial test sequences that need to flip 1 or 3 bits do not need to participate in decoding. These test sequences are the first group, the second group, the fourth group, the seventh group, the eighth group, the eleventh group, the thirteenth group, the fourteenth group, the fifteenth group, the eighteenth group, the twentieth group, the twenty-first group, the twenty-third group, the twenty-fourth group, the twenty-fifth group, the twenty-sixth group, the twenty-ninth group, the thirty-first group, the thirty-second group, the thirty-fourth group, the thirty-fifth group, the thirty-sixth group, the thirty-eighth group, the thirty-ninth group, the fortieth group and the forty-first group, a total of 26 test sequences. The above 26 test sequences are only needed when the initial value p_o==1'b0. In the case of the initial parity bit p_o==1'b1, the remaining 16 groups of initial test sequences starting with the zeroth group are needed as the final test sequences. In the subsequent decoding process, which group of final test sequences will be used depends only on the input initial parity bit in addition to the order of the final test sequences themselves. The final test sequence can be selected from multiple groups of initial test sequences based on the initial parity bit. In the subsequent decoding, the corresponding syndromes that need to be found for the error position are reduced from 42 to 26 (including 16 groups of initial syndromes obtained from 16 groups of final test sequences and 10 groups of supplementary syndromes), saving table lookup resources. In the subsequent decoding steps based on syndromes, the amount of data that needs to calculate the minimum Euclidean distance and the number of minimum values ​​to be found are also reduced.

[0074] In summary, no matter what the value of the initial parity bit is, there will always be a part of the initial test sequence that cannot become the final test sequence. That is to say, in the present disclosure, the test sequence can be optimized from the initial 42 groups to 26 groups, and the effect of resource optimization is quite obvious.

[0075] As mentioned above, if the parity bit is 0, it means there is no error or there is more than one error. In the present disclosure, the errors of the data to be decoded cannot be too many. Figure 3 As shown, before determining N unreliable positions in the data to be decoded, the decoding method further includes:

[0076] In step S100, soft decoding is used to correct errors in the initial data to obtain the data to be decoded, wherein the error of the data to be decoded is no more than 3 bits.

[0077] In the present disclosure, the initial data needs to be subjected to 1-bit error correction and have a parity bit.

[0078] As a second aspect of the present disclosure, a decoding device is provided, comprising:

[0079] An unreliable position determination module, used to determine N unreliable positions in the data to be decoded;

[0080] A test sequence selection module 410 is used to determine M initial test sequences according to the N unreliable positions, and select P final test sequences from the M initial test sequences according to the initial parity check bits, wherein the number of bits of the initial test sequences is N, M>P, the initial parity check bits are the parity check bits corresponding to the first initial test sequence, and the P final test sequences include the P initial test sequences whose parity check bits are 1;

[0081] The decoding module 420 is configured to decode the data to be decoded using the P final test sequences.

[0082] The decoding device is used to execute the decoding method provided by the first aspect of the present disclosure. The working principle and beneficial effects of the decoding method have been described in detail above and will not be repeated here.

[0083] exist Figure 4 In the embodiment shown in , the test sequence selection module 410 includes the following modules:

[0084] Soft and hard separation module bch_decode_syndrome, unreliable position determination module find_6min, test sequence generation module bch_decode_syndrome_ext.

[0085] The soft-hard separation module bch_decode_syndrome corresponds to the emphasis on sorting function, and calculates the absolute value of soft information (dehaming_abs), hard judgment result (y0), initial syndrome (s_origin), initial parity bit (p_origin) and decoding early exit signal (s_p_flag) for the received data. In other words, the soft-hard separation module bch_decode_syndrome separates the input soft and hard information, and determines whether it is necessary to exit early based on the hard information.

[0086] The unreliable position determination module find_6min mainly implements the soft decoding function, finds the 6 most unreliable positions in the 128-bit data according to the soft information, and outputs the addresses of the corresponding hard bits.

[0087] The test sequence generation module bch_decode_syndrome_ext calculates the final test sequence of the flipped bits to implement the soft decoding function.

[0088] The decoding module 420 may include a hard decoding module bch_decode_pn and a best finding module find_best.

[0089] The hard decoding module bch_decode_pn completes the table lookup of the s signal and outputs the hard bit error position corresponding to each final test sequence to realize the hard decoding function.

[0090] The best search module find_best finds the best flip position and reverses it according to the output result of the err_pn signal, compares the correlation differences of all test sequences and finds the best result, and finally outputs it after reverse sorting and removing the parity bit.

[0091] Since the initial check bit p_o input to the bch_decode_syndrome module is known, the last set of test sequences flips 3 bits, so the check bit corresponding to this set of test sequences is also located at a certain position, p41==~p_o. If the input p_o==1'b1 at this time, then p41==1'b0. It can be seen from the algorithm that if the parity bit is 0, it means there is no error or there is more than one error. At this time, the decoding will definitely fail or no decoding is required. If no decoding is required, there will be a corresponding adjacent test sequence, such as the 37th group (corresponding to flipping the fifth unreliable position and the sixth unreliable position) to complete the error correction output of the same result. At this time, the 41st group of test sequences will not be used at all, so there is no need to put it into the test sequence for comparison. If there are multiple errors before the flip sequence, it may be corrected by soft decision so that the data can complete the Hamming decoding operation. In the entire Hamming soft decoding process, at most three bits can be changed by soft information, and 1 bit can be corrected by Hamming decoding. Through the decoding device provided in the present disclosure, the test sequence can be optimized from the initial 42 groups to 26 groups, which has a significant effect on resource optimization.

[0092] Similar to the initial parity bit p_o==1'b0, when the initial parity bit p_o==1'b1 is input, all test sequences that need to flip 1 or 3 bits do not need to participate in decoding, a total of 26 test sequences, which are only needed when the initial value p_o==1'b0, otherwise the remaining 16 test sequences starting with the zeroth group are needed. Which group of test sequences will be used in subsequent modules depends only on the input initial parity bit in addition to the order of the test sequences themselves, so the output test sequence is obtained by the selector controlled by p_o. In the bch_decode_pn module, the corresponding syndromes that need to find the error position are reduced from 42 to 26, saving table lookup resources. In the find_best module, due to the simplification of the test sequence, the number of err_pn inputs is also reduced, the amount of data required to calculate the minimum Euclidean distance and the number of minimum values ​​to be found are also reduced. The optimization in the find_best module is mainly based on the reduction of the number of operations. Since the optimization of the bch_decode_syndrome module omits the judgment condition of the parity bit in the find_best module, the parity bit corresponding to the input data satisfies the condition of being equal to one. In addition, there is no update on the scheme. The synthesis after optimization shows that the count of the find_best module after optimization is 17456, and the count of the find_best module before optimization is 30234. After optimization, this module is estimated to reduce 40% of resources, which has a significant impact. Generally speaking, the larger the scale of the test sequence, the better the optimization effect will be.

[0093] As a third aspect of the present disclosure, an electronic device is provided, such as Figure 5 As shown, the electronic device includes:

[0094] One or more processors 101;

[0095] The memory 102 stores one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the decoding method provided in the first aspect of the present disclosure.

[0096] Optionally, the electronic device may further include one or more I / O interfaces 103 connected between the processor and the memory and configured to implement information interaction between the processor and the memory.

[0097] Among them, the processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU) and the like; the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 103 is connected between the processor 101 and the memory 102, and can realize information interaction between the processor 101 and the memory 102, including but not limited to a data bus (Bus) and the like.

[0098] In some embodiments, the processor 101 , the memory 102 , and the I / O interface 103 are connected to each other via a bus 104 , and further connected to other components of the computing device.

[0099] As a fourth aspect of the present disclosure, Figure 6 As shown, a computer-readable medium is provided, on which a computer program is stored, and when the program is executed by a processor, the method provided by any one of the above aspects of the present disclosure is implemented.

[0100] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0101] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A decoding method, comprising: Determining N unreliable positions in the data to be decoded; Determine M initial test sequences according to the N unreliable positions, wherein the number of bits of the initial test sequences is N; Selecting P final test sequences from M initial test sequences according to the initial parity check bit, wherein M>P, the initial parity check bit is the parity check bit corresponding to the first initial test sequence, and the P final test sequences include the P initial test sequences whose parity check bits are 1; The to-be-decoded data are decoded using the P final test sequences.

2. The decoding method according to claim 1, wherein: When the initial parity check bit is 1, an initial test sequence of at least one bit in the to-be-decoded data that needs to be flipped and whose bit number satisfies formula (1) is used as the final test sequence; In the case where the initial parity check bit is 0, an initial test sequence of at least one bit in the to-be-decoded data whose bit number satisfies formula (2) needs to be flipped as the final test sequence; S = 2i + 1 (1); S = 2i (2); Wherein, i is an integer and i≥0.

3. The decoding method according to claim 2, wherein: The step of decoding the to-be-decoded data by using the P final test sequences comprises: Generate P groups of syndromes according to the P final test sequences of the data to be decoded; The data to be decoded is decoded according to the P groups of syndromes.

4. The decoding method according to claim 3, wherein: When the initial parity bit is 1, In the case where the initial parity bit is 0, Wherein, j is an integer.

5. The decoding method according to claim 3, wherein: The decoding of the to-be-decoded data according to the M groups of syndromes comprises: Determine the initial error position of the syndrome of group P; Determine a target error position according to the correlation difference of the test sequence of group P and the initial error position; Flipping the bit located at the target error position in the data to be decoded to obtain an initial decoding result; The initial decoding results are reversed and the check bits are removed to obtain the final decoding results.

6. The decoding method according to any one of claims 1 to 4, wherein: M=42, and the 42 initial test sequences correspond to flipping the first 3 unreliable positions among the 6 unreliable positions.

7. The decoding method according to any one of claims 1 to 4, wherein: Before determining the N unreliable positions in the data to be decoded, the decoding method further includes: The initial data is corrected by using soft decoding to obtain the data to be decoded, wherein the error of the data to be decoded is no more than 3 bits.

8. A decoding device, comprising: An unreliable position determination module, used to determine N unreliable positions in the data to be decoded; A test sequence selection module, used to determine M initial test sequences according to N unreliable positions, and select P final test sequences from the M initial test sequences according to initial parity check bits, wherein the number of bits of the initial test sequences is N, M>P, the initial parity check bit is the parity check bit corresponding to the first initial test sequence, and the P final test sequences include the P initial test sequences whose parity check bits are 1; A decoding module is used to decode the data to be decoded using the P final test sequences.

9. An electronic device, comprising: one or more processors; A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the decoding method described in any one of claims 1 to 7.

10. A computer-readable medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the decoding method according to any one of claims 1 to 7.

Images