Extensible network security mainboard system

Abstract

The invention provides an extensible network security mainboard system, relates to the technical field of network security mainboards, and aims to improve the security of the system by dynamically adjusting clock signals and alternately using various encryption algorithms, so that the data encryption process is more complex and diversified, and the risk caused by a fixed encryption algorithm is reduced. Meanwhile, by flexibly adjusting the working time of the encryption unit, the parallel processing capability and the overall efficiency of the system can be improved. The dynamic clock signal and various encryption algorithms are combined, so that the system can flexibly adjust the working mode according to different interactive data, and the adaptability and flexibility of the system are improved. Besides, the number of the time sequence subunits and the number of the encryption subunits can be expanded or deleted, the expandability and applicability of the whole mainboard system are greatly improved, the overall performance of the mainboard system can be improved, the power consumption of the system is effectively reduced, and the resource utilization rate is optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of network security motherboards, and in particular to an expandable network security motherboard system. Background Art

[0002] With the rapid development of information technology and network communication technology, data security issues have become increasingly prominent, especially in network environments, where encryption security in data transmission is particularly important. Existing network security motherboard systems usually use fixed encryption algorithms to encrypt interactive data. However, fixed encryption algorithms have significant security risks. Once the encryption algorithm is cracked, the overall security of the system will be seriously threatened. In addition, when processing large amounts of interactive data, existing network security motherboard systems often have problems such as low processing efficiency and insufficient resource utilization, and are difficult to dynamically adapt to different data load conditions. Therefore, designing a network security motherboard system that can dynamically adjust the encryption algorithm and effectively improve data processing efficiency is the key to solving the problems of the prior art.

[0003] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0004] The object of the present invention is to provide an expandable network security motherboard system to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] An expandable network security motherboard system, specifically comprising:

[0007] A mainboard body, the mainboard body being electrically connected to the encryption module and the timing module, and being used to send interactive data to the encryption module, dynamically generate a clock signal according to the interactive data, and send the clock signal to the timing module;

[0008] An encryption module, which is electrically connected to the data transmission module and includes at least two groups of sub-encryption units connected in parallel, and is used to encrypt the interactive data to generate encrypted data, and send the encrypted data to the data transmission module;

[0009] A timing module, the timing module comprising at least two groups of serially connected sub-timing units, the sub-timing units being arranged corresponding to the sub-encryption units, for generating a timing signal according to a clock signal, and controlling the sub-encryption units using the timing signal;

[0010] A data transmission module, wherein the data transmission module is used to transmit encrypted data.

[0011] Preferably, the main board body includes a data output terminal and a clock signal terminal, the sub-encryption unit includes a data input terminal, a data output terminal and a chip select terminal, the sub-timing unit adopts a D trigger, including a data input terminal, a clock signal terminal and a data output terminal, and the data transmission module includes a data input terminal and a data output terminal.

[0012] Preferably, the data output terminal of the mainboard body is signal-connected to the data input terminal of each sub-encryption unit, and the data output terminal of each sub-encryption unit is signal-connected to the data input terminal of the data transmission module.

[0013] Preferably, each of the sub-timing units is numbered and arranged according to the number, the data output end and the data input end signal of two adjacent numbered sub-timing units are connected, and the data output end of each of the sub-timing units is connected to the chip select end signal of the corresponding sub-encryption unit.

[0014] Preferably, the timing module also includes a logic unit, which is an NOR gate, and the data output end of each of the sub-timing units is signal-connected to the data input end of the logic unit, and the data output end of the logic unit is signal-connected to the signal input end of the sub-timing unit with the frontmost number.

[0015] Preferably, each group of the sub-encryption units is preset with a different encryption algorithm, and the overall working logic of the mainboard system is:

[0016] The mainboard collects data information of the interactive data, and adjusts the signal period of the clock signal according to the data information of the interactive data;

[0017] The timing module generates a divided timing signal according to the adjusted clock signal, sends the timing signal to the chip selection terminal of each sub-encryption unit, and uses the timing signal to control the working status of the sub-encryption unit;

[0018] The sub-encryption unit in the working state encrypts the received interactive data to generate encrypted data, and sends the encrypted data to the data transmission module.

[0019] Preferably, the data information of the interactive data includes data number, receiving time, and data length, and the logic of adjusting the signal period of the clock signal according to the data information of the interactive data is:

[0020] Collect data information of interaction data in time period t, set observation windows based on integer multiples of time period t, generate priority numbers for each time period t in the observation window, and the duration corresponding to time period t is t';

[0021] The priority number of each time period t in the observation window is divided into three priority levels, the number and proportion of time periods t in each priority level are counted, and a signal period corresponding to the observation window is generated.

[0022] Preferably, the priority number of the time period t is calculated as follows:

[0023]

[0024] In the formula Represents the period t i The corresponding priority number, the subscript i represents the number of the time period t, i = 1, 2, 3 ... N, N represents the total number of time periods in the observation window, μ1, μ2, μ3 represent the first priority weight, the second priority weight and the third priority weight respectively, μ1 + μ2 + μ3 = 1, T j , L j Respectively represent the receiving period and data length of the jth interactive data, M i Indicates that in time period t i The number of internal interaction data;

[0025] The priority numbers of all time periods in the observation window are divided as follows:

[0026] When the priority number corresponding to the time period meets:

[0027]

[0028] Consider this period as low priority;

[0029] When the priority number corresponding to the time period meets

[0030]

[0031] This period is considered to be of medium priority;

[0032] When the priority number corresponding to the time period meets

[0033]

[0034] Consider this period as high priority;

[0035] In the formula They respectively represent the maximum and minimum values ​​of the priority numbers in all time periods within the observation window.

[0036] Preferably, the signal period is calculated as follows:

[0037]

[0038] Wherein Tz represents the signal period, α1, α2, and α3 represent the first influence weight, the second influence weight, and the third influence weight, respectively, wherein α1<α2<α3, and α1+α2+α3=1, and N(l), N(m), and N(h) represent the number of time periods with low priority, medium priority, and high priority in the observation window, respectively.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] The present invention greatly improves the security of the system by dynamically adjusting the clock signal and using multiple encryption algorithms in turn, making the data encryption process more complex and diverse, and reducing the risks brought by fixed encryption algorithms. At the same time, the generation and control of the dynamic clock signal can flexibly adjust the working time of the encryption unit, thereby improving the parallel processing capability and overall efficiency of the system. The combination of the dynamic clock signal and the multiple encryption algorithms enables the system to flexibly adjust the working mode according to different interactive data, thereby improving the adaptability and flexibility of the system. In addition, the number of sub-timing units and sub-encryption units can be expanded or deleted, which greatly improves the scalability and applicability of the overall mainboard system, helps to improve the overall performance of the mainboard system, and effectively reduces the power consumption of the system and optimizes resource utilization. These improvements significantly solve the problems of insufficient data transmission security, low processing efficiency and insufficient resource utilization in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of the circuit structure of the present invention. DETAILED DESCRIPTION

[0042] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0043] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0044] Example:

[0045] See also Figure 1 , the present invention provides a technical solution:

[0046] An expandable network security mainboard system specifically comprises: a mainboard body, an encryption module, a timing module, and a data transmission module.

[0047] The main board body is electrically connected to the encryption module and the timing module, and can adopt an i.MX series embedded integrated main board, which has multiple expandable GPIO interfaces, including a data output terminal and a clock signal terminal, which are used to send interactive data to the encryption module, dynamically generate a clock signal according to the interactive data and send it to the timing module.

[0048] The encryption module is electrically connected to the data transmission module, and includes at least two groups of parallel sub-encryption units. The AES-128 series encryption module can be used. Each group of sub-encryption units is preset with different encryption algorithms, such as AES, DES and other encryption algorithms, which are used to encrypt the interactive data to generate encrypted data and send the encrypted data to the data transmission module. The port of each sub-encryption unit includes a data input terminal, a data output terminal and a chip select terminal.

[0049] The timing module includes at least 2 groups of sub-timing units connected in series. The sub-timing units use 74HC74 series D flip-flops, including a data input terminal, a clock signal terminal and a data output terminal. The data transmission module includes a data input terminal and a data output terminal. The sub-timing units are correspondingly arranged with the sub-encryption units, and are used to generate timing signals according to the clock signals, and use the timing signals to control the sub-encryption units. The timing module also includes a logic unit, which is a 74HC02 series NOR gate. The data output terminal of each sub-timing unit is signal-connected to the data input terminal of the logic unit, and the data output terminal of the logic unit is signal-connected to the signal input terminal of the sub-timing unit with the front number.

[0050] The data output terminal of the mainboard body is connected to the data input terminal signal of each sub-encryption unit, and the data output terminal of each sub-encryption unit is connected to the data input terminal signal of the data transmission module. Each sub-timing unit is numbered and set according to the number, and the data output terminal and data input terminal signal of two adjacent sub-timing units are connected, and the data output terminal of each sub-timing unit is connected to the chip select terminal signal of the corresponding sub-encryption unit.

[0051] The data transmission module can use a serial communication chip of the FTDI FT232R series to transmit encrypted data.

[0052] It can be understood that the clock signal end in the main board body and the timing module includes two independent ports, which are respectively used to output two clock signals with opposite phases. The periodic change of the clock signal is used to control multiple groups of sub-timing units to generate high-level signals in turn, and only one of the multiple groups of sub-timing units is at a high level at the same time. The chip select end of the sub-encryption unit is started at a high level. When the timing signal corresponding to a certain sub-timing unit is high, the chip select end of the corresponding sub-encryption unit is started. The sub-encryption unit is in a working state, receives the interactive data sent by the main board body, and uses a preset encryption algorithm to encrypt and generate encrypted data, and then sends it to the data transmission module for transmission. By generating high-level signals in turn by the sub-timing units, different sub-encryption units can be selected in turn, so that the interactive data can be automatically encrypted with different encryption algorithms, which greatly improves the security of data transmission and reduces the risks brought by a single encryption algorithm. At the same time, the running time of the sub-encryption unit is equal to the high-level duration of the sub-timing unit, and the high-level duration of the sub-timing unit is controlled by the signal period of the clock signal. In other words, by adjusting the signal period of the clock signal, the running time of the sub-encryption unit can be adjusted, that is, the switching time between different encryption algorithms can be adjusted.

[0053] The overall working logic of the motherboard system is:

[0054] The mainboard collects data information of the interactive data, and adjusts the signal period of the clock signal according to the data information of the interactive data;

[0055] The timing module generates a divided timing signal according to the adjusted clock signal, sends the timing signal to the chip selection terminal of each sub-encryption unit, and uses the timing signal to control the working status of the sub-encryption unit;

[0056] The sub-encryption unit in the working state encrypts the received interactive data to generate encrypted data, and sends the encrypted data to the data transmission module.

[0057] In this step, by dynamically adjusting the clock signal and using multiple encryption algorithms in turn, the security of the system is greatly improved, making the data encryption process more complex and diverse. At the same time, the generation and control of the dynamic clock signal can flexibly adjust the working time of the encryption unit and improve the parallel processing capability and overall efficiency of the system. The combination of dynamic clock signals and multiple encryption algorithms enables the system to flexibly adjust the working mode according to different interactive data, improving the adaptability and flexibility of the system. The number of sub-timing units and sub-encryption units can be expanded or deleted, which greatly improves the overall scalability and applicability of the motherboard system and helps to improve the overall performance of the motherboard system.

[0058] The data information of the interactive data includes data number, receiving time, and data length. The logic for adjusting the signal period of the clock signal according to the data information of the interactive data is:

[0059] Collect data information of interaction data in time period t, set observation windows based on integer multiples of time period t, generate priority numbers for each time period t in the observation window, and the duration corresponding to time period t is t';

[0060] The priority number of each time period t in the observation window is divided into three priority levels, the number and proportion of time periods t in each priority level are counted, and a signal period corresponding to the observation window is generated.

[0061] The priority number of time period t is calculated as:

[0062]

[0063] In the formula Represents the period t i The corresponding priority number, the subscript i represents the number of the time period t, i = 1, 2, 3 ... N, N represents the total number of time periods in the observation window, μ1, μ2, μ3 represent the first priority weight, the second priority weight and the third priority weight respectively, μ1 + μ2 + μ3 = 1, T j , L j Respectively represent the receiving period and data length of the jth interactive data, M i Indicates that in time period t i The number of interactive data.

[0064] In this step, an example is given to illustrate that, assuming that the duration of each period is 1 hour and the observation window is 1 day, the corresponding period number is 1 to 24. When constructing the equation of the priority number, the first part considers the total number of interaction data in the period. The more interaction data there are, the larger the priority number corresponding to the period, and the total number of interaction data gradually weakens the impact of the priority number. The second part considers the average time spent receiving each interaction data in the period. This factor has the most intuitive impact on the priority number, so a linear function is used to represent it. The third part considers the total length of all interaction data in the period. It can be understood that, in general, the total length of interaction data is much larger than the total number, so a logarithmic function is used to weaken its changes, indicating its nonlinear impact on the priority number. It can be seen that the priority number reflects the overall workload of the motherboard system in a certain period of time. The higher the priority number, the greater the overall workload of the motherboard system in the period, which means that the data interaction is more frequent.

[0065] The priority numbers of all time periods in the observation window are divided as follows:

[0066] When the priority number corresponding to the time period meets:

[0067]

[0068] Consider this period as low priority;

[0069] When the priority number corresponding to the time period meets

[0070]

[0071] This period is considered to be of medium priority;

[0072] When the priority number corresponding to the time period meets

[0073]

[0074] Consider this period as high priority;

[0075] In the formula They respectively represent the maximum and minimum values ​​of the priority numbers in all time periods within the observation window.

[0076] The signal period is calculated as:

[0077]

[0078] Wherein Tz represents the signal period, α1, α2, and α3 represent the first influence weight, the second influence weight, and the third influence weight, respectively, wherein α1<α2<α3, and α1+α2+α3=1, and N(l), N(m), and N(h) represent the number of time periods with low priority, medium priority, and high priority in the observation window, respectively.

[0079] Understandably, The overall value range of this item is [0,1], and the influence of high priority, medium priority, and low priority on the signal cycle gradually weakens. In other words, when the overall data interaction of the motherboard system is more frequent and the signal cycle is shorter, the switching speed between different encryption algorithms will be faster to ensure the security of data transmission. On the contrary, when the overall data interaction of the motherboard system is less and the signal cycle is longer, the switching speed between different encryption algorithms will be slower to reduce the overall resource utilization of the motherboard system and reduce its power consumption.

[0080] In summary, the present invention greatly improves the security of the system by dynamically adjusting the clock signal and using multiple encryption algorithms in turn, making the data encryption process more complex and diverse, and reducing the risks brought by fixed encryption algorithms. At the same time, the generation and control of the dynamic clock signal can flexibly adjust the working time of the encryption unit, thereby improving the parallel processing capability and overall efficiency of the system. The combination of the dynamic clock signal and multiple encryption algorithms enables the system to flexibly adjust the working mode according to different interactive data, thereby improving the adaptability and flexibility of the system. In addition, the number of sub-timing units and sub-encryption units can be expanded or deleted, which greatly improves the scalability and applicability of the overall mainboard system, helps to improve the overall performance of the mainboard system, and effectively reduces the power consumption of the system and optimizes resource utilization. These improvements significantly solve the problems of insufficient data transmission security, low processing efficiency and insufficient resource utilization in the prior art.

[0081] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0082] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented by software, the above embodiments may be implemented in whole or in part in the form of a computer program product. Those skilled in the art may appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein may be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed by hardware or software methods depends on the specific application and design constraints of the technical solution.

[0083] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0084] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. An expandable network security motherboard system, characterized in that: Specifically include: A mainboard body, the mainboard body being electrically connected to the encryption module and the timing module, and being used to send interactive data to the encryption module, dynamically generate a clock signal according to the interactive data, and send the clock signal to the timing module; An encryption module, which is electrically connected to the data transmission module and includes at least two groups of sub-encryption units connected in parallel, and is used to encrypt the interactive data to generate encrypted data, and send the encrypted data to the data transmission module; A timing module, the timing module comprising at least two groups of serially connected sub-timing units, the sub-timing units being arranged corresponding to the sub-encryption units, for generating a timing signal according to a clock signal, and controlling the sub-encryption units using the timing signal; A data transmission module, wherein the data transmission module is used to transmit encrypted data.

2. The scalable network security motherboard system according to claim 1, characterized in that: The main board body includes a data output terminal and a clock signal terminal, the sub-encryption unit includes a data input terminal, a data output terminal and a chip select terminal, the sub-timing unit adopts a D trigger, includes a data input terminal, a clock signal terminal and a data output terminal, and the data transmission module includes a data input terminal and a data output terminal.

3. The scalable network security motherboard system according to claim 2, characterized in that: The data output end of the mainboard body is signal-connected to the data input end of each sub-encryption unit, and the data output end of each sub-encryption unit is signal-connected to the data input end of the data transmission module.

4. The scalable network security motherboard system according to claim 3, characterized in that: Each of the sub-timing units is numbered and arranged according to the number, the data output end and the data input end signal of two adjacent numbered sub-timing units are connected, and the data output end of each of the sub-timing units is connected to the chip select end signal of the corresponding sub-encryption unit.

5. The scalable network security motherboard system according to claim 4, characterized in that: The timing module also includes a logic unit, which is a NOR gate. The data output end of each sub-timing unit is signal-connected to the data input end of the logic unit, and the data output end of the logic unit is signal-connected to the signal input end of the sub-timing unit with the frontmost number.

6. The expandable network security motherboard system according to claim 5, characterized in that: Each group of sub-encryption units is preset with a different encryption algorithm, and the overall working logic of the mainboard system is: The mainboard collects data information of the interactive data, and adjusts the signal period of the clock signal according to the data information of the interactive data; The timing module generates a divided timing signal according to the adjusted clock signal, sends the timing signal to the chip selection terminal of each sub-encryption unit, and uses the timing signal to control the working status of the sub-encryption unit; The sub-encryption unit in working state encrypts the received interactive data to generate encrypted data, and sends the encrypted data to the data transmission module.

7. The expandable network security motherboard system according to claim 6, characterized in that: The data information of the interactive data includes data number, receiving time, and data length. The logic of adjusting the signal period of the clock signal according to the data information of the interactive data is: Collect data information of interaction data in time period t, set observation windows based on integer multiples of time period t, generate priority numbers for each time period t in the observation window, and the duration corresponding to time period t is t'; The priority number of each time period t in the observation window is divided into three priority levels, the number and proportion of time periods t in each priority level are counted, and a signal period corresponding to the observation window is generated.

8. The expandable network security motherboard system according to claim 7, characterized in that: The calculation method of the priority number of the time period t is: In the formula Represents the period t i The corresponding priority number, the subscript i represents the number of the time period t, i = 1, 2, 3 ... N, N represents the total number of time periods in the observation window, μ1, μ2, μ3 represent the first priority weight, the second priority weight and the third priority weight respectively, μ1 + μ2 + μ3 = 1, T j , L j They represent the receiving period and data length of the jth interactive data, respectively, and M represents the receiving period and data length of the jth interactive data in period t i The number of internal interaction data; The priority numbers of all time periods in the observation window are divided as follows: When the priority number corresponding to the time period meets: Consider this period as low priority; When the priority number corresponding to the time period meets This period is considered to be of medium priority; When the priority number corresponding to the time period meets Consider this period as high priority; In the formula They respectively represent the maximum and minimum values ​​of the priority numbers in all time periods within the observation window.

9. The expandable network security motherboard system according to claim 8, characterized in that: The signal period is calculated as follows: Wherein Tz represents the signal period, α1, α2, and α3 represent the first influence weight, the second influence weight, and the third influence weight, respectively, wherein α1<α2<α3, and α1+α2+α3=1, and N(l), N(m), and N(h) represent the number of time periods with low priority, medium priority, and high priority in the observation window, respectively.

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