Image sensor mixed domain accumulator based on pixel sharing and application method thereof

Abstract

The invention discloses an image sensor mixed domain accumulator based on pixel sharing and an application method thereof, the image sensor mixed domain accumulator comprises N two-stage charge domain accumulators and an N-stage analog domain accumulator, the output end of each two-stage charge domain accumulator is connected with the input end of the N-stage analog domain accumulator to form a 2N-stage mixed domain accumulator, the N-stage analog domain accumulator is connected with the N-stage charge domain accumulator, and the N-stage analog domain accumulator is connected with the N-stage charge domain accumulator. The two-stage charge domain accumulator can realize two-time accumulation of the same signal within two-time roller exposure time and output the signal after the two-time accumulation is finished after the two-time roller exposure is finished, the N-stage simulation domain accumulator is used for storing the output signal of the two-stage charge domain accumulator on a storage capacitor of the integrator, the operation is repeated for multiple times, and the output signal of the N-stage simulation domain accumulator is stored in the storage capacitor of the integrator. According to the hybrid domain accumulator of the image sensor, low-noise accumulation can be achieved, meanwhile, the complexity of pixel circuit design is basically not improved, the influence of stray capacitance on an accumulation result of a high-level digital simulation domain can be restrained, and the signal-to-noise ratio of the image sensor is further improved.

Description

Technical Field

[0001] The invention belongs to the technical field of TDI type image sensors and relates to a mixed domain accumulator of a TDI type image sensor based on pixel sharing. Background Art

[0002] The time delay integration (TDI) image sensor is an image sensor that realizes the linear array imaging function in the form of a planar array of pixels. Compared with ordinary linear array imaging sensors, it can expose the same target multiple times and accumulate the multiple exposure signals, which prolongs the equivalent exposure time of the image sensor and increases the exposure, thereby enhancing the image signal. Since the TDI image sensor accumulates multiple sampling signals, the signal increase rate is higher than the noise, which can achieve an improvement in the signal-to-noise ratio. Based on the above characteristics, the TDI image sensor can obtain an output image with a high signal-to-noise ratio (SNR) under high-speed and low-light conditions.

[0003] Early TDI image sensors were all implemented through charge coupled devices (CCDs). Although TDI CCD image sensors can achieve low-noise signal accumulation through charge transfer, their high power consumption and poor compatibility with CMOS processes limit their applications. With the development of CMOS technology, its power consumption and cost are getting lower and lower, and its integration is getting higher and higher. At the same time, the performance of MOS devices is also constantly improving, especially in terms of noise, light response, dark current, etc. Therefore, TDI CMOS image sensors have begun to be widely used.

[0004] TDI CMOS image sensors can be implemented in the charge domain, analog domain, and digital domain. As the number of accumulation stages increases, the difficulty of pixel circuit design will continue to increase when the TDI CMOS image sensor is implemented in the charge domain. When the TDI CMOS image sensor is implemented in the analog domain, the accumulation result of the analog accumulator is increasingly affected by the internal parasitic capacitance. When the TDI CMOS image sensor is implemented in the digital domain, higher power consumption and a high-speed analog-to-digital converter (ADC) are required. These problems strictly limit the improvement of the effective accumulation stage and signal-to-noise ratio of the TDI CMOS image sensor. Summary of the invention

[0005] An object of the present invention is to provide a mixed domain accumulator for an image sensor based on pixel sharing, which can improve the effective accumulation level and signal-to-noise ratio of a TDI type CMOS image sensor while avoiding the increase of circuit area and power consumption.

[0006] Another object of the present invention is to provide an application method of a mixed domain accumulator of an image sensor based on pixel sharing.

[0007] The first technical solution adopted by the present invention is a hybrid domain accumulator of an image sensor based on pixel sharing, including N two-stage charge domain accumulators and one N-stage analog domain accumulator. The output end of each two-stage charge domain accumulator is connected to the input end of the N-stage analog domain accumulator to form a 2N-stage hybrid domain accumulator. The two-stage charge domain accumulator will realize two accumulations of the same signal within two roller exposure times, and output the signal that has completed the two accumulations after the two roller exposures are completed. The N-stage analog domain accumulator is used to store the output signal of the two-stage charge domain accumulator on the storage capacitor of the integrator. The operation is repeated many times to realize multi-stage accumulation of the hybrid domain.

[0008] Among them, the two-stage charge domain accumulator includes two photodiodes PD1 and PD2, two reset tubes M1 and M5, two transmission tubes M2 and M6, a source follower tube M3, and a row select tube M4. The gate of the reset tube M1 is connected to the signal RST1, the drain is connected to the power supply voltage, the source is connected to the cathode of the photodiode PD1, and the anode of the photodiode PD1 is grounded. The gate of the transmission tube M2 is connected to the signal TX1, the drain is connected to the cathode of the photodiode PD1, and the source is connected to the gate of the source follower tube M3. The gate of the reset tube M5 is connected to the signal RST2, the drain is connected to the power supply voltage, the source is connected to the cathode of the photodiode PD2, and the anode of the photodiode PD2 is grounded. The gate of the transmission tube M6 is connected to the signal TX2, the drain is connected to the cathode of the photodiode PD2, the source is connected to the gate of the source follower tube M3, the drain of the source follower tube M3 is connected to the power supply voltage, the source is connected to the drain of the row select tube M4, the gate of the row select tube M4 is connected to the signal SEL2, and the source is connected to the column line output.

[0009] The N-stage analog domain accumulator includes an operational amplifier, two sampling switches RST and RST', an N+1-stage integrator, two sampling capacitors Cs1 and Cs2, and four circuit switching switches L 11 , L 12 , L 21 , L 22 The lower plate of the sampling capacitor Cs1 is connected to the column line output, and the upper plate is connected to the circuit switching switch L 11 , L 21 Input terminal, circuit switching switch L 11 The output terminal is connected to the negative input terminal of the operational amplifier and the circuit switching switch L 22 Output terminal, circuit switching switch L 21 The output terminal is connected to the positive input terminal of the operational amplifier and the circuit switching switch L 12 Output terminal, circuit switching switch L 22 The input end is connected to the upper plate of the sampling capacitor Cs2 and the circuit switching switch L 12Input end, the lower plate of the sampling capacitor Cs2 is connected to the reference voltage, one end of the sampling switch RST is connected to the negative input end of the operational amplifier and the input end of each stage integrator, and the other end is connected to the positive output end of the operational amplifier, the sampling switch RST' input end is connected to the positive input end of the operational amplifier and the input end of each stage integrator, and the output end is connected to the negative output end of the operational amplifier.

[0010] Each integrator stage consists of four integral switches I A ,I B ,I C ,I D , four circuit switching switches K A , K B , K C , K D , two integrating capacitors C H , C H ', and three reset switches Rs, Rs', Rs", the integral switch I A , Circuit switch K A The input of the reset switch Rs is connected to the negative input of the operational amplifier, and the integral switch I A , the output end of the reset switch Rs is connected to the circuit switching switch K B Input terminal and integrating capacitor C H Upper plate, circuit switch K A The output terminal is connected to the integrating capacitor C H Lower plate and integral switch I B Input terminal, circuit switching switch K B and integral switch I B The output ends of the reset switch Rs' are connected to the positive output end of the operational amplifier, and the input end of the reset switch Rs' is connected to the integral capacitor C H The lower plate, the output end is connected to the integrating capacitor C H 'Lower plate, positive input of operational amplifier connected to circuit switch K C , Integral switch I D and reset switch Rs” input terminal, circuit switching switch K C The output terminal is connected to the integral switch I C Input terminal and integrating capacitor C H 'Lower plate, integral switch I D Output terminal connected to circuit switch K D Input, reset switch Rs” output and integral capacitor C H 'Upper plate, circuit switch K D and integral switch I C The output terminal is connected to the negative output terminal of the operational amplifier.

[0011] The second technical solution adopted by the present invention is an application method of a hybrid domain accumulator of an image sensor based on pixel sharing, which divides the image into 2N rows of pixels and represents them with 2N symbols. Each time the drum is exposed, only one new symbol image enters the sensor. In order to realize two-level accumulation, the PD and FD nodes are reset first, and the charge accumulated by the photodiodes in the first row of pixels is transferred to the FD node after the first drum exposure. After the second drum exposure, the charge of the same image accumulated by the photodiodes in the second row of pixels is transferred to the FD node, realizing two-level charge domain noise-free accumulation, and outputting to the N-level analog domain accumulator through the source follower tube M3 and the row select tube M4. The circuit switching switch L in the N-level analog domain accumulator 11 , L 12 With circuit switch L 21 , L 22 The integrator works alternately in different working cycles of the analog domain accumulator, and the integration switch and the circuit switching switch in the integrator also work alternately in different working cycles of the analog domain accumulator, so that two positive sign signals are accumulated in the same integration capacitor, and a signal coupled to the integration capacitor by a reverse parasitic capacitor and a signal coupled to the integration capacitor by a forward parasitic capacitor will be offset on the integration capacitor.

[0012] During the first roller exposure, the RST1 signal is high, the reset tube M1 is turned on, and the first row of pixels is reset. After the reset, the RST1 signal is low, the reset tube M1 is turned off, and the photodiode PD1 of the first row of pixels begins to expose the first symbol. After the exposure, the TX1 signal is high, the transmission tube M2 is turned on, and the charge accumulated at the PD1 node is transferred to the FD2 node, and the charge accumulated by the first symbol of one exposure is stored at the FD2 node. Then the TX1 signal is low, and the transmission tube M2 is turned off.

[0013] During the second roller exposure, the RST1 signal is high, the reset tube M1 is turned on, and the first row of pixels is reset. After the reset, the RST1 signal is low, the reset tube M1 is turned off, and the photodiode PD1 of the first row of pixels begins to expose the second symbol. Before the first row of pixels is exposed, the RST2 signal is high, the reset tube M5 is turned on, and the second row of pixels is reset. After the reset, the RST2 signal is low, the reset tube M5 is turned off, and then the photodiode PD2 of the second row of pixels begins to expose the first symbol. Then the TX2 and SEL2 signals are high, the transmission tube M6 and the row selection tube M4 are turned on, and the charge accumulated at the PD2 node will be transferred to the FD2 node. The first row of pixels exposed twice will be exposed twice at the FD2 node. The charge accumulated by the symbol is accumulated and output through the source follower tube and the row select tube to realize the two-level accumulation of the charge domain. Then the RST2 signal is high, the reset tube M5 is turned on, the PD2 and FD2 nodes are reset, and the reset signal is output. Then the TX2, SEL2, and RST2 signals are low, the transmission tube M6, the row select tube M4, and the reset tube M5 are turned off. Then the TX1 signal is high, the transmission tube M2 is turned on, and the charge accumulated at the PD1 node is transferred to the FD2 node, and the charge accumulated by the second symbol exposed once is stored at the FD2 node. Then the TX1 signal is low, the transmission tube M2 is turned off, and when waiting for the next drum exposure, the charge accumulated by the second symbol exposed by the second row of pixels is accumulated and output.

[0014] During the same working cycle of the N-stage analog domain accumulator, the circuit switches the switch L 11 , L 12 and four integral switches I A ,I B ,I C ,I D Working simultaneously, during the next N-stage analog domain accumulator working cycle, the circuit switches switch L 21 , L 22 And four circuit switching switches K A , K B , K C , K D Working simultaneously, the integrating capacitor will store a positive sign signal and a signal coupled to the integrating capacitor by a negative parasitic capacitance, and a positive sign signal and a signal coupled to the integrating capacitor by a positive parasitic capacitance in two working cycles.

[0015] The beneficial effect of the present invention is that a mixed domain accumulator of an image sensor based on pixel sharing is formed by N two-stage charge domain accumulators and one N-stage analog domain accumulator, and every two rows of pixels will share an output circuit. Therefore, compared with the traditional 4T pixel structure, one transistor is reduced for each pixel in the pixel sharing circuit, thereby improving the fill factor of the pixel module, and the complexity of the pixel circuit design is basically not increased while achieving low-noise accumulation; for the analog domain accumulator, a circuit switching switch is added, and the influence of parasitic capacitance on the high-order analog domain accumulation result is suppressed without changing the working principle of the analog domain accumulator, which can further improve the signal-to-noise ratio of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a circuit diagram of a mixed domain accumulator of an image sensor based on pixel sharing of the present invention;

[0017] Figure 2 It is a circuit diagram of a two-stage charge domain accumulator in a hybrid domain accumulator of an image sensor based on pixel sharing of the present invention;

[0018] Figure 3 It is a circuit diagram of an N-level analog domain accumulator in a hybrid domain accumulator of an image sensor based on pixel sharing of the present invention;

[0019] Figure 4 It is a working timing diagram of a two-stage charge domain accumulator in a hybrid domain accumulator of an image sensor based on pixel sharing of the present invention;

[0020] Figure 5 It is a working timing diagram of the N-level analog domain accumulator in the hybrid domain accumulator of the image sensor based on pixel sharing of the present invention. DETAILED DESCRIPTION

[0021] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Example 1

[0023] A mixed domain accumulator for image sensors based on pixel sharing, referring to Figure 1 , including N two-stage charge domain accumulators and one N-stage analog domain accumulator. The output end of each two-stage charge domain accumulator is connected to the input end of the N-stage analog domain accumulator to form a 2N-stage mixed domain accumulator. The two-stage charge domain accumulator will realize two accumulations of the same signal within two roller exposure times, and output the signal after the two roller exposures. The N-stage analog domain accumulator is used to store the output signal of the two-stage charge domain accumulator on the storage capacitor of the integrator. The operation is repeated many times to realize multi-stage accumulation of the mixed domain.

[0024] Reference Figure 2The two-stage charge domain accumulator includes two photodiodes PD1 and PD2, two reset tubes M1 and M5, two transmission tubes M2 and M6, a source follower tube M3, and a row select tube M4. The gate of the reset tube M1 is connected to the signal RST1, the drain is connected to the power supply voltage, the source is connected to the cathode of the photodiode PD1, and the anode of the photodiode PD1 is grounded. The gate of the transmission tube M2 is connected to the signal TX1, the drain is connected to the cathode of the photodiode PD1, and the source is connected to the gate of the source follower tube M3. The gate of the reset tube M5 is connected to the signal RST2, the drain is connected to the power supply voltage, the source is connected to the cathode of the photodiode PD2, and the anode of the photodiode PD2 is grounded. The gate of the transmission tube M6 is connected to the signal TX2, the drain is connected to the cathode of the photodiode PD2, the source is connected to the gate of the source follower tube M3, the drain of the source follower tube M3 is connected to the power supply voltage, the source is connected to the drain of the row select tube M4, the gate of the row select tube M4 is connected to the signal SEL2, and the source is connected to the column line output.

[0025] The N-stage analog domain accumulator includes an operational amplifier, two sampling switches RST and RST', an N+1-stage integrator, two sampling capacitors Cs1 and Cs2, and four circuit switching switches L 11 , L 12 , L 21 , L 22 The lower plate of the sampling capacitor Cs1 is connected to the column line output, and the upper plate is connected to the circuit switching switch L 11 , L 21 Input terminal, circuit switching switch L 11 The output terminal is connected to the negative input terminal of the operational amplifier and the circuit switching switch L 22 Output terminal, circuit switching switch L 21 The output terminal is connected to the positive input terminal of the operational amplifier and the circuit switching switch L 12 Output terminal, circuit switching switch L 22 The input end is connected to the upper plate of the sampling capacitor Cs2 and the circuit switching switch L 12 Input end, the lower plate of the sampling capacitor Cs2 is connected to the reference voltage, one end of the sampling switch RST is connected to the negative input end of the operational amplifier and the input end of each stage integrator, and the other end is connected to the positive output end of the operational amplifier, the sampling switch RST' input end is connected to the positive input end of the operational amplifier and the input end of each stage integrator, and the output end is connected to the negative output end of the operational amplifier.

[0026] Example 2

[0027] A pixel-sharing-based image sensor hybrid domain accumulator comprises N two-stage charge domain accumulators and one N-stage analog domain accumulator. The output end of each two-stage charge domain accumulator is connected to the input end of the N-stage analog domain accumulator to form a 2N-stage hybrid domain accumulator. The two-stage charge domain accumulator includes two photodiodes PD1 and PD2, two reset tubes M1 and M5, two transmission tubes M2 and M6, a source follower tube M3, and a row select tube M4. The gate of the reset tube M1 is connected to the signal RST1, the drain is connected to the power supply voltage, the source is connected to the cathode of the photodiode PD1, and the anode of the photodiode PD1 is grounded. The gate of the transmission tube M2 is connected to the signal TX1, the drain is connected to the cathode of the photodiode PD1, and the source is connected to the gate of the source follower tube M3. The gate of the reset tube M5 is connected to the signal RST2, the drain is connected to the power supply voltage, the source is connected to the cathode of the photodiode PD2, and the anode of the photodiode PD2 is grounded. The gate of the transmission tube M6 is connected to the signal TX2, the drain is connected to the cathode of the photodiode PD2, the source is connected to the gate of the source follower tube M3, the drain of the source follower tube M3 is connected to the power supply voltage, the source is connected to the drain of the row select tube M4, the gate of the row select tube M4 is connected to the signal SEL2, and the source is connected to the column line output.

[0028] See also Figure 3 The N-level analog domain accumulator includes an operational amplifier, two sampling switches RST, RST', N+1-level integrator, two sampling capacitors Cs1, Cs2, and four circuit switching switches L 11 , L 12 , L 21 , L 22 The lower plate of the sampling capacitor Cs1 is connected to the column line output, and the upper plate is connected to the circuit switching switch L 11 , L 21 Input terminal, circuit switching switch L 11 The output terminal is connected to the negative input terminal of the operational amplifier and the circuit switching switch L 22 Output terminal, circuit switching switch L 21 The output terminal is connected to the positive input terminal of the operational amplifier and the circuit switching switch L 12 Output terminal, circuit switching switch L 22 The input end is connected to the upper plate of the sampling capacitor Cs2 and the circuit switching switch L 12 Input end, the lower plate of the sampling capacitor Cs2 is connected to the reference voltage, one end of the sampling switch RST is connected to the negative input end of the operational amplifier and the input end of each stage integrator, and the other end is connected to the positive output end of the operational amplifier, the sampling switch RST' input end is connected to the positive input end of the operational amplifier and the input end of each stage integrator, and the output end is connected to the negative output end of the operational amplifier.

[0029] Each integrator stage consists of four integral switches I A ,I B ,I C ,I D , four circuit switching switches KA , K B , K C , K D , two integrating capacitors C H , C H ', and three reset switches Rs, Rs', Rs", the integral switch I A , Circuit switch K A The input of the reset switch Rs is connected to the negative input of the operational amplifier, and the integral switch I A , the output end of the reset switch Rs is connected to the circuit switching switch K B Input terminal and integrating capacitor C H Upper plate, circuit switch K A The output terminal is connected to the integrating capacitor C H Lower plate and integral switch I B Input terminal, circuit switching switch K B and integral switch I B The output ends of the reset switch Rs' are connected to the positive output end of the operational amplifier, and the input end of the reset switch Rs' is connected to the integral capacitor C H The lower plate, the output end is connected to the integrating capacitor C H 'Lower plate, positive input of operational amplifier connected to circuit switch K C , Integral switch I D and reset switch Rs” input terminal, circuit switching switch K C The output terminal is connected to the integral switch I C Input terminal and integrating capacitor C H 'Lower plate, integral switch I D Output terminal connected to circuit switch K D Input, reset switch Rs” output and integral capacitor C H 'Upper plate, circuit switch K D and integral switch I C The output terminal is connected to the negative output terminal of the operational amplifier.

[0030] The two-stage charge domain accumulator will realize two accumulations of the same signal within the two roller exposure times, and output the signals that have completed the two accumulations after the two roller exposures. The N-stage analog domain accumulator is used to store the output signals of the two-stage charge domain accumulator on the storage capacitor of the integrator. The operation is repeated many times to realize multi-stage accumulation in the mixed domain.

[0031] Example 3

[0032] An application method of a mixed domain accumulator for an image sensor based on pixel sharing, referring to Figure 4 and Figure 5, the image is divided into 2N rows of pixels, represented by 2N symbols such as A, B, C, D, E, F, etc., each time the drum is exposed, only one new symbol image will enter the sensor. In order to achieve two-level accumulation, the PD and FD nodes are reset first, and the charge accumulated by the photodiodes in the first row of pixels is transferred to the FD node after the first drum exposure. After the second drum exposure, the charge of the same image accumulated by the photodiodes in the second row of pixels is transferred to the FD node to achieve two-level charge domain noise-free accumulation, and output to the N-level analog domain accumulator through the source follower tube M3 and the row select tube M4. The circuit switching switch L in the N-level analog domain accumulator 11 , L 12 With circuit switch L 21 , L 22 The analog domain accumulator works alternately in different working cycles, and the integration switch and the circuit switching switch in the integrator also work alternately in different working cycles of the analog domain accumulator.

[0033] During the same working cycle of the N-stage analog domain accumulator, the circuit switches the switch L 11 , L 12 and four integral switches I A ,I B ,I C ,I D Working simultaneously, during the next N-stage analog domain accumulator working cycle, the circuit switches switch L 21 , L 22 And four circuit switching switches K A , K B , K C , K D Working at the same time, the integration capacitor will store a positive sign signal and a reverse parasitic capacitance coupled to the integration capacitor, as well as a positive sign signal and a positive parasitic capacitance coupled to the integration capacitor in two working cycles. The two positive sign signals are accumulated in the same integration capacitor, and a reverse parasitic capacitance coupled to the integration capacitor and a positive parasitic capacitance coupled to the integration capacitor are offset on the integration capacitor, thereby suppressing the influence of the parasitic capacitance on the accumulation result and achieving compensation for the parasitic effect.

[0034] During the first roller exposure, the RST1 signal is high, the reset tube M1 is turned on, and the first row of pixels is reset. After the reset, the RST1 signal is low, the reset tube M1 is turned off, and the photodiode PD1 of the first row of pixels begins to expose the first symbol, that is, symbol A. After the exposure, the TX1 signal is high, the transmission tube M2 is turned on, and the charge accumulated at the PD1 node is transferred to the FD2 node, and the charge accumulated by the symbol A exposed once is stored at the FD2 node. Then the TX1 signal is low, and the transmission tube M2 is turned off.

[0035] During the second roller exposure, the RST1 signal is high, the reset tube M1 is turned on, and the first row of pixels is reset. After the reset, the RST1 signal is low, the reset tube M1 is turned off, and the photodiode PD1 of the first row of pixels begins to expose the second symbol, that is, symbol B. Before the first row of pixels is exposed, the RST2 signal is high, the reset tube M5 is turned on, and the second row of pixels is reset. After the reset, the RST2 signal is low, the reset tube M5 is turned off, and then the photodiode PD2 of the second row of pixels begins to expose symbol A. Then the TX2 and SEL2 signals are high, the transmission tube M6 and the row selection tube M4 are turned on, and the charge accumulated at the PD2 node is transferred to the FD2 node. The two charges are transferred to the FD2 node. The charge accumulated by the exposure symbol A is accumulated and output through the source follower tube and the row select tube to realize the two-level accumulation of the charge domain. Then the RST2 signal is high, the reset tube M5 is turned on, the PD2 and FD2 nodes are reset, and the reset signal is output. Then the TX2, SEL2, and RST2 signals are low, the transmission tube M6, the row select tube M4, and the reset tube M5 are turned off. Then the TX1 signal is high, the transmission tube M2 is turned on, and the charge accumulated at the PD1 node is transferred to the FD2 node, and the charge accumulated by the exposure symbol B is stored at the FD2 node. Then the TX1 signal is low, the transmission tube M2 is turned off, and when waiting for the next drum exposure, the charge accumulated by the exposure symbol B of the second row of pixels is accumulated and output.

[0036] After the first two roller exposures are completed, the symbol A signal exposed twice in pixels 1 and 2 is output, and the circuit switches switch L 11 , L 12 , the sampling switches RST, RST', and the three reset switches Rs1, Rs1' and Rs1" are turned on, and the circuit switching switch L 21 and L 22 Disconnected, the sampling capacitor collects information, and the integrating capacitor C H1 and C H1 'Reset, then the sampling switches RST, RST', and the three reset switches Rs1, Rs1' and Rs1" are disconnected, and the four integration switches I A1 ,I B1 ,I C1 and I D1 When the sampling capacitor is turned on, the charge accumulated on the sampling capacitor will be transferred to the integrating capacitor C H1 and C H1 ', at this time the integral capacitor C H1 and C H1 A positive A signal is stored on the ', and the output voltage will have a jump V A Then the four integral switches I A1 ,I B1 ,I C1 and I D1The sampling switches RST and RST' are turned on, and the output voltage will have a reverse jump -V A , the parasitic capacitance in the integrator will cause this reverse jump -V A Coupled to the integrating capacitor C H1 and C H1 'superior.

[0037] After the third and fourth drum exposures are completed, the symbol B signal is output twice in pixels 1 and 2, and the circuit switches switch L 21 , L 22 , sampling switches RST, RST', and three reset switches Rs N+1 , Rs N+1 ' and Rs N+1 " is turned on, the circuit switches to switch L 11 and L 12 Disconnected, the sampling capacitor collects information, and the integrating capacitor C HN+1 and C HN+1 'Reset, then sampling switches RST, RST', and three reset switches Rs N+1 , Rs N+1 ' and Rs N+1 "Disconnect, four circuit switch K AN+1 , K BN+1 , K CN+1 , K DN+1 The charge accumulated on the sampling capacitor is transferred to the integrating capacitor C HN+1 and C HN+1 ', at this time the integral capacitor C HN+1 and C HN+1 'A positive sign B signal is stored on the output voltage, and there is a jump V B Then the four circuit switches K AN+1 , K BN+1 , K CN+1 , K DN+1 The sampling switches RST and RST' are turned on, and the symbol A signal exposed twice in pixels 3 and 4 is output. The sampling capacitor collects information. At this time, the output voltage will have a reverse jump -V B , the parasitic capacitance in the integrator will cause this reverse jump -V B Coupled to the integrating capacitor C HN+1 and C HN+1 '. Then the sampling switches RST and RST' are disconnected, and the four circuit switching switches K A1 , K B1 , K C1 and K D1 When the sampling capacitor is turned on, the charge accumulated on the sampling capacitor will be transferred to the integrating capacitor C H1 and C H1', at this time the integral capacitor C H1 and C H1 A positive A signal is stored on the ', and the output voltage will have a jump V A Then the sampling switches RST and RST' are turned on, and the four circuit switching switches K A1 , K B1 , K C1 and K D1 Disconnect, the output voltage will have a positive jump V A , the parasitic capacitance in the integrator will cause this positive jump V A Coupled to the integrating capacitor C H1 and C H1 '. At this time, the integral capacitor C H1 and C H1 There will be two positive A signals and one negative parasitic capacitance coupled to the integral capacitor C. H1 and C H1 The signal on the ' and a positive parasitic capacitance are coupled to the integrating capacitor C H1 and C H1 ', the two signals will cancel each other out due to parasitic capacitance coupling, and only the integral capacitor C H1 and C H1 In addition, the two opposite output jumps of integrator 1 in the second working cycle of the analog domain accumulator will also be coupled to the integration capacitor C through the parasitic capacitance. HN+1 and C HN+1 ', but the two can directly cancel each other out. Working in this way, the circuit switching will suppress the effect of parasitic capacitance on the analog domain accumulation result, thereby further improving the SNR of the image sensor.

Claims

1. Image sensor mixed domain accumulator based on pixel sharing, It is characterized in that It includes N two-stage charge domain accumulators and one N-stage analog domain accumulator. The output end of each two-stage charge domain accumulator is connected to the input end of the N-stage analog domain accumulator to form a 2N-stage mixed domain accumulator. The two-stage charge domain accumulator can realize two accumulations of the same signal within two roller exposure times, and output the signal after the two roller exposures. The N-stage analog domain accumulator is used to store the output signal of the two-stage charge domain accumulator on the storage capacitor of the integrator. The operation is repeated many times to realize multi-stage accumulation of the mixed domain.

2. The image sensor mixed domain accumulator based on pixel sharing according to claim 1, It is characterized in that The two-stage charge domain accumulator includes two photodiodes PD 1 , PD 2 , two reset tubes M 1 、M 5 , two transmission tubes M 2 、M 6 , a source follower M 3 , a row selection control M 4 , reset tube M 1 Gate termination signal RST 1 , the drain terminal is connected to the power supply voltage, and the source terminal is connected to the photodiode PD 1 The cathode of the photodiode PD 1 Anode grounded, transmission tube M 2 Gate termination signal TX 1 , drain-terminated photodiode PD 1 Cathode, source terminal connected to source follower tube M 3 The gate of the reset tube M 5 Gate termination signal RST 2 , the drain terminal is connected to the power supply voltage, and the source terminal is connected to the photodiode PD 2 The cathode of the photodiode PD 2 Anode grounded, transmission tube M 6 Gate termination signal TX 2 , drain-terminated photodiode PD 2 Cathode, source terminal connected to source follower tube M 3 The gate of the tube M 3 The drain terminal is connected to the power supply voltage, and the source terminal is connected to the row select tube M 4 The drain terminal of the row selector M 4 The gate termination signal SEL 2 , the source terminal is connected to the column line output.

3. The image sensor mixed domain accumulator based on pixel sharing according to claim 2, It is characterized in that The N-stage analog domain accumulator includes an operational amplifier, two sampling switches RST, RST', an N+1-stage integrator, and two sampling capacitors Cs 1 , Cs 2 , four circuit switching switches L 11 , L 12 , L 21 , L 22 , sampling capacitor Cs 1 The lower plate is connected to the column line output, and the upper plate is connected to the circuit switch L 11 , L 21 Input terminal, circuit switching switch L 11 The output terminal is connected to the negative input terminal of the operational amplifier and the circuit switching switch L 22 Output terminal, circuit switching switch L 21 The output terminal is connected to the positive input terminal of the operational amplifier and the circuit switching switch L 12 Output terminal, circuit switching switch L 22 The input terminal is connected to the sampling capacitor Cs 2 Upper plate and circuit switch L 12 Input terminal, sampling capacitor Cs 2 The lower plate is connected to the reference voltage, one end of the sampling switch RST is connected to the negative input of the operational amplifier and the input of each stage integrator, and the other end is connected to the positive output of the operational amplifier, the input of the sampling switch RST' is connected to the positive input of the operational amplifier and the input of each stage integrator, and the output is connected to the negative output of the operational amplifier.

4. The image sensor mixed domain accumulator based on pixel sharing according to claim 3, It is characterized in that Each stage of the integrator consists of four integral switches I A ,I B ,I C ,I D , four circuit switching switches K A , K B , K C , K D , two integrating capacitors C H , C H ', and three reset switches Rs, Rs', Rs", the integral switch I A , Circuit switch K A The input of the reset switch Rs is connected to the negative input of the operational amplifier, and the integral switch I A , the output end of the reset switch Rs is connected to the circuit switching switch K B Input terminal and integrating capacitor C H Upper plate, circuit switch K A The output terminal is connected to the integrating capacitor C H Lower plate and integral switch I B Input terminal, circuit switching switch K B and integral switch I B The output ends of the reset switch Rs' are connected to the positive output end of the operational amplifier, and the input end of the reset switch Rs' is connected to the integral capacitor C H The lower plate, the output end is connected to the integrating capacitor C H 'Lower plate, positive input of operational amplifier connected to circuit switch K C , Integral switch I D and reset switch Rs” input terminal, circuit switching switch K C The output terminal is connected to the integral switch I C Input terminal and integrating capacitor C H 'Lower plate, integral switch I D Output terminal connected to circuit switch K D Input, reset switch Rs” output and integral capacitor C H 'Upper plate, circuit switch K D and integral switch I C The output terminal is connected to the negative output terminal of the operational amplifier.

5. Application method of mixed domain accumulator for image sensor based on pixel sharing, It is characterized in that The image is divided into 2N rows of pixels, represented by 2N symbols. Each time the drum is exposed, only one new symbol image enters the sensor. In order to achieve two-level accumulation, the PD and FD nodes are reset first. After the first drum exposure, the charge accumulated by the photodiodes in the first row of pixels is transferred to the FD node. After the second drum exposure, the charge accumulated by the photodiodes in the second row of pixels is transferred to the FD node. This realizes two-level charge domain noiseless accumulation and is transmitted through the source follower M. 3 and the election management 4 The output is sent to the N-level analog domain accumulator, and the circuit in the N-level analog domain accumulator switches the switch L 11 , L 12 With circuit switch L 21 , L 22 The integrator works alternately in different working cycles of the analog domain accumulator, and the integration switch and the circuit switching switch in the integrator also work alternately in different working cycles of the analog domain accumulator, so that two positive sign signals are accumulated in the same integration capacitor, and a signal coupled to the integration capacitor by a reverse parasitic capacitor and a signal coupled to the integration capacitor by a forward parasitic capacitor will be offset on the integration capacitor.

6. The application method of the image sensor mixed domain accumulator based on pixel sharing according to claim 5, It is characterized in that During the first drum exposure, RST 1 The signal is high, reset tube M 1 Turn on, reset the first row of pixels, and RST 1 The signal is low, reset tube M 1 The photodiodes PD of the first row of pixels are turned off. 1 Start exposing the first symbol. After the exposure is completed, TX 1 The signal is high, the transmission tube M 2 Conductivity, PD 1 The charge accumulated in the node is transferred to the FD 2 The charge accumulated by the first symbol of an exposure is stored in FD 2 Node, then TX 1 The signal is low, the transmission tube M 2 Shut down.

7. The application method of the image sensor mixed domain accumulator based on pixel sharing according to claim 6, It is characterized in that During the second drum exposure, RST 1 The signal is high, reset tube M 1 Turn on, reset the first row of pixels, and RST 1 The signal is low, reset tube M 1 The photodiodes PD of the first row of pixels are turned off. 1 Start exposing the second symbol. Before the first row of pixels is exposed, RST 2 The signal is high, reset tube M 5 Turn on and reset the pixels in the second row. After the reset is completed, RST 2 The signal is low, reset tube M 5 The photodiodes PD of the second row of pixels are then turned off. 2 Start exposing the first symbol, then TX 2 , SEL 2 The signal is high, the transmission tube M 6 , Bank Election Administration 4 Conductivity, PD 2 The charge accumulated in the node is transferred to the FD 2 Node, in FD 2 The node accumulates the charge accumulated by the first symbol of the two exposures and outputs it through the source follower tube and the row select tube to achieve two-level accumulation of the charge domain. 2 The signal is high, reset tube M 5 Turn on, reset PD 2 , FD 2 node, outputs the reset signal, and then TX 2 , SEL 2 , RST 2 The signal is low, the transmission tube M 6 , Bank Election Administration 4 , reset tube M 5 Shutdown, followed by TX 1 The signal is high, the transmission tube M 2 Conductivity, PD 1 The charge accumulated in the node is transferred to the FD 2 The charge accumulated by the second symbol of the first exposure is stored in the FD 2 The node, then the TX1 signal is low, the transmission tube M2 is turned off, and waits for the next roller exposure, and the charge accumulated by the second symbol exposed by the second row of pixels is accumulated and output.

8. The application method of the image sensor mixed domain accumulator based on pixel sharing according to claim 7, It is characterized in that During the same working cycle of the N-stage analog domain accumulator, the circuit switches the switch L 11 , L 12 and four integral switches I A ,I B ,I C ,I D Working simultaneously, during the next N-stage analog domain accumulator working cycle, the circuit switches switch L 21 , L 22 And four circuit switching switches K A , K B , K C , K D Working simultaneously, the integrating capacitor will store a positive sign signal and a signal coupled to the integrating capacitor by a negative parasitic capacitance, and a positive sign signal and a signal coupled to the integrating capacitor by a positive parasitic capacitance in two working cycles.

Images