Thermoelectric refrigeration heat dissipation enhanced gallium nitride device and preparation method thereof

Abstract

The invention discloses a thermoelectric refrigeration enhanced heat dissipation GaN device, which mainly solves the problem that the output power density index of the existing GaN device is sharply deteriorated due to self-heating and heat accumulation effects under high power. The thermoelectric refrigeration device comprises a heat sink layer, a heat transfer interface layer, a substrate, a nucleating layer, a buffer layer, a channel layer, a barrier layer and a metal electrode from bottom to top, a plurality of thermoelectric refrigeration modules which are arranged in sequence are arranged between the heat transfer interface layer and the substrate, and each thermoelectric refrigeration module comprises an N-type thermoelectric material layer and a P-type thermoelectric material layer which correspond to each other. An upper metal electrode layer and a lower metal electrode layer which are patterned in series are respectively arranged on the upper surface and the lower surface, and an insulating support material is wrapped on the periphery; and a substrate insulating layer is arranged on the lower surface of the substrate so as to realize electrical isolation of the substrate and the thermoelectric refrigeration module. The method can reduce the thermal resistance of the device, enhance the heat conduction from the device substrate to the heat sink, improve the heat dissipation capability of the device, and can be used for GaN microwave power devices and power electronic devices.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a GaN device and a preparation method thereof, which can be used as a microwave power device and a power electronic device. Background Art

[0002] With the rapid advancement of microelectronics technology, GaN devices are increasingly used in multiple industries. Thanks to the high electron saturation velocity and mobility of GaN materials, their devices perform well in power conversion and current processing, especially in situations where high power and high frequency need to be processed, such as power amplifiers and RF power devices, they provide a nearly ideal solution. In addition, the wide bandgap and high breakdown voltage of GaN materials make it stable in high temperature environments and very suitable for extreme working conditions. Therefore, it has been widely used in key fields such as communications, energy and national defense. Looking to the future, with the advancement of technology, GaN devices will continue to play their unique advantages and provide strong support for the innovation of electronic technology and the expansion of application areas.

[0003] Nevertheless, with the increase in market demand, higher requirements are placed on the performance and output power of GaN devices. The self-heating effect and extremely high power of GaN devices will cause the heat flow inside the device to rise sharply in a short period of time, which seriously affects its electrical performance and long-term stability. At the same time, due to the high thermal resistance of GaN materials and insufficient thermal conductivity, this limits the output power density and overall efficiency of GaN devices. Therefore, in order to improve the electrical performance and reliability of the device, effective thermal management technology is urgently needed. There are currently four main technologies for optimizing the heat dissipation performance of GaN devices. One is to use high thermal conductivity materials such as silicon carbide and diamond as GaN device substrates to improve the heat dissipation performance of the device. However, due to the large lattice mismatch between GaN materials and diamond and other materials, the electrical performance of the device is affected. The second is to use substrate thinning technology to reduce the heat transfer path, thereby improving device performance, but due to the excessive thinness of the substrate, the subsequent process is too difficult, reducing the device yield. Third, high thermal conductivity materials such as nanocrystalline diamond and boron nitride are deposited on the surface of GaN devices as a passivation layer, and the flip-package technology is used at the same time to increase the thermal conductivity while reducing the heat transfer path, thereby improving the heat dissipation performance of the device. However, the direct growth of high thermal conductivity materials on the surface of the device will bring additional stress, thereby reducing the electrical performance of the device and reducing the reliability of the device. Fourth, layout optimization is performed to adjust the hot spot spacing of the device to reduce the thermal crosstalk effect, thereby slowing down the self-heating effect of the device, but this will increase the area of ​​the overall chip and the heat dissipation effect is not good. Fifth, microfluidic channels are integrated inside or on the surface of the device substrate to achieve active cooling of the device through refrigerant, thereby improving the heat dissipation efficiency of the device. However, since the coolant requires additional energy for transportation, the energy consumption of the device is increased.

[0004] Patent document with application number CN202211287046.7 discloses a method for bonding a GaN layer on a diamond substrate and a device thereof, the device structure is as follows Figure 5 As shown in the figure, the GaN material and the diamond substrate are bonded by the transfer method to complete the device manufacturing, so that the GaN device directly uses the diamond with higher thermal conductivity to dissipate heat. However, this method is difficult to operate, has a low success rate, and is difficult to achieve large-scale production. At the same time, there is a large lattice mismatch between GaN materials and materials such as diamond, which affects the electrical performance of the device.

[0005] Patent document with application number CN202010324599.X discloses a GaN semiconductor structure, device and preparation method with diamond microchannels. The device structure is as follows: Figure 6 As shown in the figure, a diamond film with a microchannel structure is grown on the AlGaN back barrier layer, which improves the thermal conductivity of the substrate and uses the coolant to directly contact the device heat source to dissipate heat, thereby improving the heat dissipation performance of the device. However, the growth temperature of diamond is extremely high, which will damage the grown GaN material at high temperature, causing the device to fail, and the coolant requires additional energy to transport, which increases the energy consumption of the device. Summary of the invention

[0006] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose a GaN device with enhanced heat dissipation through thermoelectric cooling and a preparation method, so as to avoid the additional stress and lattice mismatch caused by the contact between the surface of the GaN device and the high thermal conductivity material, reduce the additional power consumption of the device, and further optimize the heat dissipation performance of the device.

[0007] The technical solutions for achieving the purpose of the present invention include the following:

[0008] 1. A GaN device with enhanced heat dissipation for thermoelectric cooling, comprising from bottom to top: a heat sink layer, a heat transfer interface layer, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a metal electrode, characterized in that:

[0009] A plurality of sequentially arranged thermoelectric cooling modules are provided between the heat transfer interface layer and the substrate, each thermoelectric cooling module includes an N-type thermoelectric material layer and a P-type thermoelectric material layer corresponding to each other, and the upper and lower surfaces thereof are respectively provided with an upper metal electrode layer and a lower metal electrode layer which are patterned in series, for connecting the N-type thermoelectric material layer and the P-type thermoelectric material layer in series and applying a voltage; the outer periphery thereof is wrapped with an insulating support material to support the deposition and patterning of the lower metal electrode layer and realize electrical isolation between adjacent thermoelectric cooling modules;

[0010] A substrate insulating layer is provided on the lower surface of the substrate, which is used to achieve electrical isolation between the substrate and the thermoelectric cooling module.

[0011] Furthermore, the N-type thermoelectric material layer in the thermoelectric cooling module is made of Bi 2 Te 3 、Bi 2 (TeSe) 3 , PbTe or any other N-type material with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm;

[0012] The P-type thermoelectric material layer in the thermoelectric cooling module adopts Sb 2 Te 3 、(BiSb) 2 Te 3 、Bi 2 Te 3 Or any one of other P-type materials with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm;

[0013] The spacing between the N-type thermoelectric material layer and the P-type thermoelectric material layer in the single thermoelectric cooling module is 10-20 μm, and the spacing between two adjacent thermoelectric cooling modules is 10-30 μm.

[0014] Furthermore, the patterned upper metal electrode layer and the lower metal electrode layer are made of Ni / Au, Au / Cu, Ni / Cu or other metals matching the thermoelectric material, and have a thickness of 40 to 100 / 200 to 2000 nm, which are used to apply voltage to the thermoelectric cooling module to form current, so that a temperature difference is formed between the upper and lower surfaces of the thermoelectric cooling module, thereby improving the heat dissipation capacity of the device.

[0015] The substrate insulating layer is made of SiO 2 or Si 3 N 4 , its thickness is 0.1~1μm;

[0016] The insulating support material is SiO 2 、Si 3 N 4 Or any one of the photoresists, the thickness of which is the sum of the thickness of the upper metal electrode layer and the thermoelectric cooling module.

[0017] Furthermore, the heat transfer interface layer is made of any one of silica gel, silicone grease, epoxy resin or phase change material, and has a thickness of 1 to 500 μm, wherein the phase change material includes polyolefin resin and acrylic resin.

[0018] The heat sink layer is made of any one of copper alloy, aluminum alloy, high thermal conductivity metal or high thermal conductivity ceramic material, and its thickness is 0.1 to 10 mm, wherein the copper alloy includes copper-tungsten alloy and copper-molybdenum alloy, the aluminum alloy includes aluminum-magnesium-silicon alloy and aluminum-silicon-carbon alloy, the high thermal conductivity metal includes W, Mo, Cu, Al, and the high thermal conductivity ceramic material includes SiC ceramic and AlN ceramic.

[0019] Furthermore, the substrate is made of Si or SiC with a thickness of 50 to 500 μm; the nucleation layer is made of AlN with a thickness of 20 to 200 nm; the buffer layer is made of any one of GaN, AlN or AlGaN with a thickness of 0.1 to 5 μm; the channel layer is made of GaN with a thickness of 20 to 1000 nm; and the barrier layer is made of AlGaN with a thickness of 10 to 30 nm.

[0020] 2. A method for preparing a GaN device with enhanced heat dissipation by electrothermal cooling, characterized in that it comprises the following steps:

[0021] S1: epitaxially depositing a nucleation layer, a buffer layer, a channel layer, and a barrier layer in sequence on the upper surface of the substrate by metal organic chemical vapor deposition (MOCVD);

[0022] S2: Electrode metal is first deposited on the barrier layer by electron beam evaporation E-Beam, and then ion implantation is performed to achieve device isolation;

[0023] S3: connecting the surface of the barrier layer to an external carrier wafer through a bonding process, and pre-treating the lower surface of the substrate by thinning and polishing the surface;

[0024] S4: depositing a substrate insulating layer on the lower surface of the pretreated substrate by plasma enhanced chemical vapor deposition (PECVD);

[0025] S5: depositing a metal electrode layer on the substrate insulating layer by electron beam evaporation E-Beam;

[0026] S6: depositing an N-type thermoelectric material layer and a P-type thermoelectric material layer on the upper metal electrode layer by photolithography and metal organic chemical vapor deposition (MOCVD) to form a thermoelectric cooling module;

[0027] S7: depositing an insulating support material on the periphery of the thermoelectric cooling module by plasma enhanced chemical vapor deposition (PECVD) or spin coating;

[0028] S8: depositing a metal electrode layer on the thermoelectric cooling module and the insulating support material by electron beam evaporation E-Beam;

[0029] S9: Bonding the heat sink material to the surface of the lower metal electrode layer through the heat transfer interface material, and removing the carrier wafer to complete the device manufacturing.

[0030] Compared with the existing invention, the present invention has the following advantages:

[0031] 1) In the present invention, a plurality of sequentially arranged thermoelectric cooling modules are provided between the substrate and the heat transfer interface layer, and a voltage is applied by connecting the upper and lower metal electrode layers of the plurality of thermoelectric cooling modules, so that a current is formed in the thermoelectric cooling modules, a thermoelectric effect is generated on the upper and lower surfaces of the thermoelectric cooling modules, the upper surface temperature of the thermoelectric cooling modules is reduced, and the heat dissipation capacity of the device is improved.

[0032] 2) Since the present invention provides a substrate insulating layer between the upper metal electrode layer and the substrate, electrical isolation between the thermoelectric cooling module and the conductive channel can be achieved, substrate current leakage of the device can be reduced, and the electrical performance of the device can be optimized while improving the heat dissipation performance of the device.

[0033] 3) The present invention achieves sustained low temperature on the substrate side of the device through the thermoelectric effect of the thermoelectric cooling module. Compared with passive cooling technologies such as high thermal conductivity substrate or passivation layer cooling, it can further increase the thermal conductivity of the device, while avoiding the additional stress and lattice mismatch caused by the high thermal conductivity substrate or passivation layer directly contacting the GaN device surface, and can achieve better device heat dissipation performance and electrical performance; at the same time, since the thermoelectric cooling technology used only needs to apply voltage to the thermoelectric module, compared with existing active cooling technologies such as microchannel cooling technology, the additional power consumption of the device is greatly reduced.

[0034] 4) Since the present invention directly heterogeneously integrates the thermoelectric cooling module on the back side of the substrate, the heat conduction distance is shortened to a great extent, the thermal resistance of the device is reduced, and it is beneficial to reduce the size and weight of the equipment; at the same time, since the thermoelectric cooling module is integrated on the substrate, the thermal design of the subsequent device packaging can be simplified, and the complexity of device manufacturing is reduced. While ensuring the stability and reliability of the device, its flexibility and overall performance are further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a schematic diagram of the structure of the GaN HEMT with thermoelectric cooling and enhanced heat dissipation of the present invention;

[0036] Figure 2 It is a schematic diagram of the process flow of manufacturing a GaN device with enhanced heat dissipation for thermoelectric cooling according to the present invention;

[0037] Figure 3 It is a partial top view of different steps of manufacturing a thermoelectric cooling module in the present invention;

[0038] Figure 4This is a schematic diagram of the structure of a GaN SBD with enhanced heat dissipation through thermoelectric cooling manufactured in Example 3 of the present invention;

[0039] Figure 5 It is a schematic diagram of the structure of a device with a GaN layer bonded on a diamond substrate in the patent document with application number CN202211287046.7;

[0040] Figure 6 It is a schematic diagram of the structure of a GaN semiconductor device with a diamond microchannel in the patent document with application number CN202010324599.X. DETAILED DESCRIPTION

[0041] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0042] Reference Figure 1 The GaN high electron mobility transistor HEMT with enhanced heat dissipation by thermoelectric cooling of the present invention comprises a heat sink layer 1, a heat transfer interface layer 2, a thermoelectric cooling module 3, a substrate insulating layer 41, a substrate 4, a nucleation layer 5, a buffer layer 6, a channel layer 7, a barrier layer 8, a source electrode S, a drain electrode D, and a gate electrode G. Among them:

[0043] The substrate 4 is made of Si or SiC and has a thickness of 50-500 μm.

[0044] The nucleation layer 5 is made of AlN and has a thickness of 20-200 nm. It is located on the substrate 4 .

[0045] The buffer layer 6 is made of any one of GaN, AlN or AlGaN, has a thickness of 0.1-5 μm, and is located on the nucleation layer 5 .

[0046] The channel layer 7 is made of GaN and has a thickness of 20-1000 nm. The channel layer 7 is located on the buffer layer 6 .

[0047] The barrier layer 8 is made of AlGaN and has a thickness of 10-30 nm. It is located on the channel layer 7 .

[0048] The source S and drain D are made of Ti / Au with a thickness of 10-80 / 70-200 nm, and are located on the barrier layer 8 ; the gate G is made of Ni / Au with a thickness of 20-80 / 60-300 nm, and is located between the source S and drain D and on the barrier layer 8 .

[0049] The substrate insulating layer 41 is made of SiO 2 or Si 3 N 4 , with a thickness of 0.1 to 1 μm, and is located on the back side of the substrate 4 .

[0050] The thermoelectric cooling module 3 is provided in multiple numbers and is sequentially arranged between the heat transfer interface layer and the substrate at a spacing of 10 to 30 μm. Each thermoelectric cooling module is composed of an N-type thermoelectric material layer and a P-type thermoelectric material layer corresponding to each other. The spacing between the N-type thermoelectric material layer and the P-type thermoelectric material layer is 10 to 20 μm. The upper and lower surfaces of each pair of N-type thermoelectric material layers and P-type thermoelectric material layers are respectively provided with a series-patterned upper metal electrode layer 31 and a lower metal electrode layer 32, which are used to connect the N-type thermoelectric material layer and the P-type thermoelectric material layer in series and apply voltage. The outer periphery of each pair of N-type thermoelectric material layers and P-type thermoelectric material layers is wrapped with an insulating support material 33 to support the deposition and patterning of the lower metal electrode layer 32, so as to achieve electrical isolation between adjacent thermoelectric cooling modules 3.

[0051] The N-type thermoelectric material layer uses Bi 2 Te 3 、Bi 2 (TeSe) 3 , PbTe or any other N-type material with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm, and is located on the upper surface of the heat transfer interface layer 2 .

[0052] The P-type thermoelectric material layer uses Sb 2 Te 3 、(BiSb) 2 Te 3 、Bi 2 Te 3 Or any other P-type material with thermoelectric effect, with a thickness of 0.03-3000 μm and a side length of 60-200 μm; it is located on the lower surface of the substrate insulating layer 41 .

[0053] The upper metal electrode layer 31 and the lower metal electrode layer 32 are both 240-2100 nm thick and are both formed by depositing Ni / Au, Au / Cu, Ni / Cu or other metals matching the thermoelectric material.

[0054] The insulating support material 33 is SiO 2 、Si 3 N 4 or any one of the photoresists, and the thickness is the sum of the thickness of the upper metal electrode layer 31 and the thermoelectric cooling module 3 .

[0055] The heat transfer interface layer 2 is made of any one of silica gel, silicone grease, epoxy resin or phase change material, has a thickness of 1 to 500 μm, and is located on the lower surface of the lower metal electrode layer.

[0056] The heat sink layer 1 is made of any one of copper alloy, aluminum alloy, high thermal conductivity metal or high thermal conductivity ceramic material, with a thickness of 0.1-10 mm, and is located on the lower surface of the heat transfer interface layer.

[0057] Reference Figure 2 The present invention provides the following three examples, but the embodiments of the present invention are not limited thereto. The experimental methods described in the following examples are conventional methods unless otherwise specified; the reagents and materials described are commercially available unless otherwise specified.

[0058] Embodiment 1: Making the N-type thermoelectric material layer of the thermoelectric cooling module as Bi 2 Te 3 , the P-type thermoelectric material layer is Sb 2 Te 3 , with a thickness of 30nm, a buffer layer of GaN, and a GaN high electron mobility transistor HEMT with a thickness of 100nm.

[0059] Step 1: epitaxially deposit a group III nitride material on the front side of the Si substrate 4, such as Figure 2 (a).

[0060] 1.1) Deposition of AlN nucleation layer 5:

[0061] A Si substrate 4 with a size of 6 inches, a thickness of 600 μm, and a crystal orientation of

[111] is selected;

[0062] Using metal organic chemical vapor deposition (MOCVD) technology, 3 Under the process conditions of a flow rate ratio of 1000 to TMAl, a temperature of 450° C., and a growth pressure of 50 mbar, an AlN nucleation layer 5 with a thickness of 20 nm is epitaxially grown on the front side of the Si substrate 4;

[0063] 1.2) Deposition of GaN buffer layer 6:

[0064] Using metal organic chemical vapor deposition (MOCVD) technology, 3 Under the process conditions of a flow rate ratio of 1500 to TMGa, a temperature of 900 °C, and a growth pressure of 50 mbar, an epitaxial growth layer with a thickness of 100 nm and a Fe doping concentration of 1×10 18 cm -3 GaN buffer layer 6;

[0065] 1.3) Deposition of GaN channel layer 7:

[0066] Using metal organic chemical vapor deposition (MOCVD) technology, 3Under the process conditions of a flow rate ratio of 2000 to TMGa, a temperature of 1000° C., and a growth pressure of 150 mbar, a non-intentionally doped GaN channel layer 7 with a thickness of 20 nm is epitaxially grown on the GaN buffer layer 6;

[0067] 1.4) Deposition of AlGaN barrier layer 8:

[0068] Using metal organic chemical vapor deposition (MOCVD) technology, 3 Under the process conditions of a flow rate ratio of 1000 for TMGa and 1000 for TMGa and TMAl, a temperature of 800°C and a growth pressure of 50 mbar, an AlGaN barrier layer 8 with an Al composition of 0.25 and a thickness of 10 nm is epitaxially grown on the GaN channel layer 7.

[0069] Step 2: Deposit source S, drain D, and gate G metal electrodes on the surface of the barrier layer 8, and perform ion implantation to achieve device isolation, such as Figure 2 (b).

[0070] 2.1) Photolithography is performed on the surface of the barrier layer 8, that is, a layer of photoresist is first coated on the barrier layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form the source and drain regions of the device, and then the source and drain regions are bombarded with oxygen plasma for 3 minutes to reduce the ohmic contact resistance of the source and drain regions;

[0071] 2.2) Through electron beam evaporation E-Beam, the vacuum in the working room is evacuated to 2.0×10 -4 Under the process conditions of 10 / 70 nm thick Ti / Au is deposited in the source and drain regions as the source S and drain D, and then the wafer is placed in a photoresist stripping solution to remove the photoresist;

[0072] 2.3) Place the wafer with the source and drain metal deposited in an annealing furnace at N 2 Rapid annealing in an atmosphere for 50 seconds at a temperature of 800° C. to form high-quality ohmic contacts at the contact surfaces of the source and drain metals and the barrier layer 8;

[0073] 2.4) The surface of the barrier layer 8 is again photolithographically formed into a gate region, and the vacuum is evacuated to 2.0×10 -4 Under the process conditions of 1000 Pa, electron gun acceleration voltage of 6 Kv, electron gun beam current of 1 A, and evaporation time of 80 s, Ni / Au with a thickness of 20 / 60 nm is deposited in the gate region as the gate G to form a Schottky contact at the contact surface between the gate metal and the barrier layer 8, and then the wafer is placed in a photoresist stripping solution to remove the photoresist;

[0074] 2.5) Using ion implantation technology, the implantation energy is 200 keV and the ion concentration is 2×10 14 cm -2 Under the process conditions, high-energy ions are implanted into the surface of the barrier layer 8 outside the active area of ​​the wafer to complete device isolation.

[0075] Step 3: Connect the surface of the barrier layer 8 to the external carrier wafer through a bonding process, and pre-treat the lower surface of the substrate 4 by grinding and thinning and surface polishing, such as Figure 2 (c).

[0076] 3.1) The surface of the barrier layer 8 of the device having the substrate 4, the nucleation layer 5, the buffer layer 6, the channel layer 7, the barrier layer 8 and the source S, the drain D and the gate G is bonded to the sapphire carrier wafer by bonding glue, and pressure is applied to the lower surface of the substrate 4 for temporary bonding;

[0077] 3.2) The lower surface of the Si substrate 4 of the device temporarily bonded with the sapphire carrier wafer is ground and thinned to reduce its thickness to 50 μm;

[0078] 3.3) The lower surface of the thinned Si substrate 4 is polished using polishing technology to improve the smoothness and flatness of the wafer surface.

[0079] Step 4: Plasma enhanced chemical vapor deposition (PECVD) technology is used to deposit 4 and N 2 The flow rate of O was 50 cm 3 / min、160cm 3 Under the process conditions of 100 nm thick SiO2 was deposited on the back of Si substrate 4 at a temperature of 250 °C, a growth pressure of 80 Pa, and a radio frequency power of 60 W. 2 The substrate insulating layer 41, such as Figure 2 (d).

[0080] Step 5: Deposit a metal electrode layer 31 on the substrate insulating layer 41, such as Figure 2 (e).

[0081] 5.1) Photolithography is performed on the surface of the substrate insulating layer 41, that is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form an area for depositing a metal electrode;

[0082] 5.2) Through electron beam evaporation E-Beam, the vacuum in the working room is evacuated to 2.5×10 -4Under the process conditions of 100 nm Au / Ni with a thickness of 200 / 40 nm is deposited in the area where the upper metal electrode is deposited, the photoresist is removed by placing the wafer in a photoresist stripping solution, and the top view thereof is shown in Figure 3(a).

[0083] Step 6: Deposit the thermoelectric cooling module 3 on the upper metal electrode layer 31, such as Figure 2 (f).

[0084] 6.1) Photolithography is performed on the surface of the upper metal electrode layer 31, that is, a layer of photoresist is first coated on the upper metal electrode layer 31, and then alignment, exposure, development, and pattern detection are performed in sequence to form multiple areas for depositing N-type thermoelectric materials, each area having a side length of 60 μm and a spacing of 80 μm;

[0085] 6.2) Using metal organic chemical vapor deposition (MOCVD) technology, under the process conditions of a flow rate ratio of DipTe to TMBi of 2, a temperature of 200°C, and a growth pressure of 300 mbar, a 30 nm thick N-type Bi was deposited in the area where the N-type thermoelectric material was deposited. 2 Te 3 As an N-type thermoelectric material layer, the wafer is then placed in a photoresist stripping solution to remove the photoresist;

[0086] 6.3) The surface of the upper metal electrode layer 31 is again photolithographically processed to form a plurality of regions for depositing P-type thermoelectric material, each region having a side length of 60 μm and a distance of 10 μm from the adjacent N-type thermoelectric material layer;

[0087] 6.4) Using metal organic chemical vapor deposition (MOCVD) technology, under the process conditions of a flow rate ratio of DipTe to TDSb of 1, a temperature of 250°C, and a growth pressure of 200 mbar, a P-type Sb with a thickness of 30 nm was deposited in the area where the P-type thermoelectric material was deposited. 2 Te 3 As a P-type thermoelectric material layer, the wafer is then placed in a photoresist stripping solution to remove the photoresist, completing the manufacture of the thermoelectric cooling module 3, whose top view is shown in Figure 3(b).

[0088] Step 7: Deposit insulating support material 33 on the periphery of the thermoelectric cooling module 3, such as Figure 2 (g).

[0089] 7.1) Photolithography is performed again on the surface of the substrate insulating layer 41, that is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form an area for depositing insulating support material;

[0090] 7.2) Using plasma enhanced chemical vapor deposition PECVD technology, SiH4 and N 2 The flow rate of O was 80 cm 3 / min、200cm 3 Under the process conditions of 300°C, 100Pa growth pressure and 100W RF power, SiO2 was deposited in the area where the insulating support material was deposited until its height was flush with the thermoelectric cooling module. 2 As insulating support material 33, the wafer is then placed in a photoresist stripping solution to remove the photoresist, and its top view is shown in Figure 3(c).

[0091] Step 8: Deposit a metal electrode layer 32 on the thermoelectric cooling module 3 and the insulating support material 33, such as Figure 2 (h).

[0092] 8.1) Photolithography is performed on the surfaces of the thermoelectric cooling module 3 and the insulating support material 33, that is, a layer of photoresist is first coated on the thermoelectric cooling module 3 and the insulating support material 33, and then alignment, exposure, development, and pattern detection are performed in sequence to form an area for depositing a lower metal electrode layer;

[0093] 8.2) Through electron beam evaporation E-Beam, the vacuum in the working room is evacuated to 2.5×10 -4 Under the process conditions of 100 nm Pa, electron gun acceleration voltage of 8 kv, electron gun beam current of 1 A, and evaporation time of 240 s, Ni / Au with a thickness of 40 / 200 nm is deposited in the area where the lower metal electrode is deposited as the lower metal electrode layer 32, and then the wafer is placed in a photoresist stripping solution to remove the photoresist, and its top view is shown in Figure 3(d).

[0094] Step 9: Bond the heat sink layer 1 to the surface of the lower metal electrode layer 32 through the heat transfer interface layer 2, and remove the carrier wafer, such as Figure 2 (i).

[0095] 9.1) Using a spin coating process, drop silica gel on a copper-tungsten alloy heat sink 1 with a thickness of 0.1 mm and rotate it at a speed of 4500 r / s for 40 seconds to obtain a silica gel film with a thickness of 1 μm as a heat transfer interface layer 2, bond the surface of the lower metal electrode layer 32 to the silica gel film, and then put it into an oven at 100° C. to cure the silica gel film for 15 minutes to complete the heat sink connection;

[0096] 9.2) Use a debonding glue to remove the sapphire carrier temporarily bonded to the surface of the barrier layer 8 to complete the preparation of the device.

[0097] Embodiment 2: Making the N-type thermoelectric material layer of the thermoelectric cooling module as Bi 2 (TeSe) 3 , the P-type thermoelectric material layer is (BiSb) 2 Te 3, thickness is 30μm, the buffer layer is AlGaN, the Al component is 0.05, and the thickness is 2μm with a GaN high electron mobility transistor HEMT with a back barrier structure.

[0098] Step 1: epitaxially depositing a group III nitride material on the front side of the SiC substrate 4, such as Figure 2 (a).

[0099] A SiC substrate 4 with a size of 6 inches and a thickness of 600 μm is selected;

[0100] Setting NH 3 Under the process conditions of a flow rate ratio of 1500 to TMAl, a temperature of 600° C., and a growth pressure of 150 mbar, an AlN nucleation layer 5 with a thickness of 100 nm is epitaxially grown on the front surface of the SiC substrate 4 by metal organic chemical vapor deposition MOCVD technology;

[0101] Setting NH 3 Under the process conditions of a flow rate ratio of 2500 to TMGa, a flow rate ratio of TMGa to TMAl of 20, a temperature of 950°C, and a growth pressure of 100 mbar, an AlGaN buffer layer 6 with an Al component of 0.05 and a thickness of 2 μm is epitaxially grown on the AlN nucleation layer 5 by metal organic chemical vapor deposition MOCVD technology;

[0102] Setting NH 3 Under the process conditions of a flow rate ratio of 2000 to TMGa, a temperature of 1000°C, and a growth pressure of 120 mbar, an unintentionally doped GaN channel layer 7 is epitaxially grown on the AlGaN buffer layer 6 by metal organic chemical vapor deposition MOCVD technology, and the thickness of the GaN channel layer 7 is 500 nm;

[0103] Setting NH 3 Under the process conditions of a flow rate ratio of TMGa to TMGa of 2000, a flow rate ratio of TMGa to TMAl of 4, a temperature of 1100°C, and a growth pressure of 150 mbar, an AlGaN barrier layer 8 with an Al component of 0.25 and a thickness of 20 nm is epitaxially grown on the GaN channel layer 7 by metal organic chemical vapor deposition (MOCVD) technology.

[0104] Step 2: Deposit source S, drain D, and gate G metal electrodes on the surface of the barrier layer 8, and perform ion implantation to achieve device isolation, such as Figure 2 (b).

[0105] The surface of the barrier layer 8 is photolithographically processed, that is, a layer of photoresist is first coated on the barrier layer 8, and then alignment, exposure, development, and pattern detection are sequentially performed to form the source and drain regions of the device, and then the source and drain regions are bombarded with oxygen plasma for 4 minutes to reduce the ohmic contact resistance of the source and drain regions;

[0106] The vacuum degree of the working chamber was set to 2.0×10 -4 Pa, the electron gun acceleration voltage is 8Kv, the electron gun beam current is 0.5A, and the evaporation time is 180s. Through electron beam evaporation E-Beam, Ti / Au with a thickness of 40 / 140nm is deposited in the source and drain regions as the source S and drain D, and then placed in a photoresist stripping solution to remove the photoresist;

[0107] The wafer with the source and drain metal deposited was placed in an annealing furnace and the temperature in the furnace was set to 830°C under N 2 Rapid annealing in an atmosphere for 40 seconds to form high-quality ohmic contacts at the contact surfaces of the source and drain metals and the barrier layer 8;

[0108] The surface of the barrier layer 8 is again photolithographically formed into a gate region, and the vacuum degree of the working chamber is set to 2.0×10 -4 Pa, the electron gun acceleration voltage is 8Kv, the electron gun beam current is 0.5A, and the evaporation time is 240s. Through electron beam evaporation E-Beam, Ni / Au with a thickness of 60 / 180nm is deposited in the gate area as the gate G to form a Schottky contact at the contact surface of the gate G and the barrier layer 8, and then it is placed in a photoresist stripping solution to remove the photoresist;

[0109] The implantation energy was set to 260 keV and the ion concentration was set to 5×10 14 cm -2 Under the process conditions, ion implantation technology is used to implant high-energy ions into the surface of the barrier layer 8 outside the active area of ​​the wafer to complete device isolation.

[0110] Step 3: Connect the surface of the barrier layer 8 to the external carrier wafer through a bonding process, and pre-treat the lower surface of the substrate 4 by thinning and polishing. Figure 2 (c).

[0111] The surface of the barrier layer 8 of the device having the substrate 4, the nucleation layer 5, the buffer layer 6, the channel layer 7, the barrier layer 8 and the source S, the drain D and the gate G is bonded to the sapphire carrier wafer by bonding glue, and pressure is applied to the lower surface of the substrate 4 for temporary bonding;

[0112] The lower surface of the SiC substrate 4 of the device temporarily bonded with the sapphire carrier wafer is thinned by grinding to reduce its thickness to 250 μm;

[0113] The lower surface of the thinned SiC substrate 4 is polished using a polishing technique to improve the smoothness and flatness of the wafer surface.

[0114] Step 4: Set up SiH 4 and NH 3 The flow rate is 20cm 3 / min、15cm 3 / min, temperature of 300°C, growth pressure of 120Pa, and RF power of 300W, a Si layer with a thickness of 500nm was deposited on the back of the SiC substrate 4 by plasma enhanced chemical vapor deposition PECVD. 3 N 4 The substrate insulating layer 41, such as Figure 2 (d).

[0115] Step 5: Deposit a metal electrode layer 31 on the substrate insulating layer 41, such as Figure 2 (e).

[0116] The surface of the substrate insulating layer 41 is photolithographically processed, that is, a layer of photoresist is firstly coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are sequentially performed to form an area for depositing a metal electrode;

[0117] The vacuum degree of the working chamber was set to 2.5×10 -4 Pa, the electron gun acceleration voltage is 9Kv, the electron gun beam current is 0.7A, and the evaporation time is 1200s. By electron beam evaporation E-Beam, Cu / Au with a thickness of 1000 / 80nm is deposited in the area where the upper metal electrode is deposited as the upper metal electrode layer 31, and then the wafer is placed in a photoresist stripping solution to remove the photoresist. The top view is shown in Figure 3(a).

[0118] Step 6: Deposit the thermoelectric cooling module 3 on the upper metal electrode layer 31, such as Figure 2 (f).

[0119] The surface of the upper metal electrode layer 31 is photolithographically processed, that is, a layer of photoresist is first coated on the upper metal electrode layer 31, and then alignment, exposure, development, and pattern detection are sequentially performed to form a plurality of regions for depositing N-type thermoelectric materials, each region having a side length of 120 μm and a spacing of 155 μm;

[0120] The flow rate ratio of DipTe and TMBi was set to 5, the flow rate ratio of DipTe and DESe was set to 2, the temperature was set to 420°C, and the growth pressure was set to 400 mbar. N-type Bi with a thickness of 30 μm was deposited in the area where the N-type thermoelectric material was deposited by metal organic chemical vapor deposition MOCVD technology. 2 (TeSe) 3As an N-type thermoelectric material layer, the wafer is then placed in a photoresist stripping solution to remove the photoresist;

[0121] The surface of the upper metal electrode layer 31 is again photolithographically processed to form a plurality of regions for depositing P-type thermoelectric material, each region having a side length of 120 μm and a distance of 15 μm from an adjacent N-type thermoelectric material layer and a distance of 20 μm from an adjacent N-type thermoelectric material layer;

[0122] The flow rate ratio of DipTe and TMBi is set to 4, the flow rate ratio of TMBi and TDSb is set to 2, the temperature is set to 350°C, and the growth pressure is set to 400mbar. P-type (BiSb) with a thickness of 30μm is deposited in the area where the P-type thermoelectric material is deposited by metal organic chemical vapor deposition MOCVD technology. 2 Te 3 As a P-type thermoelectric material layer, the wafer is then placed in a photoresist stripping solution to remove the photoresist, completing the manufacture of the thermoelectric cooling module 3, whose top view is shown in Figure 3(b).

[0123] Step 7: Deposit insulating support material 33 on the periphery of the thermoelectric cooling module 3, such as Figure 2 (g).

[0124] The surface of the substrate insulating layer 41 is again subjected to photolithography, that is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form an area for depositing the insulating support material 33;

[0125] Setting up SiH 4 and NH 3 The flow rate is 30cm 3 / min、20cm 3 / min, temperature of 400℃, growth pressure of 150Pa, and RF power of 500W, a Si layer was deposited in the area where the insulating support material was deposited until its height was flush with the thermoelectric cooling module 3 by plasma enhanced chemical vapor deposition PECVD technology. 3 N 4 As insulating support material 33, the wafer is then placed in a photoresist stripping solution to remove the photoresist, and its top view is shown in Figure 3(c).

[0126] Step 8: Deposit a metal electrode layer 32 on the thermoelectric cooling module 3 and the insulating support material 33, such as Figure 2 (h).

[0127] Photolithography is performed on the surfaces of the thermoelectric cooling module 3 and the insulating support material 33, that is, a layer of photoresist is first coated on the thermoelectric cooling module 3 and the insulating support material 33, and then alignment, exposure, development, and pattern detection are performed in sequence to form an area for depositing a lower metal electrode layer;

[0128] The vacuum degree of the working chamber was set to 2.5×10 -4 Pa, the electron gun acceleration voltage is 9Kv, the electron gun beam current is 0.7A, and the evaporation time is 1200s. By electron beam evaporation E-Beam, Au / Cu with a thickness of 80 / 1000nm is deposited in the area where the lower metal electrode is deposited as the lower metal electrode layer 32, and then the wafer is placed in a photoresist stripping solution to remove the photoresist. The top view is shown in Figure 3(d).

[0129] Step 9: Bond the heat sink layer 1 to the surface of the lower metal electrode layer 32 through the heat transfer interface layer 2, and remove the carrier wafer, such as Figure 2 (i).

[0130] By using a spin coating process, epoxy resin is dripped onto an aluminum-silicon-carbon alloy heat sink 1 with a thickness of 1 mm and then rotated at a speed of 4000 r / s for 40 seconds to obtain an epoxy resin film with a thickness of 20 μm as a heat transfer interface layer 2, and the surface of the lower metal electrode layer 32 is bonded to the epoxy resin film, and then placed in an oven at 150° C. to cure the epoxy resin film for 20 minutes to complete the heat sink connection;

[0131] The sapphire carrier temporarily bonded to the surface of the barrier layer is removed by using a debonding glue to complete the preparation of the device.

[0132] Example 3: In the thermoelectric cooling module, the N-type thermoelectric material layer is PbTe and the P-type thermoelectric material layer is Bi 2 Te 3 , with a thickness of 300μm, a buffer layer of AlN, and a GaN Schottky diode SBD with a thickness of 5μm.

[0133] Step A: epitaxially depositing a group III nitride material on the front side of the SiC substrate 4 .

[0134] A SiC substrate 4 with a size of 6 inches and a thickness of 600 μm is selected;

[0135] A1) using metal organic chemical vapor deposition (MOCVD) technology, epitaxially growing an AlN nucleation layer 5 with a thickness of 200 nm on the front side of the SiC substrate 4, wherein the process conditions of the metal organic chemical vapor deposition (MOCVD) are as follows:

[0136] NH 3 The flow rate ratio of TMAl is 2500.

[0137] The temperature is 600℃,

[0138] The growth pressure is 100 mbar;

[0139] A2) using metal organic chemical vapor deposition (MOCVD) technology, epitaxially growing an AlN buffer layer 6 with a thickness of 5 μm on the AlN nucleation layer 5, wherein the process conditions of the metal organic chemical vapor deposition (MOCVD) are as follows:

[0140] NH 3 The flow rate ratio of TMAl is 3000.

[0141] The temperature is 750℃,

[0142] The growth pressure is 250mbar;

[0143] A3) using metal organic chemical vapor deposition (MOCVD) technology, epitaxially growing a 1000 nm thick, non-intentionally doped GaN channel layer 7 on the AlN buffer layer 6, wherein the process conditions of the metal organic chemical vapor deposition (MOCVD) are as follows:

[0144] NH 3 The flow rate ratio of TMGa is 2500.

[0145] The temperature is 1100℃,

[0146] The growth pressure is 200mbar;

[0147] A4) using metal organic chemical vapor deposition (MOCVD) technology, epitaxially growing an AlGaN barrier layer 8 with an Al component of 0.25 and a thickness of 30 nm on the GaN channel layer 7, wherein the process conditions of the metal organic chemical vapor deposition (MOCVD) are as follows:

[0148] NH 3 The flow rate ratio of TMGa is 2000.

[0149] The flow rate ratio of TMGa and TMAl is 4,

[0150] The temperature is 1100℃,

[0151] The growth pressure was 150 mbar.

[0152] Step B: depositing cathode and anode metal electrodes on the surface of the barrier layer 8 and performing ion implantation to achieve device isolation.

[0153] B1) performing photolithography on the surface of the barrier layer 8, i.e., first coating a layer of photoresist on the barrier layer 8, and then sequentially performing alignment, exposure, development, and pattern detection to form a cathode region of the device, and then bombarding the cathode region with oxygen plasma for 5 minutes to reduce the ohmic contact resistance of the cathode region;

[0154] B2) Ti / Au with a thickness of 80 / 200 nm is deposited in the cathode region as a cathode by electron beam evaporation E-Beam, and then the wafer is placed in a photoresist stripping solution to remove the photoresist, wherein the process conditions of electron beam evaporation E-Beam are as follows:

[0155] The vacuum degree of the working chamber is 2.0×10 -4 Pa,

[0156] The electron gun acceleration voltage is 10Kv.

[0157] The electron gun beam current is 0.2A.

[0158] The evaporation time is 280s;

[0159] B3) Place the above-mentioned cathode metal-deposited wafer into an annealing furnace at N 2 Rapid annealing for 35 seconds in an environment, with the annealing temperature in the furnace being 860° C., so as to form an ohmic contact at the contact surface between the cathode and the barrier layer 8;

[0160] B4) The surface of the barrier layer 8 is again photolithographically processed to form an anode region, and Ni / Au with a thickness of 80 / 300 nm is deposited in the anode region as an anode by electron beam evaporation E-Beam to form a Schottky contact at the contact surface between the anode and the barrier layer 8, and then the wafer is placed in a photoresist stripping solution to remove the photoresist, wherein the process conditions of the electron beam evaporation E-Beam are as follows:

[0161] The vacuum degree of the working chamber is 2.0×10 -4 Pa,

[0162] The electron gun acceleration voltage is 10Kv.

[0163] The electron gun beam current is 0.2A.

[0164] The evaporation time is 380s;

[0165] B5) Using ion implantation technology, high-energy ions are implanted into the surface of the barrier layer 8 outside the active area of ​​the wafer to complete device isolation, wherein the process conditions of the ion implantation are as follows:

[0166] The injection energy is 320keV,

[0167] The ion concentration is 8×10 14 cm -2 .

[0168] Step C: Connect the surface of the barrier layer 8 to the external carrier wafer through a bonding process, and perform pretreatment of grinding thinning and surface polishing on the lower surface of the substrate 4.

[0169] C1) bonding the surface of the barrier layer 8 of the device having the substrate 4, the nucleation layer 5, the buffer layer 6, the channel layer 7, the barrier layer 8 and the cathode and the anode to the sapphire carrier wafer by bonding glue, and applying pressure to the lower surface of the substrate 4 for temporary bonding;

[0170] C2) grinding and thinning the lower surface of the SiC substrate 4 of the device temporarily bonded with the sapphire carrier wafer to reduce its thickness to 350 μm;

[0171] C3) The lower surface of the thinned SiC substrate 4 is polished using a polishing technique to improve the smoothness and flatness of the wafer surface.

[0172] Step D: Deposit Si with a thickness of 1 μm on the back of the SiC substrate 4 by plasma enhanced chemical vapor deposition (PECVD). 3 N 4 The substrate insulating layer 41, wherein the process conditions of plasma enhanced chemical vapor deposition PECVD are as follows:

[0173] S H 4 and NH 3 The flow rate is 30cm 3 / min、20cm 3 / min,

[0174] The temperature is 400℃,

[0175] The growth pressure is 150Pa.

[0176] The RF power is 500W.

[0177] Step E: depositing an upper metal electrode layer 31 on the substrate insulating layer 41 .

[0178] E1) performing photolithography on the surface of the substrate insulating layer 41, that is, first coating a layer of photoresist on the substrate insulating layer 41, and then sequentially performing alignment, exposure, development, and pattern detection to form an area for depositing a metal electrode;

[0179] E2) Using electron beam evaporation E-Beam, a Cu / Ni layer with a thickness of 2000 / 100 nm is deposited in the area where the upper metal electrode is deposited as the upper metal electrode layer 31, and then the wafer is placed in a photoresist stripping solution to remove the photoresist. The process conditions of the electron beam evaporation E-Beam are as follows:

[0180] The vacuum degree of the working chamber is 2.5×10 -4 Pa,

[0181] The electron gun acceleration voltage is 10Kv.

[0182] The electron gun beam current is 0.5A.

[0183] The evaporation time is 2100s.

[0184] Step F: depositing the thermoelectric cooling module 3 on the upper metal electrode layer 31 .

[0185] F1) performing photolithography on the surface of the upper metal electrode layer 31, i.e., first coating a layer of photoresist on the upper metal electrode layer 31, and then sequentially performing alignment, exposure, development, and pattern detection to form a plurality of regions for depositing N-type thermoelectric materials, each region having a side length of 200 μm and a spacing of 250 μm;

[0186] F2) depositing N-type PbTe with a thickness of 300 μm as an N-type thermoelectric material layer in the area where the N-type thermoelectric material is deposited by metal organic chemical vapor deposition (MOCVD) technology, and then placing the wafer in a photoresist stripping solution to remove the photoresist, wherein the process conditions of metal organic chemical vapor deposition (MOCVD) are as follows:

[0187] The flow rate ratio of DipTe and TEL is 2,

[0188] The temperature is 400℃,

[0189] The growth pressure is 450mbar;

[0190] F3) performing photolithography again on the surface of the upper metal electrode layer 31 to form a plurality of regions for depositing P-type thermoelectric material, each region having a side length of 200 μm and being 20 μm away from an adjacent N-type thermoelectric material layer and 30 μm away from an adjacent N-type thermoelectric material layer;

[0191] F4) Using metal organic chemical vapor deposition (MOCVD) technology, a P-type Bi with a thickness of 300 μm is deposited in the area where the N-type thermoelectric material is deposited. 2 Te 3 As a P-type thermoelectric material layer, the wafer is then placed in a photoresist stripping solution to remove the photoresist, completing the manufacture of the thermoelectric cooling module 3, wherein the process conditions of metal organic chemical vapor deposition MOCVD are as follows:

[0192] When the flow rate ratio of DipTe and TMBi is 6,

[0193] The temperature is 500℃,

[0194] The growth pressure is 600 mbar.

[0195] Step G: depositing insulating support material 33 on the periphery of the thermoelectric cooling module 3 .

[0196] G1) Photolithography is performed on the surface of the substrate insulating layer 41. A layer of photoresist is first coated on the substrate insulating layer 41 by spin coating technology, and then alignment, exposure, development, and pattern detection are performed in sequence. In the area where the insulating support material needs to be deposited, the photoresist with a height flush with the thermoelectric cooling module is retained as the insulating support material, wherein the process conditions of the spin coating are as follows:

[0197] The speed is 2000r / s,

[0198] The spin coating time was 35 s;

[0199] G2) hard-baking the wafer on which the insulating support material 33 is deposited so that the photoresist will not dissolve in the photoresist stripping solution or other etching solvents used subsequently, wherein the hard-baking process conditions are as follows:

[0200] The baking temperature is 240℃.

[0201] The baking time is 10 minutes.

[0202] Step H: depositing a metal electrode layer on the thermoelectric cooling module 3 and the insulating support material 33 .

[0203] H1) performing photolithography on the surface of the thermoelectric cooling module 3 and the insulating support material 33, that is, first coating a layer of photoresist on the thermoelectric cooling module 3 and the insulating support material 33, and then sequentially performing alignment, exposure, development, and pattern detection to form an area for depositing the lower metal electrode layer 32;

[0204] H2) Depositing Ni / Cu with a thickness of 100 / 2000 nm as the lower metal electrode layer 32 in the area where the lower metal electrode is deposited by electron beam evaporation E-Beam, and then placing the wafer in a photoresist stripping solution to remove the photoresist, wherein the process conditions of electron beam evaporation E-Beam are as follows:

[0205] The vacuum degree of the working chamber is 2.5×10 -4 Pa,

[0206] The electron gun acceleration voltage is 10Kv.

[0207] The electron gun beam current is 0.5A.

[0208] The evaporation time is 2100s.

[0209] Step I: Bond the heat sink layer 1 to the surface of the lower metal electrode layer 32 via the heat transfer interface layer 2 and remove the carrier wafer.

[0210] I1) using a spin coating process, dripping polyolefin resin on an AlN ceramic heat sink 1 with a thickness of 5 mm, and then rotating at a speed of 3000 r / s for 30 seconds to obtain a polyolefin resin film with a thickness of 100 μm as a heat transfer interface layer 2, bonding the lower metal electrode layer surface 32 and the polyolefin resin film, and then putting it into an oven at 250° C. to cure the polyolefin resin film for 25 minutes to complete the heat sink connection;

[0211] I2) Using a debonding glue solution, the sapphire carrier temporarily bonded to the surface of the barrier layer is removed to obtain a GaN Schottky diode SBD, such as Figure 4 shown.

[0212] The above descriptions are only three specific examples of the present invention and do not constitute any limitation to the present invention. Obviously, after understanding the content and principle of the present invention, professionals in this field may make various modifications and changes in form and details without deviating from the principle and result of the present invention. For example, in addition to copper-tungsten alloy, aluminum-silicon-carbon alloy, aluminum-silicon-carbon alloy, and AlN ceramics, the heat sink layer can also use copper-molybdenum alloy, aluminum-magnesium-silicon alloy, SiC ceramics, and high thermal conductivity metals; in addition to Bi 2 Te 3 / Sb 2 Te 3 、Bi 2 (TeSe) 3 / (BiSb) 2 Te 3 、PbTe / Bi 2 Te 3 , other materials with thermoelectric effect can also be used; in addition to Au / Cu, Ni / Cu, Ni / Au, the upper and lower metal electrode layers can also use other metals that match the thermoelectric materials, but these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A GaN device for thermoelectric cooling and enhanced heat dissipation, comprising, from bottom to top: a heat sink layer (1), a heat transfer interface layer (2), a substrate (4), a nucleation layer (5), a buffer layer (6), a channel layer (7), a barrier layer (8) and a metal electrode, characterized in that: A plurality of sequentially arranged thermoelectric cooling modules (3) are provided between the heat transfer interface layer (2) and the substrate (4), each thermoelectric cooling module comprising an N-type thermoelectric material layer and a P-type thermoelectric material layer corresponding to each other, and upper and lower surfaces thereof are respectively provided with an upper metal electrode layer (31) and a lower metal electrode layer (32) which are patterned in series, and are used to connect the N-type thermoelectric material layer and the P-type thermoelectric material layer in series and apply a voltage; and the outer periphery thereof is wrapped with an insulating support material (33) to support the deposition and patterning of the lower metal electrode layer (32) and to achieve electrical isolation between adjacent thermoelectric cooling modules (3); A substrate insulating layer (41) is provided on the lower surface of the substrate (4) for achieving electrical isolation between the substrate (4) and the thermoelectric cooling module (3).

2. The device according to claim 1, characterized in that: The N-type thermoelectric material layer in the thermoelectric cooling module (3) is made of any one of Bi2Te3, Bi2(TeSe)3, PbTe or other N-type materials with thermoelectric effect, and has a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm; The P-type thermoelectric material layer in the thermoelectric cooling module (3) is made of any one of Sb2Te3, (BiSb)2Te3, Bi2Te3 or other P-type materials with thermoelectric effect, and has a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm; The spacing between the N-type thermoelectric material layer and the P-type thermoelectric material layer in the single thermoelectric cooling module is 10-20 μm, and the spacing between two adjacent thermoelectric cooling modules is 10-30 μm.

3. The device according to claim 1, characterized in that: The patterned upper metal electrode layer (31) and the lower metal electrode layer (32) are made of Ni / Au, Au / Cu, Ni / Cu or other metals matching the thermoelectric material, and have a thickness of 40-100 / 200-2000 nm, and are used to apply voltage to the thermoelectric cooling module to form a current, so that a temperature difference is formed between the upper and lower surfaces of the thermoelectric cooling module, thereby improving the heat dissipation capacity of the device; The substrate insulating layer (41) is made of SiO2 or Si3N4 and has a thickness of 0.1 to 1 μm; The insulating support material (33) is any one of SiO2, Si3N4 or photoresist, and its thickness is the sum of the thickness of the upper metal electrode layer (31) and the thermoelectric cooling module (3).

4. The device according to claim 1, characterized in that: The heat transfer interface layer (2) is made of any one of silica gel, silicone grease, epoxy resin or phase change material, and has a thickness of 20 to 500 μm, wherein the phase change material includes polyolefin resin and acrylic resin; The heat sink layer (1) is made of any one of copper alloy, aluminum alloy, high thermal conductivity metal or high thermal conductivity ceramic material, and has a thickness of 0.1 to 10 mm, wherein the copper alloy includes copper-tungsten alloy and copper-molybdenum alloy, the aluminum alloy includes aluminum-magnesium-silicon alloy and aluminum-silicon-carbon alloy, the high thermal conductivity metal includes W, Mo, Cu, Al, and the high thermal conductivity ceramic material includes SiC ceramic and AlN ceramic.

5. The device according to claim 1, characterized in that: The substrate (4) is made of Si or SiC and has a thickness of 50 to 500 μm; The nucleation layer (5) is made of AlN and has a thickness of 20 to 200 nm; The buffer layer (6) is made of any one of GaN, AlN or AlGaN, and has a thickness of 0.1 to 5 μm; The channel layer (7) is made of GaN and has a thickness of 20 to 1000 nm; The barrier layer (8) is made of AlGaN and has a thickness of 10 to 30 nm.

6. A method for preparing a GaN device with enhanced heat dissipation by electrothermal cooling, characterized in that: The following steps are involved: S1: epitaxially depositing a nucleation layer, a buffer layer, a channel layer, and a barrier layer in sequence on the upper surface of the substrate by metal organic chemical vapor deposition (MOCVD); S2: Electrode metal is first deposited on the barrier layer by electron beam evaporation E-Beam, and then ion implantation is performed to achieve device isolation; S3: connecting the surface of the barrier layer to an external carrier wafer through a bonding process, and pre-treating the lower surface of the substrate by thinning and polishing the surface; S4: depositing a substrate insulating layer on the lower surface of the pretreated substrate by plasma enhanced chemical vapor deposition (PECVD); S5: depositing a metal electrode layer on the substrate insulating layer by electron beam evaporation E-Beam; S6: depositing an N-type thermoelectric material layer and a P-type thermoelectric material layer on the upper metal electrode layer by photolithography and metal organic chemical vapor deposition (MOCVD) to form a thermoelectric cooling module; S7: depositing an insulating support material on the periphery of the thermoelectric cooling module by plasma enhanced chemical vapor deposition (PECVD) or spin coating; S8: depositing a metal electrode layer on the thermoelectric cooling module and the insulating support material by electron beam evaporation E-Beam; S9: Bonding the heat sink material to the surface of the lower metal electrode layer through the heat transfer interface material, and removing the carrier wafer to complete the device manufacturing.

7. The method according to claim 6, characterized in that: The process conditions of the metal organic chemical vapor deposition MOCVD in step S1 are as follows: TMGa is used as Ga precursor, TMAl is used as Al precursor, NH3 is used as nitrogen source, and H2 and N2 mixed gas is used as carrier gas; The flow rate ratio of NH3 and TMAl for depositing AlN is 1000-3000, the temperature is maintained at 450-750°C, and the growth pressure is maintained at 50-250 mbar; The flow rate ratio of NH3 and TMGa for depositing GaN is 1500-2500, the temperature is maintained at 900-1100°C, and the growth pressure is maintained at 50-200mbar; The flow rate ratio of NH3 and TMGa for depositing AlGaN is 1000-2000, the flow rate ratio of TMGa and TMAl is 4-20, the temperature is maintained at 800-1100°C, and the growth pressure is maintained at 50-150mbar.

8. The method according to claim 6, characterized in that: The process conditions of the metal organic chemical vapor deposition MOCVD in step S6 are as follows: TMBi was used as a precursor of Bi, TDSb as a precursor of Sb, DipTe as a precursor of Te, TEL as a precursor of Pb, DESe as a precursor of Se, and high-purity H2 as a carrier gas; The flow rate ratio of DipTe and TMBi for depositing Bi2Te3 is 2-10, the temperature is maintained at 200-500°C, and the growth pressure is maintained at 300-600 mbar; The flow rate ratio of DipTe and TDSb for depositing Sb2Te3 is 1 to 6, the temperature is maintained at 250 to 450°C, and the growth pressure is maintained at 200 to 500 mbar; The flow rate ratio of DipTe and TEL for depositing PbTe is 1 to 3, the temperature is maintained at 300 to 500 °C, and the growth pressure is maintained at 200 to 450 mbar; The flow rate ratio of DipTe to TMBi for depositing Bi2(TeSe)3 is 1 to 8, the flow rate ratio of DipTe to DESe is 1 to 3, the temperature is maintained at 220 to 600°C, and the growth pressure is maintained at 200 to 600 mbar; The flow rate ratio of DipTe and TMBi for depositing (BiSb)2Te3 is 1-5, the flow rate ratio of TMBi and TDSb is 2-4, the temperature is maintained at 200-550°C, and the growth pressure is maintained at 300-500 mbar.

9. The method according to claim 6, characterized in that In step S4 and step S7, the plasma enhanced chemical vapor deposition PECVD process conditions are as follows: SiO2 deposition uses SiH4 and N2O as precursor gases, with a flow rate of 50-80 cm 3 / min, 160~200cm 3 / min, the temperature was maintained at 250-300°C, the growth pressure was maintained at 80-100Pa, and the RF power was set to 60-100W; Deposition of Si3N4 uses SiH4 and NH3 as precursor gases, with a flow rate of 10-30 cm 3 / min, 5~20cm 3 / min, the temperature is maintained at 200-400°C, the growth pressure is maintained at 100-150Pa, and the RF power is set to 50-500W.

10. The method according to claim 6, characterized in that: The process conditions of the electron beam evaporation E-Beam in step S2 are as follows: The working room is evacuated to 2.0×10 -4 Pa, the electron gun acceleration voltage is 6-10Kv, the electron gun beam current is 0.1-1A, and the evaporation time is 80-380s; The process conditions of the electron beam evaporation E-Beam in step S5 and step S8 are as follows: The working room is evacuated to 2.5×10 -4 Pa, the electron gun acceleration voltage is 8~10Kv, the electron gun beam current is 0.4~1A, and the evaporation time is 240~2100s.

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