Package structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a packaging structure and a manufacturing method thereof. The method comprises the following steps: providing a first chip, wherein the surface of the first chip is provided with a sensing area; arranging a protective layer on one side of the first chip, which is provided with the sensing area; the protective layer at least covers the sensing area; arranging the first chip on one side of the interposer, wherein the first chip is located between the interposer and the protective layer; performing plastic package on the first chip on one side of the interposer to form a plastic package layer; removing the protective layer to expose the sensing area; wherein the plastic packaging layer covers the side wall of the first chip.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a packaging structure and a method for manufacturing the same. Background Art

[0002] With the rapid development of semiconductor packaging technology, the size of the packaging structure is getting smaller and smaller, and the integration of the packaging structure is getting higher and higher. In the chip-on-wafer-on-substrate (CoWoS) packaging, the chip surface is usually covered with plastic packaging materials, and the sensing signal that the sensor chip needs to collect cannot penetrate the plastic packaging materials. Therefore, the current packaging structure is not suitable for packaging sensor chips.

[0003] Therefore, there is an urgent need to provide a packaging structure and a manufacturing method thereof. Summary of the invention

[0004] In view of this, an embodiment of the present disclosure provides a packaging structure and a manufacturing method thereof.

[0005] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a packaging structure, the method comprising: providing a first chip, the surface of the first chip having a sensing area; setting a protective layer on a side of the first chip having the sensing area; the protective layer at least covers the sensing area; arranging the first chip on one side of an interposer, the first chip being located between the interposer and the protective layer; plastic-sealing the first chip on one side of the interposer to form a plastic-sealing layer; removing the protective layer to expose the sensing area; wherein the plastic-sealing layer covers the side wall of the first chip.

[0007] In some embodiments, a second chip is further provided on one side of the interposer, and the first chip and the second chip are provided on the same side of the interposer; the first chip is plastic-encapsulated on one side of the interposer to form a plastic-encapsulation layer, comprising: plastic-encapsulating the first chip and the second chip on one side of the interposer to form the plastic-encapsulation layer; wherein the plastic-encapsulation layer covers the side wall of the first chip and the surface of the protective layer away from the interposer, and the plastic-encapsulation layer also covers the side wall of the second chip and the surface of the second chip away from the interposer.

[0008] In some embodiments, providing a protective layer on the side of the first chip having the sensing region includes: bonding the surface of the first chip having the sensing region and the protective layer to form the protective layer on the side of the first chip having the sensing region.

[0009] In some embodiments, a protruding structure surrounding the sensing area is further provided between the first chip and the protective layer; providing the protective layer on the side of the first chip having the sensing area comprises: providing the protective layer on the side of the protruding structure away from the first chip, forming a cavity between the first chip, the protruding structure and the protective layer, and the cavity exposing the sensing area.

[0010] In some embodiments, the height of the first chip along a direction perpendicular to the interposer is less than or equal to the height of the second chip along a direction perpendicular to the interposer; the removing the protective layer to expose the sensing area includes: removing the plastic encapsulation layer covering the protective layer to expose the protective layer; debonding the first chip and the protective layer; removing the protective layer to expose the sensing area; wherein the distance between the surface of the plastic encapsulation layer covering the second chip and the interposer is greater than the distance between the surface of the first chip away from the interposer and the interposer.

[0011] In some embodiments, the height of the first chip along a direction perpendicular to the interposer is less than or equal to the height of the second chip along a direction perpendicular to the interposer; the removing the protective layer to expose the sensing area includes: removing the plastic layer covering the protective layer to expose the protective layer; removing the protective layer to expose the protruding structure and the sensing area; wherein the distance between the surface of the plastic layer covering the second chip and the interposer is greater than the distance between the surface of the first chip away from the interposer and the interposer.

[0012] In some embodiments, the height of the first chip along a direction perpendicular to the interposer is greater than the height of the second chip along a direction perpendicular to the interposer; the removing the protective layer to expose the sensing area includes: planarizing the plastic encapsulation layer and the protective layer to expose the sensing area; wherein the surface of the plastic encapsulation layer covering the second chip and the surface of the first chip away from the interposer are substantially flush.

[0013] In a second aspect, an embodiment of the present disclosure provides a packaging structure, comprising: a substrate and an interposer disposed on one side of the substrate; a first chip disposed on a side of the interposer away from the substrate, the surface of the first chip away from the interposer having a sensing area; and a plastic encapsulation layer disposed on one side of the interposer and surrounding the first chip, the plastic encapsulation layer covering the side wall of the first chip and exposing the sensing area.

[0014] In some embodiments, the packaging structure further includes: a protruding structure disposed on a surface of the first chip away from the interposer and surrounding the sensing area, and the plastic encapsulation layer covers an outer sidewall of the protruding structure and exposes an inner sidewall of the protruding structure.

[0015] In some embodiments, the packaging structure also includes: a second chip arranged on a side of the interposer away from the substrate, the first chip and the second chip are arranged on the same side of the interposer, and the plastic encapsulation layer covers the side wall of the second chip and the surface of the second chip away from the interposer; wherein the height of the first chip along a direction perpendicular to the interposer is less than or equal to the height of the second chip along a direction perpendicular to the interposer; and the distance between the surface of the plastic encapsulation layer covering the second chip and the interposer is greater than the distance between the surface of the first chip away from the interposer and the interposer.

[0016] In some embodiments, the packaging structure also includes: a second chip arranged on a side of the interposer away from the substrate, the first chip and the second chip are arranged on the same side of the interposer, and the plastic encapsulation layer covers the side wall of the second chip and the surface of the second chip away from the interposer; wherein the height of the first chip along a direction perpendicular to the interposer is greater than the height of the second chip along a direction perpendicular to the interposer; the surface of the plastic encapsulation layer covering the second chip is substantially flush with the surface of the first chip away from the interposer.

[0017] In some embodiments, the interposer is provided with a plurality of conductive structures extending along the thickness direction of the interposer, the conductive structure having a first end and a second end relatively arranged along the extension direction, the first end of the conductive structure being coupled to the first chip, and the second end of the conductive structure being coupled to the substrate through a bump.

[0018] The disclosed embodiment provides a packaging structure and a manufacturing method thereof. In the disclosed embodiment, the surface of the first chip has a sensing area; a protective layer is provided on one side of the first chip, and the protective layer at least covers the sensing area; the first chip is provided on one side of the interposer, and after the first chip is plastic-sealed on the side of the interposer, the protective layer is removed to expose the sensing area; wherein the plastic-sealing layer covers the side wall of the first chip. In this way, the protective layer can protect the sensing area of ​​the first chip during the process of forming the plastic-sealing layer, and the sensing area can be exposed after the protective layer is removed, so that the first chip can receive the sensing signal through the sensing area; and the plastic-sealing layer can plastic-seale the side wall of the first chip to better protect the performance and stability of the first chip during use. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a process for manufacturing a packaging structure provided by an embodiment of the present disclosure;

[0020] FIG. 2A to FIG. 2E A cross-sectional view of the packaging structure provided by the first embodiment during the manufacturing process;

[0021] Figure 3A A cross-sectional view of a first chip provided with a protruding structure according to an embodiment of the present disclosure;

[0022] Figure 3B A top view of a first chip provided with a protruding structure according to an embodiment of the present disclosure Figure 1 ;

[0023] Figure 3C A second top view of a first chip provided with a protruding structure according to an embodiment of the present disclosure;

[0024] Figure 4A A cross-sectional view of a first chip provided with a protective layer according to an embodiment of the present disclosure Figure 1 ;

[0025] Figure 4B A second cross-sectional view of a first chip provided with a protective layer according to an embodiment of the present disclosure;

[0026] Figure 4C A third cross-sectional view of a first chip provided with a protective layer according to an embodiment of the present disclosure;

[0027] Figure 4D A fourth cross-sectional view of a first chip provided with a protective layer according to an embodiment of the present disclosure;

[0028] FIG. 5A to FIG. 5C A cross-sectional view of the packaging structure provided by the second embodiment during the manufacturing process;

[0029] 6A to 6F A cross-sectional view of the packaging structure provided by the third embodiment during the manufacturing process;

[0030] 7A to 7D A cross-sectional view of the packaging structure provided in the fourth embodiment during the manufacturing process.

[0031] The figure includes: 200, packaging structure; 202, first chip; 204, sensing area; 206, protruding structure; 208, protective layer; 210, cavity; 212, second chip; 214, intermediate layer; 216, conductive structure; 218, first end; 220, second end; 222, bump; 224, plastic layer; 226, substrate; 302, protruding structure; 304, protruding structure; 306, protruding structure; 402, raised structure; 404, protective layer; 406, cavity; 408, protective layer; 410, cavity; 412, first annular groove; 414, protective layer; 416, cavity; 418, recessed area; 420, raised structure; 422, second annular groove; 424, cavity; 500, packaging structure; 502, first chip; 504, sensing area; 506, raised structure; 508, protective layer protective layer; 510, cavity; 512, second chip; 514, intermediary layer; 516, conductive structure; 518, first end; 520, second end; 522, bump; 524, plastic layer; 526, substrate; 600, packaging structure; 602, first chip; 604, sensing area; 608, protective layer; 612, second chip; 614, intermediary layer; 616, conductive structure; 618, first end; 6 20, second end; 622, bump; 624, plastic layer; 626, substrate; 628, bonding layer; 700, packaging structure; 702, first chip; 704, sensing area; 708, protection layer; 712, second chip; 714, intermediate layer; 716, conductive structure; 718, first end; 720, second end; 722, bump; 724, plastic layer; 726, substrate; 728, bonding layer. DETAILED DESCRIPTION

[0032] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0034] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0036] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0039] refer to Figure 1 , Figure 1 A schematic flow chart of a method for manufacturing a packaging structure provided in an embodiment of the present disclosure.

[0040] like Figure 1 As shown, an embodiment of the present disclosure provides a method for manufacturing a packaging structure, the method comprising:

[0041] Step S101: providing a first chip, wherein a surface of the first chip has a sensing area.

[0042] Step S102: a protective layer is provided on a side of the first chip having the sensing area, wherein the protective layer at least covers the sensing area.

[0043] Step S103: placing a first chip on one side of the interposer, wherein the first chip is located between the interposer and the protective layer.

[0044] Step S104: plastic-encapsulating the first chip on one side of the interposer to form a plastic-encapsulation layer.

[0045] Step S105: removing the protective layer to expose the sensing area; wherein the plastic packaging layer covers the side wall of the first chip.

[0046] refer to FIG. 2A to FIG. 2E , FIG. 2A to FIG. 2E This is a cross-sectional view of the packaging structure provided in the first embodiment during the manufacturing process. Figure 1 as well as FIG. 2A to FIG. 2E , and describes in detail the manufacturing process of the packaging structure.

[0047] Before introducing the embodiments of the present disclosure, various directions that may be involved in the following are defined. Intersecting X-direction and Y-direction are defined in the plane where the substrate is located, and the thickness direction of the substrate is defined as Z-direction. In this way, the X-direction and the Y-direction are parallel to the substrate, and the Z-direction is perpendicular to the substrate. In some embodiments, the X-direction and the Y-direction are perpendicular to each other, so that the X-direction, the Y-direction, and the Z-direction are perpendicular to each other.

[0048] like Figure 2A As shown, in step S101 , a first chip 202 is provided, and a surface of the first chip 202 has a sensing region 204 . The surface of the first chip 202 is also provided with a protruding structure 206 surrounding the sensing region 204 .

[0049] Here, the first chip 202 has a top surface and a bottom surface opposite to each other along the Z direction. The surface with the sensing area 204 can be called the top surface of the first chip 202 , and the other surface opposite to the top surface is the bottom surface of the first chip 202 .

[0050] Figure 3A A cross-sectional view of a first chip provided with a protruding structure according to an embodiment of the present disclosure, Figure 3B and Figure 3C FIG. 1 is a top view of a first chip provided with a protruding structure according to an embodiment of the present disclosure. Figure 3A As shown, the top surface of the first chip 202 is provided with a sensing area 204, and the first chip 202 can receive the sensing signal through the sensing area 204 and process the sensing signal. The top surface of the first chip 202 is also provided with a protruding structure 302 surrounding the sensing area 204; wherein the protruding structure 302 protrudes from the top surface of the first chip 202.

[0051] Here, the protruding structure 302 has a top surface and a bottom surface that are oppositely arranged along the Z direction, the top surface of the protruding structure 302 is far away from the first chip 202, and the bottom surface of the protruding structure 302 is close to the first chip 202. The protruding structure 302 has an outer side wall and an inner side wall that are oppositely arranged along the X direction, the outer side wall of the protruding structure 302 is far away from the sensing area 204, and the inner side wall of the protruding structure 302 is close to the sensing area 204. The top surface of the protruding structure 302 is higher than the top surface of the first chip 202.

[0052] like Figure 3A As shown, in some embodiments, the orthographic projection shape of the outer sidewall (or inner sidewall) of the protrusion structure 302 on the XY plane may include a circle, an ellipse, a square or other shapes. Figure 3B It is shown that the orthographic projection shape of the outer wall of the protruding structure 304 on the XY plane is a circle. Figure 3C The orthographic projection shape of the outer wall of the protruding structure 306 on the XY plane is a square. The present disclosure has no special limitation on the orthographic projection shape of the outer wall (or inner wall) of the protruding structure on the XY plane, as long as the protruding structure surrounds the sensing area.

[0053] like Figure 3A As shown, in some embodiments, the orthographic projection shape of the protrusion structure 302 on the XZ plane may include a rectangle, a trapezoid, or other shapes. Figure 3A The orthographic projection shape of the protruding structure 302 on the XZ plane is shown as a rectangle. The present disclosure has no special limitation on the orthographic projection shape of the protruding structure 302 on the XZ plane, as long as the protruding structure 302 protrudes from the top surface of the first chip 202 .

[0054] In some embodiments, the top surface of the first chip 202 may be micro-machined to form the protruding structure 302. In other embodiments, after the protruding structure 302 is manufactured, the protruding structure 302 may be fixed to the top surface of the first chip 202 by, for example, gluing. The present disclosure does not specifically limit the process for manufacturing the protruding structure 302.

[0055] In some embodiments, the first chip 202 may include at least one of the following: a microelectromechanical system (MEMS) chip, a photosensitive chip, a gas-sensitive chip, and a pressure-sensitive chip.

[0056] Still Figure 2A As shown, in step S102, a protective layer 208 is disposed on the side of the first chip 202 having the sensing region 204, and the protective layer 208 at least covers the sensing region 204, that is, the protective layer 208 is disposed on the side of the protruding structure 206 away from the first chip 202, and a cavity 210 is formed between the first chip 202, the protruding structure 206 and the protective layer 208, and the cavity 210 exposes the sensing region 204. The orthographic projection of the sensing region 204 on the XY plane is within the orthographic projection range of the protective layer 208 on the XY plane.

[0057] Here, the outer contour of the orthographic projection of the protruding structure 206 on the XY plane is within the orthographic projection range of the protection layer 208 on the XY plane. In other words, the size of the outer sidewall of the protruding structure 206 along the X direction is smaller than the size of the protection layer 208 along the X direction. In this way, the top surface of the first chip 202 and the protection layer 208 form two surfaces of the cavity 210 that are opposite to each other, and the protruding structure 206 forms the sidewall of the cavity 210.

[0058] FIG. 4A to FIG. 4D A cross-sectional view of a first chip provided with a protective layer according to an embodiment of the present disclosure. Figure 4A As shown, in some embodiments, the surface of the protection layer 404 close to the protruding structure 402 is a flat surface, wherein a cavity 406 is formed between the protection layer 404, the protruding structure 402 and the first chip 202. Here, the protection layer 404 can be placed directly on the protruding structure 402.

[0059] Here, the dimensions of the cavity 406 along the X and Y directions are the same as the dimensions of the inner sidewall of the protruding structure 402 along the X and Y directions, and the height of the cavity 406 along the Z direction is the height of the protruding structure 402 along the Z direction.

[0060] In the disclosed embodiment, the protective layer can protect the sensing area of ​​the first chip in a non-contact manner, and the sensing area can be exposed after the protective layer is subsequently removed, so that the first chip can receive the sensing signal through the sensing area.

[0061] like Figure 4B As shown, in some embodiments, the surface of the protective layer 408 close to the protruding structure 402 is further provided with a first annular groove 412, the opening of the first annular groove 412 faces the protruding structure 402, and the protruding structure 402 is embedded in the first annular groove 412; wherein a cavity 410 is formed between the protective layer 408, the protruding structure 402 and the first chip 202. Here, the protruding structure 402 and the first annular groove 412 are substantially the same in shape and size, and more specifically, the size of the protruding structure 402 along the X direction and the Y direction is substantially the same as the size of the first annular groove 412 along the X direction and the Y direction.

[0062] In some embodiments, the depth of the first annular groove 412 along the Z direction is less than the height of the protruding structure 402 along the Z direction. Here, the dimensions of the cavity 410 along the X direction and the Y direction are still substantially the same as the dimensions of the inner sidewall of the protruding structure 402 along the X direction and the Y direction, and the height of the cavity 410 along the Z direction is the difference between the height of the protruding structure 402 along the Z direction and the depth of the first annular groove 412 along the Z direction.

[0063] In the disclosed embodiment, the protruding structure is embedded in the first annular groove, which is more conducive to stably fixing the relative position between the protruding structure and the protective layer, so that the protective layer can provide non-contact protection for the sensing area of ​​the first chip. After the protective layer is removed, the sensing area can be exposed, so that the first chip can receive the sensing signal through the sensing area.

[0064] like Figure 4C As shown, in some embodiments, a first annular groove 412 is provided on the surface of the protective layer 414 close to the protruding structure 402, the opening of the first annular groove 412 faces the protruding structure 402, and the protruding structure 402 is embedded in the first annular groove 412; a recessed area 418 is also provided on the surface of the protective layer 414 close to the sensing area 204; wherein a cavity 416 is formed between the protective layer 414, the protruding structure 402 and the first chip 202, and the recessed area 418 also becomes a part of the cavity 416. Here, the protruding structure 402 and the first annular groove 412 are substantially the same in shape and size, and more specifically, the size of the protruding structure 402 along the X direction and the Y direction is substantially the same as the size of the first annular groove 412 along the X direction and the Y direction.

[0065] In some embodiments, the depth of the first annular groove 412 along the Z direction is less than the height of the protrusion structure 402 along the Z direction. A recessed area 418 is provided in the protection layer 414 to increase the height of the cavity 416 and avoid direct contact between the protection layer 414 and the sensing area 204 .

[0066] like Figure 4DAs shown, in some embodiments, the top surface of the first chip 202 is further provided with a second annular groove 422 surrounding the sensing area 204; the surface of the protective layer 404 close to the first chip 202 is further provided with a protruding structure 420, and the protruding structure 420 can be embedded in the second annular groove 422; wherein a cavity 424 is formed between the protective layer 404, the protruding structure 420 and the first chip 202. Here, the protruding structure 420 and the second annular groove 422 are substantially the same in shape and size, and more specifically, the size of the protruding structure 420 along the X direction and the Y direction is substantially the same as the size of the second annular groove 422 along the X direction and the Y direction.

[0067] In some embodiments, the depth of the second annular groove 422 along the Z direction is less than the height of the protrusion structure 420 along the Z direction.

[0068] like Figure 2B As shown, in step S103, the first chip 202 is disposed on one side of the interposer 214, and the first chip 202 is located between the interposer 214 and the protective layer 208; wherein the bottom surface of the first chip 202 is close to the interposer 214, and the top surface of the first chip 202 is away from the interposer 214. The surface of the first chip 202 away from the interposer 214 has a sensing region 204, and the surface of the first chip 202 away from the interposer 214 is also provided with a protruding structure 206 surrounding the sensing region 204. The first chip 202 can be electrically connected to the interposer 214.

[0069] Further references Figure 2B As shown, the intermediate layer 214 is provided with a plurality of conductive structures 216 extending along the Z direction, and the conductive structures 216 have a first end 218 and a second end 220 (eg, Figure 2B As shown in the dotted circle, the first end 218 of the conductive structure 216 is electrically connected to the first chip 202 .

[0070] Exemplarily, forming the interposer 214 may include the following steps: forming a photoresist layer on the interposer and patterning the photoresist layer; etching the interposer using the patterned photoresist layer to form a plurality of etching holes; filling the etching holes with a conductive material to form a conductive material layer; and planarizing the conductive material layer to form a conductive structure in the etching holes and expose the interposer.

[0071] In some embodiments, the process of forming the conductive material layer may include, but is not limited to, electroplating.

[0072] In some embodiments, the material of the conductive material layer may include, but is not limited to, a metal material, such as copper.

[0073] In some embodiments, the planarization process may include but is not limited to chemical mechanical polishing (CMP).

[0074] In some embodiments, before filling the conductive material, a dielectric layer covering the sidewalls of the etching hole may be formed, such as silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, before filling the conductive material, a barrier layer covering the sidewalls of the etching hole may be formed, such as titanium nitride.

[0075] In some embodiments, the process of forming the dielectric layer and the barrier layer may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0076] like Figure 2B As shown, a second chip 212 is also provided on one side of the interposer 214, and the first chip 202 and the second chip 212 are provided on the same side of the interposer 214; wherein the second chip 212 may also be electrically connected to the interposer 214. More specifically, the second chip 212 may also be connected to the first end 218 of the conductive structure 216 in the interposer 214. Here, the second chip 212 has a bottom surface and a top surface that are arranged opposite to each other along the Z direction, the bottom surface of the second chip 212 is close to the interposer 214, and the top surface of the second chip 212 is away from the interposer 214.

[0077] In some embodiments, the second chip 212 may include other types of chips besides the sensor chip. The second chip 212 does not need to be provided with a sensing area to receive the sensing signal, so the second chip 212 may be plastic-encapsulated to form a packaging structure. The packaging structure provided in the embodiment of the present disclosure may include only the first chip 202 (i.e., the sensor chip), or may include both the first chip 202 (i.e., the sensor chip) and the second chip 212 (i.e., the non-sensing chip).

[0078] like Figure 2C As shown, in step S104 , the first chip 202 is plastic-encapsulated on one side of the interposer 214 to form a plastic-encapsulation layer 224 ; wherein the plastic-encapsulation layer 224 covers the sidewall of the first chip 202 and the surface of the protection layer 208 away from the interposer 214 .

[0079] Here, the plastic encapsulation material can be used to cover the sidewall of the first chip 202 and the surface of the protective layer 208 away from the interposer 214 on one side of the interposer 214. The plastic encapsulation material can be, for example, based on epoxy resin, with a curing agent, a coupling agent, etc. added. The present disclosure does not specifically limit the type of plastic encapsulation material, and all materials used for plastic encapsulation in the related technical solutions can be used to form the plastic encapsulation layer in the present disclosure.

[0080] Still Figure 2C As shown, in some embodiments, step S104 includes: plastic-sealing the first chip 202 and the second chip 212 on one side of the interposer 214 to form a plastic-sealing layer 224; wherein the plastic-sealing layer 224 covers the side wall of the first chip 202 and the surface of the protective layer 208 away from the interposer 214, and the plastic-sealing layer 224 also covers the side wall of the second chip 212 and the surface of the second chip 212 away from the interposer 214.

[0081] Here, the molding layer 224 has a bottom surface and a top surface that are oppositely disposed along the Z direction. The bottom surface of the molding layer 224 contacts the intermediate layer 214 , and the top surface of the molding layer 224 is away from the intermediate layer 214 .

[0082] Here, the first chip and the second chip are arranged on the same side of the interposer, and the subsequent removal of the protective layer needs to consider the size relationship between the heights of the first chip and the second chip along the Z direction to avoid damage to the second chip during the removal of the protective layer.

[0083] In some embodiments, the height of the first chip along the Z direction is less than or equal to the height of the second chip along the Z direction. In this case, in order to avoid damaging the second chip during the process of removing the protective layer, the plastic encapsulation layer covering the protective layer and the protective layer can be removed separately to expose the protruding structure and the sensing area; wherein the plastic encapsulation layer can be in close contact with the side wall of the first chip and the outer side wall of the protruding structure and expose the sensing area of ​​the first chip, and the plastic encapsulation layer also covers the side wall and top surface of the second chip. Figure 2D and Figure 2E , detailing the process of removing the protective layer to expose the sensing area.

[0084] like Figure 2D As shown, in some embodiments, step S105 includes: the encapsulation layer 224 can be planarized to remove the encapsulation layer 224 covering the protective layer 208 to expose the protective layer 208; wherein the encapsulation layer 224 can be in close contact with the side walls of the first chip 202, the outer side walls of the protruding structure 206 and the side walls of the protective layer 208, and the encapsulation layer 224 also covers the side walls and top surface of the second chip 212.

[0085] Here, the surface of the protective layer 208 is substantially flush with the surface of the plastic encapsulation layer 224 covering the second chip 212. Substantially flush means that the surface of the protective layer 208 is flush with the surface of the plastic encapsulation layer 224 covering the second chip 212, or that the height difference along the Z direction between the surface of the protective layer 208 and the surface of the plastic encapsulation layer 224 covering the second chip 212 meets the process error range requirement.

[0086] It should be noted that Figure 2D It is shown that although the height of the first chip 202 along the Z direction is less than or equal to the height of the second chip 212 along the Z direction, the sum of the heights of the first chip 202, the protruding structure 206 and the protective layer 208 along the Z direction is still greater than the height of the second chip 212 along the Z direction. Therefore, the plastic encapsulation layer 224 can be planarized to expose the protective layer 208. If the sum of the heights of the first chip, the protruding structure and the protective layer along the Z direction is less than the height of the second chip 212 along the Z direction, it is not suitable to planarize the plastic encapsulation layer. At this time, it is necessary to remove only the part of the plastic encapsulation layer covering the protective layer and retain the part of the plastic encapsulation layer covering the top surface of the second chip to expose the protective layer.

[0087] like Figure 2E As shown, in some embodiments, step S105 includes: removing the protective layer 208 to expose the protruding structure 206 and the sensing area 204; wherein the plastic encapsulation layer 224 can still be in close contact with the sidewalls of the first chip 202 and the outer sidewalls of the protruding structure 206, and the plastic encapsulation layer 224 also covers the sidewalls and top surface of the second chip 212. At this time, the distance between the top surface of the plastic encapsulation layer 224 covering the second chip 212 and the interposer 214 is greater than the distance between the surface of the first chip 202 away from the interposer 214 and the interposer 214. In other words, the top surface of the plastic encapsulation layer 224 covering the second chip 212 is higher than the top surface of the first chip 202.

[0088] In the disclosed embodiment, the protective layer can protect the sensing area of ​​the first chip in a non-contact manner, and the sensing area can be exposed after the protective layer is subsequently removed, so that the first chip can receive the sensing signal through the sensing area. In the disclosed embodiment, the protective layer protects the sensing area of ​​the first chip in a non-contact manner, and the protective layer can be removed more easily without causing damage to the sensing area of ​​the first chip. In addition, the plastic encapsulation layer can plastic encapsulate the side wall of the first chip to better protect the performance and stability of the first chip during use.

[0089] like Figure 2EAs shown, the first end 218 of the conductive structure 216 is coupled to the first chip 202 or the second chip 212, so that the first chip 202 and the second chip 212 can be electrically connected to the interposer 214. The surface of the interposer 214 away from the first chip 202 can also be thinned to expose the second end 220 of the conductive structure 216, and a bump 222 is formed at the second end 220 of the conductive structure 216.

[0090] In some embodiments, after step S105 , the method further includes: coupling the second end 220 of the conductive structure 216 to the substrate 226 via the bump 222 .

[0091] like Figure 2E As shown, an embodiment of the present disclosure provides a packaging structure 200, which includes: a substrate 226 and an intermediate layer 214 arranged on one side of the substrate 226; a first chip 202 arranged on a side of the intermediate layer 214 away from the substrate 226, and the surface of the first chip 202 away from the intermediate layer 214 has a sensing area 204; a plastic layer 224 arranged on one side of the intermediate layer 214 and surrounding the first chip 202, and the plastic layer 224 covers the side wall of the first chip 202 and exposes the sensing area 204.

[0092] In some embodiments, the package structure 200 further includes: a protruding structure 206 disposed on a surface of the first chip 202 away from the interposer 214 and surrounding the sensing region 204, and a plastic encapsulation layer 224 covering an outer sidewall of the protruding structure 206 and exposing an inner sidewall of the protruding structure 206. Here, the plastic encapsulation layer 224 is in close contact with the sidewall of the first chip 202 and the outer sidewall of the protruding structure 206.

[0093] In some embodiments, the packaging structure 200 also includes: a second chip 212 arranged on the side of the interposer 214 away from the substrate 226, the first chip 202 and the second chip 212 are arranged on the same side of the interposer 214, and the plastic encapsulation layer 224 covers the side wall of the second chip 212 and the surface of the second chip 212 away from the interposer 214; wherein, the height of the first chip 202 along the direction perpendicular to the interposer 214 is less than or equal to the height of the second chip 212 along the direction perpendicular to the interposer 214; the distance between the top surface of the plastic encapsulation layer 224 covering the second chip 212 and the interposer 214 is greater than the distance between the surface of the first chip 202 away from the interposer 214 and the interposer 214.

[0094] In some other embodiments, the height of the first chip along the Z direction is greater than the height of the second chip along the Z direction. In this case, since the height of the first chip is greater, it can be directly flattened without damaging the second chip, and the plastic layer covering the protective layer and the protective layer are removed to expose the sensing area, and the plastic layer covering the second chip can also be removed; wherein the plastic layer can be in close contact with the side wall of the first chip and expose the sensing area of ​​the first chip, and the plastic layer also covers the side wall and top surface of the second chip. FIG. 5A to FIG. 5C , detailing the process of removing the protective layer to expose the sensing area.

[0095] like Figure 5A As shown, a first chip 502 and a second chip 512 are provided on one side of an interposer 514; wherein a surface of the first chip 502 away from the interposer 514 has a sensing region 504, and a surface of the first chip 502 away from the interposer 514 is also provided with a protruding structure 506 surrounding the sensing region 504, a cavity 510 is formed between the first chip 502, the protruding structure 506 and a protective layer 508, and the cavity 510 exposes the sensing region 504; a surface of the protruding structure 506 away from the first chip 502 is also provided with a protective layer 508.

[0096] like Figure 5B As shown, the first chip 502 and the second chip 512 are encapsulated to form an encapsulation layer 524. At this time, the encapsulation layer 524 is in close contact with the sidewalls of the first chip 502, the outer sidewalls of the protruding structure 506, and the sidewalls of the protection layer 508, and the encapsulation layer 524 also covers the sidewalls and top surface of the second chip 512.

[0097] like Figure 5C As shown, in some embodiments, step S105 includes: performing a planarization process on the plastic encapsulation layer 524, the protective layer 508 and the protruding structure 506 to expose the sensing area 504; wherein the plastic encapsulation layer 524 can still be in close contact with the side wall of the first chip 502, and the plastic encapsulation layer 524 also covers the side wall and the top surface of the second chip 512. At this time, the top surface of the plastic encapsulation layer 524 covering the second chip 512 is substantially flush with the surface of the first chip 502 away from the interposer 514. In other words, the top surface of the plastic encapsulation layer 524 covering the second chip 512 is substantially flush with the top surface of the first chip 502.

[0098] Here, the top surface of the plastic encapsulation layer 524 after planarization is substantially flush with the top surface of the first chip 502. Substantially flush means that the top surface of the plastic encapsulation layer 524 is flush with the top surface of the first chip 502, or the height difference between the top surface of the plastic encapsulation layer 524 and the top surface of the first chip 502 along the Z direction meets the process error range requirement.

[0099] In the disclosed embodiment, the protective layer can protect the sensing area of ​​the first chip in a non-contact manner, and the sensing area can be exposed after the protective layer is subsequently removed, so that the first chip can receive the sensing signal through the sensing area; and the plastic encapsulation layer can plastic-encapsulate the side wall of the first chip to better protect the performance and stability of the first chip during use.

[0100] Still refer to Figure 5C As shown, the intermediate layer 514 is provided with a plurality of conductive structures 516 extending along the Z direction, and the conductive structures 516 have a first end 518 and a second end 520 (eg, Figure 5C The first end 518 of the conductive structure 516 is coupled to the first chip 502 or the second chip 512. The interposer 514 may be thinned to expose the second end 520 of the conductive structure 516, and a bump 522 is formed at the second end 520 of the conductive structure 516.

[0101] In some embodiments, after step S105 , the method further includes: coupling the second end 520 of the conductive structure 516 to the substrate 526 via a bump 522 .

[0102] like Figure 5C As shown, an embodiment of the present disclosure provides a packaging structure 500, which includes: a substrate 526 and an intermediate layer 514 arranged on one side of the substrate 526; a first chip 502 arranged on a side of the intermediate layer 514 away from the substrate 526, and the surface of the first chip 502 away from the intermediate layer 514 has a sensing area 504; a plastic layer 524 arranged on one side of the intermediate layer 514 and surrounding the first chip 502, and the plastic layer 524 covers the side wall of the first chip 502 and exposes the sensing area 504.

[0103] In some embodiments, the packaging structure 500 also includes: a second chip 512 disposed on a side of the interposer 514 away from the substrate 526, the first chip 502 and the second chip 512 are disposed on the same side of the interposer 514, and the plastic encapsulation layer 524 covers the side walls of the second chip 512 and the surface of the second chip 512 away from the interposer 514; wherein the height of the first chip 502 along a direction perpendicular to the interposer 514 is greater than the height of the second chip 512 along a direction perpendicular to the interposer 514; and the surface of the plastic encapsulation layer 524 covering the second chip 512 is substantially flush with the surface of the first chip 502 away from the interposer 514.

[0104] In some embodiments, a plurality of conductive structures 516 extending along the thickness direction of the interposer 514 are provided in the interposer 514, and the conductive structure 516 has a first end 518 and a second end 520 relatively arranged along the extension direction, and the first end 518 of the conductive structure 516 is coupled to the first chip 502 or the second chip 512, and the second end 520 of the conductive structure 516 is coupled to the substrate 526 through the bump 522.

[0105] refer to 6A to 6F , 6A to 6F This is a cross-sectional view of the packaging structure provided in the third embodiment during the manufacturing process. Figure 1 as well as 6A to 6F , describing a method for manufacturing a packaging structure.

[0106] like Fig. 6A As shown, in step S101 , a first chip 602 is provided, and a surface of the first chip 602 has a sensing region 604 ; in step S102 , the surface of the first chip 602 having the sensing region 604 and a protective layer 608 are bonded to form a protective layer 608 on a side of the first chip 602 having the sensing region 604 .

[0107] In some embodiments, after the first chip 602 and the protective layer 608 are bonded, a bonding layer 628 may be formed between the first chip 602 and the protective layer 608. For example, a bonding medium may be coated on the surface of the first chip and the protective layer, and then bonding is completed under high temperature, vacuum and external force, and the bonding medium forms a bonding layer between the first chip and the protective layer. The protective layer may be, for example, a metal material or a silicon wafer, so that the protective layer may be removed by a debonding process in the future to protect the sensing area of ​​the first chip.

[0108] like Figure 6B As shown, in step 103 , the first chip 602 is disposed on one side of the interposer 614 , and the first chip 602 is located between the interposer 614 and the protection layer 608 .

[0109] In some embodiments, a second chip 612 is further disposed on one side of the interposer 614 , and the first chip 602 and the second chip 612 are disposed on the same side of the interposer 614 .

[0110] In some embodiments, a plurality of conductive structures 616 extending along the Z direction are provided in the interposer 614, and the conductive structure 616 has a first end 618 and a second end 620 relatively arranged along the Z direction, and the first end 618 of the conductive structure 616 is coupled to the first chip 602 or the second chip 612, and the second end 620 of the conductive structure 616 is coupled to the bump 622.

[0111] like Figure 6CAs shown, in step S104, the first chip 602 and the second chip 612 are plastic-encapsulated on one side of the interposer 614 to form a plastic-encapsulation layer 624; wherein the plastic-encapsulation layer 624 covers the side wall of the first chip 602 and the surface of the protective layer 608 away from the interposer 614, and the plastic-encapsulation layer 624 also covers the side wall of the second chip 612 and the surface of the second chip 612 away from the interposer 614.

[0112] Here, the first chip and the second chip are arranged on the same side of the interposer, and the subsequent removal of the protective layer needs to consider the size relationship between the heights of the first chip and the second chip along the Z direction to avoid damage to the second chip during the removal of the protective layer.

[0113] In some embodiments, the height of the first chip along the Z direction is less than or equal to the height of the second chip along the Z direction. In this case, in order to avoid damaging the second chip during the process of removing the protective layer, the first chip and the protective layer can be debonded, and the protective layer can be removed to expose the sensing area; wherein the plastic encapsulation layer can be in close contact with the side wall of the first chip and expose the sensing area of ​​the first chip, and the plastic encapsulation layer also covers the side wall and top surface of the second chip. FIG. 6D to FIG. 6F , detailing the process of removing the protective layer to expose the sensing area.

[0114] like Fig.6D As shown, in some embodiments, step S105 includes: the encapsulation layer 624 can be planarized to remove the encapsulation layer 624 covering the protective layer 608 to expose the protective layer 608; wherein the encapsulation layer 624 can be in close contact with the side walls of the first chip 602 and the protective layer 608, and the encapsulation layer 624 also covers the side walls and top surface of the second chip 612.

[0115] Here, the surface of the protective layer 608 is substantially flush with the surface of the plastic encapsulation layer 624 covering the second chip 612. Substantially flush means that the surface of the protective layer 608 is flush with the surface of the plastic encapsulation layer 624 covering the second chip 612, or that the height difference along the Z direction between the surface of the protective layer 608 and the surface of the plastic encapsulation layer 624 covering the second chip 612 meets the process error range requirement.

[0116] like Fig. 6E As shown, in some embodiments, step S105 includes: performing a debonding process on the first chip 602 and the protection layer 608 ; and removing the protection layer 608 to expose the bonding layer 628 .

[0117] like Fig. 6FAs shown, the bonding layer 628 is removed to expose the sensing area 604. At this time, the distance between the top surface of the molding layer 624 covering the second chip 612 and the interposer 614 is greater than the distance between the surface of the first chip 602 away from the interposer 614 and the interposer 614. In other words, the top surface of the molding layer 624 covering the second chip 612 is higher than the top surface of the first chip 602.

[0118] In some embodiments, the bonding layer can be dissolved and removed by chemical reagents to expose the sensing area. Of course, other methods can also be used for debonding, such as laser stripping. Of course, the first chip and the protective layer can also be bonded in other ways, and no bonding layer may be formed between the first chip and the protective layer, so that the step of removing the bonding layer can be omitted. The present disclosure does not specifically limit the specific methods of bonding and debonding.

[0119] In the disclosed embodiment, the bonding protection layer is used to protect the sensing area of ​​the first chip, and the sensing area can be exposed after the subsequent debonding process to remove the protection layer, so that the first chip can receive the sensing signal through the sensing area. In addition, the plastic sealing layer can plastic seal the side wall of the first chip to better protect the performance and stability of the first chip during use.

[0120] like Fig. 6F As shown, an embodiment of the present disclosure provides a packaging structure, which includes: a substrate 626 and an intermediate layer 614 arranged on one side of the substrate 626; a first chip 602 arranged on a side of the intermediate layer 614 away from the substrate 626, and the surface of the first chip 602 away from the intermediate layer 614 has a sensing area 604; a plastic layer 624 arranged on one side of the intermediate layer 614 and surrounding the first chip 602, and the plastic layer 624 covers the side wall of the first chip 602 and exposes the sensing area 604.

[0121] In some embodiments, the packaging structure 600 also includes: a second chip 612 disposed on a side of the interposer 614 away from the substrate 626, the first chip 602 and the second chip 612 are disposed on the same side of the interposer 614, and the plastic encapsulation layer 624 covers the side walls of the second chip 612 and the surface of the second chip 612 away from the interposer 614; wherein the height of the first chip 602 along the Z direction is less than or equal to the height of the second chip 612 along the Z direction; and the distance between the surface of the plastic encapsulation layer 624 covering the second chip 612 and the interposer 614 is greater than the distance between the surface of the first chip 602 away from the interposer 614 and the interposer 614.

[0122] In some other embodiments, the height of the first chip along the Z direction is greater than the height of the second chip along the Z direction. In this case, since the height of the first chip is greater, it can be directly flattened without damaging the second chip, and the plastic layer covering the protective layer and the protective layer are removed to expose the sensing area, and the plastic layer covering the second chip can also be removed; wherein the plastic layer can be in close contact with the side wall of the first chip and expose the sensing area of ​​the first chip, and the plastic layer also covers the side wall and top surface of the second chip. 7A to 7D , detailing the process of removing the protective layer to expose the sensing area.

[0123] refer to 7A to 7D , FIG. 7A to FIG. 7D This is a cross-sectional view of the packaging structure provided in the fourth embodiment during the manufacturing process. Figure 1 as well as FIG. 7A to FIG. 7D , describing a method for manufacturing a packaging structure.

[0124] like Fig. 7A As shown, in step S101, a first chip 702 is provided, and the surface of the first chip 702 has a sensing area 704; in step S102, the surface of the first chip 702 having the sensing area 704 and the protective layer 708 are bonded to form the protective layer 708 on the side of the first chip 702 having the sensing area 704; in step 103, the first chip 702 is arranged on one side of the interposer 714, and the first chip 702 is located between the interposer 714 and the protective layer 708; a second chip 712 is also arranged on one side of the interposer 714, and the first chip 702 and the second chip 712 are arranged on the same side of the interposer 714.

[0125] In some embodiments, after the first chip 702 and the protection layer 708 are bonded, a bonding layer 728 may be formed between the first chip 702 and the protection layer 708 .

[0126] In some embodiments, a plurality of conductive structures 716 extending along the Z direction are provided in the interposer 714, and the conductive structure 716 has a first end 718 and a second end 720 relatively arranged along the Z direction, and the first end 718 of the conductive structure 716 is coupled to the first chip 702 or the second chip 712, and the second end 720 of the conductive structure 716 is coupled to the bump 722.

[0127] like Figure 7B As shown, in step S104, the first chip 702 and the second chip 712 are plastic-encapsulated on one side of the interposer 714 to form a plastic-encapsulation layer 724; wherein the plastic-encapsulation layer 724 covers the side wall of the first chip 702 and the surface of the protective layer 708 away from the interposer 714, and the plastic-encapsulation layer 724 also covers the side wall of the second chip 712 and the surface of the second chip 712 away from the interposer 714.

[0128] like Figure 7C As described, in some embodiments, step S105 includes: planarizing the molding layer 724 and the protective layer 708 to expose the bonding layer 728; wherein the molding layer 724 can still be in close contact with the side wall of the first chip 702, and the molding layer 724 also covers the side wall and top surface of the second chip 712.

[0129] like Fig.7D As shown, the bonding layer 728 is removed to expose the sensing area 704. At this time, since the thickness of the bonding layer 728 is relatively small, the height difference between the top surface of the plastic encapsulation layer 724 covering the second chip 712 and the surface of the first chip 702 away from the interposer 714 is the thickness of the bonding layer 728. Therefore, the top surface of the plastic encapsulation layer 724 covering the second chip 712 is slightly higher than the top surface of the first chip 702.

[0130] like Fig.7D As shown, an embodiment of the present disclosure provides a packaging structure, which includes: a substrate 726 and an intermediate layer 714 arranged on one side of the substrate 726; a first chip 702 arranged on a side of the intermediate layer 714 away from the substrate 726, and the surface of the first chip 702 away from the intermediate layer 714 has a sensing area 704; a plastic layer 724 arranged on one side of the intermediate layer 714 and surrounding the first chip 702, and the plastic layer 724 covers the side wall of the first chip 702 and exposes the sensing area 704.

[0131] The disclosed embodiment provides a packaging structure and a manufacturing method thereof. In the disclosed embodiment, the surface of the first chip has a sensing area; a protective layer is provided on the side of the first chip having the sensing area; the first chip is provided on one side of the interposer, and after the first chip is plastic-sealed on the side of the interposer, the protective layer is removed to expose the sensing area. In this way, the protective layer can protect the sensing area of ​​the first chip during the process of forming the plastic-sealing layer, and the sensing area can be exposed after the protective layer is removed, so that the first chip can receive the sensing signal through the sensing area; and the plastic-sealing layer can plastic-seale the side wall of the first chip to better protect the performance and stability of the first chip during use.

[0132] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0133] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for manufacturing a packaging structure, characterized in that: The method comprises: Providing a first chip, wherein a surface of the first chip has a sensing area; A protective layer is provided on a side of the first chip having the sensing area, wherein the protective layer at least covers the sensing area; The first chip is arranged on one side of the interposer, and the first chip is located between the interposer and the protective layer; Plastic-sealing the first chip on one side of the interposer to form a plastic-sealing layer; The protective layer is removed to expose the sensing area; wherein the plastic encapsulation layer covers the side wall of the first chip.

2. The manufacturing method according to claim 1, characterized in that: A second chip is also disposed on one side of the interposer, and the first chip and the second chip are disposed on the same side of the interposer; The step of plastic-sealing the first chip on one side of the interposer to form a plastic-sealing layer includes: The first chip and the second chip are plastic-encapsulated on one side of the interposer to form the plastic-encapsulation layer; wherein the plastic-encapsulation layer covers the side wall of the first chip and the surface of the protective layer away from the interposer, and the plastic-encapsulation layer also covers the side wall of the second chip and the surface of the second chip away from the interposer.

3. The manufacturing method according to claim 2, characterized in that: The step of providing a protective layer on the side of the first chip having the sensing area includes: The surface of the first chip having the sensing region and the protective layer are bonded to form the protective layer on the side of the first chip having the sensing region.

4. The manufacturing method according to claim 2, characterized in that: A protruding structure surrounding the sensing area is also provided between the first chip and the protective layer; The step of providing a protective layer on the side of the first chip having the sensing area includes: A protection layer is disposed on a side of the protruding structure away from the first chip, and a cavity is formed between the first chip, the protruding structure and the protection layer, wherein the cavity exposes the sensing area.

5. The manufacturing method according to claim 3, characterized in that: A height of the first chip along a direction perpendicular to the interposer is less than or equal to a height of the second chip along a direction perpendicular to the interposer; The removing of the protective layer to expose the sensing area includes: removing the plastic sealing layer covering the protective layer to expose the protective layer; performing a debonding process on the first chip and the protective layer; The protective layer is removed to expose the sensing area; wherein the distance between the surface of the plastic packaging layer covering the second chip and the intermediate layer is greater than the distance between the surface of the first chip away from the intermediate layer and the intermediate layer.

6. The manufacturing method according to claim 4, characterized in that: A height of the first chip along a direction perpendicular to the interposer is less than or equal to a height of the second chip along a direction perpendicular to the interposer; The removing of the protective layer to expose the sensing area includes: removing the plastic sealing layer covering the protective layer to expose the protective layer; The protective layer is removed to expose the protruding structure and the sensing area; wherein the distance between the surface of the plastic encapsulation layer covering the second chip and the intermediate layer is greater than the distance between the surface of the first chip away from the intermediate layer and the intermediate layer.

7. The manufacturing method according to claim 3 or 4, characterized in that: The height of the first chip along a direction perpendicular to the interposer is greater than the height of the second chip along a direction perpendicular to the interposer; The removing of the protective layer to expose the sensing area includes: The plastic encapsulation layer and the protective layer are planarized to expose the sensing area; wherein the surface of the plastic encapsulation layer covering the second chip is substantially flush with the surface of the first chip away from the interposer.

8. A packaging structure, characterized in that: The packaging structure comprises: A substrate and an interposer disposed on one side of the substrate; A first chip is disposed on a side of the interposer away from the substrate, wherein a surface of the first chip away from the interposer has a sensing area; A plastic packaging layer is disposed on one side of the intermediary layer and surrounds the first chip, wherein the plastic packaging layer covers a side wall of the first chip and exposes the sensing area.

9. The packaging structure according to claim 8, characterized in that: The packaging structure further includes: A protruding structure is disposed on a surface of the first chip away from the intermediary layer and surrounding the sensing area, wherein the plastic encapsulation layer covers an outer side wall of the protruding structure and exposes an inner side wall of the protruding structure.

10. The packaging structure according to claim 8 or 9, characterized in that: The packaging structure further includes: A second chip is arranged on a side of the interposer away from the substrate, the first chip and the second chip are arranged on the same side of the interposer, and the plastic encapsulation layer covers the side wall of the second chip and the surface of the second chip away from the interposer; wherein the height of the first chip along a direction perpendicular to the interposer is less than or equal to the height of the second chip along a direction perpendicular to the interposer; and the distance between the surface of the plastic encapsulation layer covering the second chip and the interposer is greater than the distance between the surface of the first chip away from the interposer and the interposer.

11. The packaging structure according to claim 8, characterized in that: The packaging structure further includes: A second chip is arranged on a side of the interposer away from the substrate, the first chip and the second chip are arranged on the same side of the interposer, and the plastic encapsulation layer covers the side wall of the second chip and the surface of the second chip away from the interposer; wherein the height of the first chip along a direction perpendicular to the interposer is greater than the height of the second chip along a direction perpendicular to the interposer; and the surface of the plastic encapsulation layer covering the second chip is substantially flush with the surface of the first chip away from the interposer.

12. The packaging structure according to claim 8, characterized in that: The interposer is provided with a plurality of conductive structures extending along the thickness direction of the interposer, the conductive structures have a first end and a second end oppositely arranged along the extending direction, the first end of the conductive structure is coupled to the first chip, and the second end of the conductive structure is coupled to the substrate through a bump.

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