FPGA (Field Programmable Gate Array)-based DDR (Double Data Rate) sampling clock dynamic adjustment sampling method and system

Abstract

The invention provides an FPGA-based DDR sampling clock dynamic adjustment sampling method and system, and the method comprises the steps: generating a local clock and a phase offset clock, the local clock is used for generating a DDR read command, and the phase offset clock can perform phase offset relative to the local clock; a DQS clock and DQ data are returned based on a read command sent to the DDR, and the DQS clock and the DQ data are aligned in physical layers; controlling the DQS clock to sample the phase offset clock for multiple times; comparing the sampling data with the last sampling data to obtain a comparison result; and controlling the phase offset clock to perform offset operation according to the comparison result, recalculating the phase relation of the phase offset clock relative to the local clock, and controlling to realize alignment of the edge of the phase offset clock and the central position of the DDR return data. According to the invention, the simple and efficient data sampling function is realized, the occupied resources are few, the realization is easy, and the initialization time of the DDR is reduced.

Description

Technical Field

[0001] The present invention relates to the field of data storage, and in particular to a sampling method and system for dynamically adjusting a DDR sampling clock based on FPGA. Background Art

[0002] FPGA is called Field Programmable Gate Array, which is a hardware programmable device composed of a large number of independent functional modules and wiring resources. DDR is a storage device mainly used to store large amounts of data. DDR has the function of double sampling data, that is, it has the ability to sample data at both the rising and falling edges of the clock, which can increase the efficiency of data transmission exponentially. When designing and producing DDR PHY controllers, DDR will be used in conjunction with FPGA master chips to achieve storage and data transmission functions.

[0003] There is a certain distance between DDR and FPGA, so as the clock frequency controlling DDR increases, the data returned by DDR will have asynchronous differences with the local clock inside the FPGA master chip, and this error will increase with the increase of frequency. In order to solve this problem, the Chinese invention patent application with patent application number 202311313866.2 applied for "a training method and system for a memory system". The invention describes the relevant scheme, namely, generating a gated gate by using a delay training module, and then using multiple internal clocks to sample the data, and achieving data synchronization by adjusting the delay chain at the PHY input. This method can stably and reliably implement DDR read and write operations, and is an effective acquisition method for data storage.

[0004] In the above prior art, data sampling requires the use of gate delay training module resources, and the gate delay chain needs to be adjusted multiple times, which makes the function implementation complex, occupies more resources and makes the DDR initialization time longer. Therefore, the present invention provides a sampling method and system for dynamic adjustment of DDR sampling clock based on FPGA to solve the above problems. Summary of the invention

[0005] The purpose of the present invention is to provide a sampling method and system for dynamically adjusting the DDR sampling clock based on FPGA, which solves the problem that the prior art requires the use of gated gate delay training module resources to perform data sampling, occupies less resources and thus reduces the initial time of DDR.

[0006] On the one hand, in order to achieve the purpose of the present invention, the technical solution adopted by the present invention is:

[0007] The sampling method for dynamically adjusting the DDR sampling clock based on FPGA includes the following steps:

[0008] Generate a local clock and a phase-shiftable clock, wherein the local clock is used to generate a DDR read command, and the phase-shiftable clock can be phase-shifted relative to the local clock;

[0009] Returning a DQS clock and DQ data based on a read command sent to the DDR, wherein the DQS clock and the DQ data are aligned at the physical level;

[0010] Controlling the DQS clock to sample the phase-shiftable clock multiple times;

[0011] Compare the sampling data with the last sampling data to obtain a comparison result;

[0012] The phase-shiftable clock is controlled to perform a shift operation according to the comparison result, so that the edge of the phase-shiftable clock is aligned with the center position of the returned DQ data.

[0013] Furthermore, the sampled data is compared with the last sampled data to obtain a comparison result, which specifically includes:

[0014] If the data levels of two consecutive samples are the same, the comparison result is 1;

[0015] If the levels of two consecutively sampled data are different, the comparison result is 0, and the level states of the two consecutively sampled data are further compared. If the two consecutively sampled data are changed from high level to low level, the comparison result is 00, and if the two consecutively sampled data are changed from low level to high level, the comparison result is 01.

[0016] Further, controlling the phase-shiftable clock to perform a shift operation according to the comparison result to achieve alignment of the edge of the phase-shiftable clock with the center position of the returned DQ data specifically includes:

[0017] One clock cycle of the phase-shiftable clock is recorded as N, and the phase-shiftable clock is shifted to the left or right by 1 / N phases each time when it is shifted relative to the local clock; if the comparison result is 1, then the phase-shiftable clock continues to be shifted;

[0018] Assuming that the phase-shiftable clock is shifted to the right, when the comparison result is 00, that is, the rising edge of the DQS clock is aligned with the rising edge of the phase-shiftable clock, the phase-shiftable clock is controlled to continue to shift N / 4 phases, so that the edge of the phase-shiftable clock is at the center position of the DQS clock and the DQ data;

[0019] When the comparison result is 01, that is, the rising edge of the DQS clock is aligned with the falling edge of the phase-shiftable clock, the phase-shiftable clock is controlled to continue to shift (3 / 4)N phases so that the edge of the phase-shiftable clock is at the center position of the DQS clock and the DQ data.

[0020] Further, controlling the DQS clock to sample the phase-shiftable clock multiple times specifically includes:

[0021] Identify whether the phase-shiftable clock is shifted;

[0022] Each time the phase-shiftable clock is shifted once, the DQS clock is controlled to sample the phase-shiftable clock once.

[0023] Further, identifying whether the phase-shiftable clock has a shift specifically includes:

[0024] When it is first recognized that the phase-shiftable clock is not shifted, it is determined that the recognition is invalid, and the DQS clock is controlled to sample the phase-shiftable clock twice.

[0025] Furthermore, the local clock and the phase-shifted clock are consistent in phase and frequency in an initial state.

[0026] On the other hand, in order to achieve the purpose of the present invention, the technical solution adopted by the present invention is:

[0027] A sampling system for dynamically adjusting a DDR sampling clock based on an FPGA comprises a clock generation module, a DDR module and a training module, wherein the training module comprises a CMD reading module (2), a control sampling submodule (41), a state judgment submodule and an offset control submodule, wherein:

[0028] The clock generation module is used to generate a local clock and a phase-shiftable clock, wherein the local clock is used to generate a DDR read command, and the phase-shiftable clock can be phase-shifted relative to the local clock;

[0029] The DDR module is used to return a DQS clock and DQ data based on a read command sent to the DDR, and the DQS clock and the DQ data are aligned at the physical level;

[0030] The CMD reading module is used to realize the format conversion of clock signal and command;

[0031] The control sampling submodule is used to control the CMD read module to generate a read command, so that the DQS clock samples the phase-shiftable clock multiple times;

[0032] The state judgment submodule is used to compare the sampled data with the last sampled data to obtain a comparison result;

[0033] The offset control submodule is used to control the phase-shiftable clock to perform an offset operation according to the comparison result, so as to align the edge of the phase-shiftable clock with the center position of the returned DQ data.

[0034] Furthermore, the clock generation module, the control sampling submodule, the state judgment submodule and the offset control submodule are all composed of existing resources of FPGA.

[0035] Furthermore, the DDR module includes DDR particles, which are used to return the DQS clock and the DQ data based on the read command. The DDR particles are sealed together with the FPGA so that the DQS clock and the DQ data are edge-aligned when they arrive at the input port of the training module.

[0036] Furthermore, the training module also includes a FIFO submodule, and the DQ data returned by the DDR particle is stored in the FIFO submodule through the phase-shiftable clock, and the FIFO submodule is used to achieve local clock synchronization of the DQ data.

[0037] Beneficial effects of the present invention:

[0038] 1. The present invention uses the DQS clock returned by the DDR to sample the phase-shiftable clock, finds the correct position of the DQS clock sampling through the phase-shiftable clock, aligns the DQS clock and the DQ data at the physical level, finds the correct position of the DQS clock sampling, and uses the phase-shiftable clock to synchronize the data on the DQ data to the local clock, thereby achieving correct and stable sampling of the data, reducing the clock resource occupation and saving clock resources. The entire process only moves the phase-shiftable clock, avoiding the situation of moving the DQS clock and DQ data, simplifying the training process, reducing the delay generation, and improving stability. By simplifying the training process, the initialization time of the DDR is reduced, thereby saving the user's waiting time.

[0039] 2. The present invention does not use a gated gate, and does not need to adjust the gated delay chain multiple times. The function is simple to implement, resources are saved, the logic is simpler, and the initialization time of DDR is reduced, thereby saving the user's waiting time. Compared with the prior art, the prior art uses the delay training module resources of the gated gate for data sampling, samples the data through multiple receiving clocks to obtain sampled data, and requires training of multiple receiving clocks, which consumes high power. The present invention only uses a set of offset clocks and eliminates the use of the gated gate delay training module, which reduces the overall power consumption, and also provides space for the layout design of other functional modules and is more flexible, which can speed up the design progress. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is an overall flow chart of the sampling method for dynamically adjusting the DDR sampling clock based on FPGA of the present invention;

[0041] Figure 2 A sampling flow chart of a sampling method for dynamically adjusting a DDR sampling clock based on FPGA of the present invention;

[0042] Figure 3 A timing diagram of a process of sampling a phase-shiftable clock using a DQS clock in a sampling method for dynamically adjusting a DDR sampling clock based on FPGA of the present invention;

[0043] Figure 4 Another process timing diagram of the DQS clock sampling of the phase-shiftable clock of the sampling method of the FPGA-based DDR sampling clock dynamic adjustment of the present invention;

[0044] Figure 5 The figure is an overall module flow chart of the sampling system for dynamic adjustment of DDR sampling clock based on FPGA of the present invention.

[0045] The reference numerals are as follows:

[0046] 1. Clock generation module; 2. CMD reading module; 3. DDR module; 4. Training module; 41. Control sampling submodule; 42. State judgment submodule; 43. Offset control submodule; 44. FIFO submodule. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0048] The embodiment of the present invention provides a sampling method for dynamically adjusting a DDR sampling clock based on an FPGA. The sampling method includes: generating a local clock and a phase-shiftable clock, wherein the local clock is used to generate a read command of the DDR, and the phase-shiftable clock can be phase-shifted relative to the local clock; returning a DQS clock and DQ data based on the read command sent to the DDR, and aligning the DQS clock and the DQ data at the physical level; controlling the DQS clock to sample the phase-shiftable clock multiple times; comparing the sampled data with the last sampled data to obtain a comparison result; and controlling the phase-shiftable clock to perform an offset operation according to the comparison result, so as to align the edge of the phase-shiftable clock with the center position of the returned DQ data. The sampling method provided in the embodiment of the present application samples the phase-shiftable clock by using the DQS clock returned by the DDR, and adjusts the phase of the phase-shiftable clock until the rising edge of the phase-shiftable clock is aligned with the center of the upper edge to lower edge area of ​​the DQS clock, and the DQS clock and DQ data are aligned at the physical level. The correct position of the DQS clock sampling is found, that is, the correct position of the DQ data is found, and the DQ data is synchronized to the local clock using the phase-shiftable clock, thereby achieving correct and stable sampling of the data, reducing the clock resource occupation, and saving clock resources. The entire process only moves the phase-shiftable clock, avoiding the situation of moving the DQS clock and DQ data, simplifying the training process, reducing the delay, and improving stability. By simplifying the training process, the initialization time of the DDR is reduced, thereby saving the user's waiting time.

[0049] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0050] like Figure 1 and Figure 2 As shown, the sampling method for dynamically adjusting the DDR sampling clock based on FPGA provided in the embodiment of the present application may include the following steps:

[0051] Step S1: Generate a local clock and a phase-shiftable clock. The local clock is used to generate a DDR read command, and the phase-shiftable clock can be shifted relative to the local clock.

[0052] Specifically, two clocks with the same frequency are generated, one is the local clock, and the other is the phase-shiftable clock. The local clock and the phase-shiftable clock have the same phase and frequency in the initial state. The local clock can be used to generate a read command that can be recognized by DDR. The phase-shiftable clock can be dynamically shifted relative to the local clock, and will return to the original position after a clock cycle.

[0053] Step S2: Return the DQS clock and DQ data based on the read command sent to the DDR, and align the DQS clock and DQ data at the physical level.

[0054] When DDR receives a read command, it returns the DQS clock and DQ data, and the DQ data is usually discontinuous. Since the DQS clock and DQ data are aligned at the physical level, the positions of the DQS clock and DQ data correspond to each other, and the DQS clock and DQ data remain edge-aligned when they arrive at the receiving port, thereby reducing the relative delay between the DQS clock and DQ data. By finding the position of the DQS clock, the corresponding position of the DQ data can be found. Since the upper and lower edges of a DQS clock correspond to two DQ data respectively, it is simpler and more convenient to determine the position of the DQ data by finding the position of the DQS clock.

[0055] Step S3: Control the DQS clock to sample the phase-shiftable clock multiple times.

[0056] When DDR returns the DQS clock, it identifies whether the phase-shiftable clock is offset. If it is identified for the first time that the phase-shiftable clock is not offset, it is determined that the identification is invalid, and the DQS clock is controlled to sample the phase-shiftable clock twice. If it is subsequently identified that the phase-shiftable clock is offset, the DQS clock is controlled to directly sample the phase-shiftable clock. Each time the phase-shiftable clock is offset, the DQS clock is controlled to sample the phase-shiftable clock once. The DQS clock directly samples the phase-shiftable clock multiple times to obtain sampled data.

[0057] Step S4: Compare the sampled data with the last sampled data to obtain a comparison result.

[0058] Since the time of returning the DQS clock is tCL according to the DDR protocol, sampling starts after the tCL clock cycle and the sampled data is obtained. Since the DQS clock returned by DDR is asynchronous with the local clock, the sampling phase of the returned DQS clock may be offset. The clock may be high or low. Each sampling will be accompanied by a level signal when the sampled data is obtained. The sampled data is compared with the last sampled data. If the levels of the two consecutive sampled data are the same, the comparison result is 1; if the levels of the two consecutive sampled data are different, the comparison result is 0, and the level states of the two consecutive sampled data are further compared. If the two consecutive sampled data are changed from high level to low level, the comparison result is 00; if the two consecutive sampled data are changed from low level to high level, the comparison result is 01.

[0059] Step S5: Control the phase-shiftable clock to perform a shift operation according to the comparison result, so as to align the edge of the phase-shiftable clock with the center position of the returned DQ data.

[0060] One clock cycle of the phase-shiftable clock is recorded as N, that is, the phase-shiftable clock moves N times and returns to the original phase position. When the phase-shiftable clock is offset relative to the local clock, it is offset to the left or right by 1 / N phase each time. If the comparison result is 1, that is, the two data levels of continuous sampling are the same, then the phase-shiftable clock continues to be offset.

[0061] Assume that the phase can be shifted to the right by the clock, such as Figure 3 As shown in FIG. 1 , when the comparison result is 00, that is, the rising edge of the DQS clock is aligned with the rising edge of the phase-shiftable clock, the phase-shiftable clock is controlled to continue to shift by N / 4 phases, so that the edge of the phase-shiftable clock is at the center of the DQS clock and the DQ data. Figure 4 As shown in the figure, when the comparison result is 01, that is, the rising edge of the DQS clock is aligned with the falling edge of the phase-shiftable clock, the phase-shiftable clock is controlled to continue to shift (3 / 4)N phases, so that the edge of the phase-shiftable clock is at the center of the DQS clock and the DQ data. When the edge of the phase-shiftable clock is at the center of the DQS clock and the DQ data, the phase-shiftable clock sampling to the DQ data is more stable.

[0062] like Figure 5As shown, the embodiment of the present invention also provides a sampling system for dynamically adjusting the DDR sampling clock based on FPGA. When the sampling system is running, it can drive the relevant hardware to execute the above sampling method to achieve stable and correct sampling data. The sampling system includes: a clock generation module 1, a CMD reading module 2, a DDR module 3 and a training module 4. The training module 4 includes a control sampling submodule 41, a state judgment submodule 42 and an offset control submodule 43. The clock generation module 1, the CMD reading module 2, the control sampling submodule 41, the state judgment submodule 42 and the offset control submodule 43 are all composed of existing resources of the FPGA.

[0063] in:

[0064] The clock generation module 1 is used to generate a local clock and a phase-shiftable clock. The local clock is given to the training module 4. The training module 4 generates a read enable signal and sends it to the CMD read module. After receiving the read enable signal, the CMD read module generates a read command and sends it to the DDR. The phase-shiftable clock can be phase-shifted relative to the local clock. In some embodiments, the clock generation module 1 can be specifically a PLL phase-locked loop or a DLL phase-locked loop. It can be understood that the clock generation module 1 has the function of adjusting the phase of the phase-shiftable clock, and the output phase-shiftable clock can be dynamically moved relative to the local clock. Assuming that the phase-shiftable clock moves N times and returns to the original phase position, that is, N represents a clock cycle, when the phase-shiftable clock needs to be moved, the offset control submodule 43 of the training module 4 will send a pll_step pulse to the clock generation module 1. After the clock generation module 1 recognizes the pll_step pulse, it adjusts the internal delay so that the phase-shiftable clock is shifted by 1 / N phase each time relative to the local clock. If the pll_step pulse arrives again, the phase of the phase-shiftable clock is shifted by 1 / N position cumulatively. In the initial state, the phase and frequency of the phase-shifted clock are consistent with those of the local clock.

[0065] The clock signal generated by the clock generation module 1 and the read enable signal sent by the training module 4 are transmitted to the CMD read module 2. The CMD read module 2 implements the format conversion of the clock signal and the read enable command and then transmits the format-converted clock signal and the read command to the DDR module 3. The DDR module 3 includes DDR particles. After receiving the read command, the DDR will return the DQS clock and DQ data. The DDR particles are sealed together with the FPGA so that the DQS clock and the DQ data are aligned at the physical level, so that the DQS clock and the DQ data are edge-aligned when they arrive at the input port of the training module 4. The control sampling submodule 41 controls the DQS clock to sample the phase-shiftable clock multiple times, the state judgment submodule 42 compares the sampled data with the last sampled data to obtain the comparison result, and the offset control submodule 43 controls the phase-shiftable clock to perform an offset operation according to the comparison result, so as to align the edge of the phase-shiftable clock with the center position of the returned DQ data.

[0066] Specifically, when DDR returns the DQS clock and DQ data, the control sampling submodule 41 identifies whether the phase-shiftable clock is offset. The control sampling submodule 41 first identifies that the phase-shiftable clock is not offset, determines that the identification is invalid, and controls the DQS clock to sample the phase-shiftable clock twice. Subsequently, it is identified that the phase-shiftable clock is offset, and the DQS clock is controlled to directly sample the phase-shiftable clock. Each time the phase-shiftable clock is offset, the DQS clock is controlled to sample the phase-shiftable clock once. The DQS clock directly samples the phase-shiftable clock multiple times to obtain sampled data. After the correct sampling position of the DQS clock is found, the phase-shiftable clock is no longer offset, and the control sampling submodule 41 stops identifying.

[0067] The sampled data is accompanied by a level signal, and the state judgment submodule 42 compares the level signal accompanied by the sampled data with the level signal accompanied by the last sampled data to obtain a comparison result. If the levels of the two consecutively sampled data are the same, the comparison result is 1; if the levels of the two consecutively sampled data are different, the comparison result is 0, and the level states of the two consecutively sampled data are further compared. If the two consecutively sampled data are changed from a high level to a low level, the comparison result is 00, and if the two consecutively sampled data are changed from a low level to a high level, the comparison result is 01.

[0068] If the comparison result is 1, that is, the two data levels of the continuous sampling are the same, then the offset control submodule 43 will send a pll_step pulse to the clock generation module 1. After the clock generation module 1 recognizes the pll_step pulse, it will continue to offset the phase-shiftable clock through internal delay adjustment. Assuming that the phase-shiftable clock is shifted to the right, each time the phase-shiftable clock is shifted, the DQS clock samples the phase-shiftable clock once to obtain a new comparison result. Figure 3As shown in Figure 1, when the comparison result is 00, the rising edge of the DQS clock is aligned with the rising edge of the phase-shiftable clock. Figure 3 The phase shift clock 5 and the DQS clock shown in the figure can be shifted. At this time, the phase shift clock can be controlled to continue to shift N / 4 phases. Figure 3 The phase-shiftable clock 6 and the DQS clock shown in the figure make the edge of the phase-shiftable clock be at the center position of the DQS clock and the DQ data, thus achieving the determination of the correct sampling position. Figure 4 As shown in the figure, when the comparison result is 01, the rising edge of the DQS clock is aligned with the falling edge of the phase-shiftable clock. Figure 4 The phase shift clock 5 and the DQS clock shown in the figure can be shifted. At this time, the phase shift clock can be controlled to continue to shift (3 / 4)N phases. Figure 3 The phase-shiftable clock 6 and the DQS clock shown are arranged so that the edge of the phase-shiftable clock is at the center of the DQS clock and the DQ data, thereby achieving the determination of the correct sampling position. The phase-shiftable clock samples the center of the DQ data, and the sampled DQ data is more stable.

[0069] The training module 4 also includes a FIFO submodule 44, which is used to realize the local clock synchronization of the DQ data. After the system initialization is completed, the FIFO can be used to read and write user data normally. The present invention only uses the DQS clock in the training process, eliminating the process of writing data. After initialization, the DQ data returned by the DDR particles is stored in the FIFO submodule 44 through the phase-shifted clock, wherein the sampled DQS clock is used as the write enable signal of the FIFO in the FIFO submodule 44, and the output direction of the FIFO submodule 44 has an empty empty flag signal, which is used as the read enable signal of the FIFO. The FIFO reads the DQ data and synchronizes the read DQ data with the local clock, which can be used for subsequent read and write processes. The offset result of the offset clock obtained by the training module 4 can be saved for the clock phase adjustment of other identical products, and other identical products do not need to go through the same training process, saving the user's waiting time.

[0070] Beneficial effects of the present invention:

[0071] The present invention uses the DQS clock returned by the DDR to sample the phase-shiftable clock, finds the correct position of the DQS clock sampling through the phase-shiftable clock, aligns the DQS clock and the DQ data at the physical level, finds the correct position of the DQS clock sampling, and synchronizes the data on the DQ data to the local clock using the phase-shiftable clock, thereby achieving correct and stable sampling of the data, reducing the clock resource occupation and saving clock resources. The entire process only moves the phase-shiftable clock, avoiding the situation of moving the DQS clock and DQ data, simplifying the training process, reducing the delay generation, and improving stability. By simplifying the training process, the initialization time of the DDR is reduced, thereby saving the user's waiting time.

[0072] The present invention does not use a gated gate, and does not need to adjust the gated delay chain multiple times. The function is simple to implement, resources are saved, the logic is simpler, and the initialization time of DDR is reduced, thereby saving the user's waiting time. Compared with the prior art, the prior art uses the delay training module resources of the gated gate for data sampling, samples the data through multiple receiving clocks to obtain sampled data, and requires training of multiple receiving clocks, which consumes high power. The present invention only uses a set of offset clocks and omits the use of the delay training module of the gated gate, which reduces the overall power consumption, and also provides space for the layout design of other functional modules and is more flexible, which can speed up the design progress.

[0073] DDR particles often exist as independent chips. Since DDR particles themselves have a large number of pins, it is not convenient for board design. The present invention adopts a new design to directly encapsulate DDR particles in the FPGA main control chip. Since the distance between DDR and the main control chip is reduced, the read-write efficiency and stability can be significantly improved. Since FPGA often has a lot of pins, the DDR particles are used as a storage unit and directly sealed with the FPGA as a device. This is conducive to the user end to quickly store data according to the reference design without worrying about the specific operations of the bottom layer, which indirectly improves the storage progress. And the two devices are sealed together to ensure that the delay between the two is stable. When using DDR in batches, after the sampled data is stable, the user does not have to worry about the sampling offset, which reduces the debugging time, thereby reducing the user's waiting time.

[0074] The systems, modules or units described in the above embodiments can be implemented by computer chips or physical configuration programs, or by products with certain functions. For the convenience of description, the above systems are described separately by functions in various units. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0075] The present invention is described with reference to the flowcharts and / or block diagrams of the system and configuration program according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0076] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0077] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0078] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0079] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0080] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0081] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. Sampling method based on FPGA for dynamic adjustment of DDR sampling clock. Features: The following steps are involved: Generate a local clock and a phase-shiftable clock, wherein the local clock is used to generate a DDR read command, and the phase-shiftable clock can be phase-shifted relative to the local clock; Returning a DQS clock and DQ data based on a read command sent to the DDR, wherein the DQS clock and the DQ data are aligned at the physical level; Controlling the DQS clock to sample the phase-shiftable clock multiple times; Compare the sampling data with the last sampling data to obtain a comparison result; The phase-shiftable clock is controlled to perform a shift operation according to the comparison result, so that the edge of the phase-shiftable clock is aligned with the center position of the returned DQ data.

2. The sampling method for dynamically adjusting the DDR sampling clock based on FPGA as claimed in claim 1, Features: Compare the sampled data with the previous sampled data to obtain the comparison results, including: If the data levels of two consecutive samples are the same, the comparison result is 1; If the levels of two consecutively sampled data are different, the comparison result is 0, and the level states of the two consecutively sampled data are further compared. If the two consecutively sampled data are changed from high level to low level, the comparison result is 00, and if the two consecutively sampled data are changed from low level to high level, the comparison result is 01.

3. The sampling method for dynamically adjusting the DDR sampling clock based on FPGA as claimed in claim 2, Features: Controlling the phase-shiftable clock to perform a shift operation according to the comparison result to achieve alignment of the edge of the phase-shiftable clock with the center position of the returned DQ data, specifically including: One clock cycle of the phase-shiftable clock is recorded as N, and the phase-shiftable clock is shifted to the left or right by 1 / N phases each time when it is shifted relative to the local clock; if the comparison result is 1, then the phase-shiftable clock continues to be shifted; Assuming that the phase-shiftable clock is shifted to the right, when the comparison result is 00, that is, the rising edge of the DQS clock is aligned with the rising edge of the phase-shiftable clock, the phase-shiftable clock is controlled to continue to shift N / 4 phases, so that the edge of the phase-shiftable clock is at the center position of the DQS clock and the DQ data; When the comparison result is 01, that is, the rising edge of the DQS clock is aligned with the falling edge of the phase-shiftable clock, the phase-shiftable clock is controlled to continue to shift (3 / 4)N phases so that the edge of the phase-shiftable clock is at the center position of the DQS clock and the DQ data.

4. The sampling method for dynamically adjusting the DDR sampling clock based on FPGA as claimed in claim 2, Features: Controlling the DQS clock to perform multiple sampling on the phase-shiftable clock specifically includes: Identify whether the phase-shiftable clock is shifted; Each time the phase-shiftable clock is shifted once, the DQS clock is controlled to sample the phase-shiftable clock once.

5. The sampling method for dynamically adjusting the DDR sampling clock based on FPGA as claimed in claim 4, Features: Identifying whether the phase-shiftable clock has a shift specifically includes: When it is first recognized that the phase-shiftable clock is not shifted, it is determined that the recognition is invalid, and the DQS clock is controlled to sample the phase-shiftable clock twice.

6. The sampling method for dynamically adjusting the DDR sampling clock based on FPGA as claimed in claim 1, Features: The local clock and the phase-shifted clock are consistent in phase and frequency in an initial state.

7. Sampling system with dynamic adjustment of DDR sampling clock based on FPGA, Features: The invention comprises a clock generation module (1), a DDR module (3) and a training module (4), wherein the training module (4) comprises a CMD reading module (2), a control sampling submodule (41), a state judgment submodule (42) and an offset control submodule (43), wherein: The clock generation module (1) is used to generate a local clock and a phase-shiftable clock, wherein the local clock is used to generate a DDR read command, and the phase-shiftable clock can be phase-shifted relative to the local clock; The DDR module (3) is used to return a DQS clock and DQ data based on a read command sent to the DDR, and the DQS clock and the DQ data are aligned at the physical level; The CMD reading module (2) is used to realize the format conversion of the clock signal and the command; The control sampling submodule (41) is used to control the CMD reading module (2) to generate a read command, so as to enable the DQS clock to perform multiple sampling on the phase-shiftable clock; The state judgment submodule (42) is used to compare the sampled data with the last sampled data to obtain a comparison result; The offset control submodule (43) is used to control the phase-shiftable clock to perform an offset operation according to the comparison result, so as to align the edge of the phase-shiftable clock with the center position of the returned DQ data.

8. The sampling system for dynamically adjusting the DDR sampling clock based on FPGA as claimed in claim 7, Features: The clock generation module (1), the control sampling submodule (41), the state judgment submodule (42) and the offset control submodule (43) are all composed of existing resources of the FPGA.

9. The sampling system for dynamically adjusting the DDR sampling clock based on FPGA as claimed in claim 7, Features: The DDR module (3) comprises a DDR particle, wherein the DDR particle is used to return the DQS clock and the DQ data based on the read command, and the DDR particle is sealed together with the FPGA so that the DQS clock and the DQ data are edge-aligned when they arrive at the input port of the training module (4).

10. The sampling system for dynamically adjusting the DDR sampling clock based on FPGA as claimed in claim 9, Features: The training module (4) further comprises a FIFO submodule (44), and the DQ data returned by the DDR particles is stored in the FIFO submodule (44) via the phase-shiftable clock, and the FIFO submodule (44) is used to achieve local clock synchronization of the DQ data.

Images