Memory device bandwidth optimization

Abstract

The invention relates to memory device bandwidth optimization. Techniques are disclosed for scheduling memory operations in which alternating read / write commands within a multi-bank memory operation are delayed beyond a minimum hour-order parameter to improve memory data bus utilization. The remaining read / write commands are delayed by no more than a minimum hour-order parameter. Every other clock cycle (e.g., even-numbered clock cycle) within a memory operation is reserved for an activation command, while other commands such as synchronization and read / write are scheduled at spaced clock cycles (e.g., odd-numbered clock cycles). For a memory device in which a synchronization command, which starts a clock of a memory data bus, is to be caused to be in a plurality of clock cycles in a cycle reserved for an active command prior to a corresponding read / write command, a particular mode of operation is disclosed in which the memory device internally delays the received synchronization command.

Description

[0001] This application is a divisional application of the PCT international application with an international filing date of August 18, 2022, Chinese application number 202280058595.9, and invention name “Memory Device Bandwidth Optimization” entering the Chinese national phase. Technical Field

[0002] The present disclosure relates generally to memory controllers, and more particularly, to scheduling memory commands in a manner that improves utilization of a data bus of a memory device. Background Art

[0003] One common type of computer memory that has been used for decades is dynamic random access memory (DRAM), which is a form of random access memory (RAM) that requires periodic refreshing to maintain the data stored therein. Older DRAM implementations are asynchronous, meaning that the system clock is not used to coordinate memory accesses, while many newer implementations are synchronous (SDRAM), meaning that a clock is used to coordinate memory accesses.

[0004] Memory, including SDRAM memory, is typically organized into sub-segments called banks. Banks are configured to operate independently of one another so that the device can operate on memory access commands in each bank simultaneously. This allows memory devices to achieve greater concurrency and higher data rates. One type of SDRAM is low power double data rate (LPDDR SDRAM), which consumes less power than other implementations and is therefore well suited for applications such as mobile computing.

[0005] International semiconductor memory standards have facilitated the high-volume market for a variety of electronic products by ensuring compatibility between products provided by different suppliers. JEDEC (Joint Electron Device Engineering Council) publishes standards for many different microelectronic technologies. In February 2019, JEDEC published the standard JESD209-5 for Low Power Double Data Rate 5 (LPDDR5 or LP5). The standard supports a data transfer rate of 6400Mbps and up to 16 banks per memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure sets forth techniques for scheduling operations for a memory device with reference to the following figures.

[0007] Figure 1 is a block diagram illustrating one embodiment of a scheduling paradigm for multi-bank memory operations.

[0008] Figure 2 is a block diagram illustrating an embodiment of a memory controller that can be used to implement the disclosed techniques.

[0009] FIG. 3A to FIG. 3F Contention and bus efficiency are shown for different possible schedules for a set of memory operations.

[0010] FIG. 4A to FIG. 4J Different portions of a timing diagram for a memory read operation using a "2-6" cadence are shown.

[0011] FIG. 5A to FIG. 5J Different portions of a timing diagram for a memory write operation using a "2-6" pace are shown.

[0012] FIG. 6A to FIG. 6J Different portions of a timing diagram for a memory write operation using "6-2" pacing are shown.

[0013] Figure 7 is a flow chart of one embodiment of a method for implementing the disclosed scheduling techniques.

[0014] Figure 8 is a block diagram illustrating an exemplary computing device for implementing the disclosed technology.

[0015] Fig. 9 is a diagram illustrating an exemplary application of systems and devices employing the disclosed technology.

[0016] Fig.10 is a block diagram illustrating an exemplary computer-readable medium storing circuit design information for implementing a device employing the disclosed techniques. DETAILED DESCRIPTION

[0017] The LP5 high-frequency interface presents several challenges when trying to extract high bandwidth utilization of the data bus. The standard specifies that two activation commands are required for a particular memory bank, each of which is issued on a different clock signal. In addition, under the standard, a synchronization command is required to start the data clock for the memory. In one mode, the command is issued one clock cycle before the read command or write command. (Alternatively, an "always online" mode can be used, but this mode can consume a lot of power, which is generally undesirable). The data used to read or write a particular memory bank is transmitted in two beats, two clocks per beat. However, these beats cannot be immediate because the LP5 memory cannot generate (or store) data so quickly at a high frequency. Therefore, there are two dead clock cycles between the two beats of the data. Therefore, the constraints imposed by the LP5 standard make it difficult to achieve maximum utilization of the data bus (thereby improving the performance of the memory system) while still scheduling in a manner that makes the specific implementation of the scheduler relatively efficient.

[0018] The present disclosure outlines a scheduling paradigm that seeks to maximize memory data bus utilization while considering the various constraints of the LP5 standard. The present disclosure proposes dividing the clock cycles on the interface between the memory controller and the memory into two groups of alternating clock cycles (e.g., even clock cycles and odd clock cycles). One group of clock cycles in these groups of clock cycles (e.g., even clock cycles) is used to transmit activation commands for various memory banks addressed in multi-bank memory operations (LP5 supports up to 16 memory banks for some operations). The other group (e.g., odd clock cycles) is used to transmit everything else. Therefore, each memory bank to be addressed has two activation commands scheduled in consecutive even clock cycles. Other commands are scheduled in odd clock cycles between activation commands.

[0019] Next, the present disclosure notes that the standard specifies the minimum timing delay from the end of the second activation of a given storage body until a read (or write) to the storage body can occur. For the LP5 standard, the delay corresponds to the parameter RAS to CAS delay (tRCDr for reading, tRCDw for writing). Under one version of the proposed scheduling paradigm, the first read / write in a set of transactions is delayed by more than its specified tRCD value by two clock cycles. Then the second read / write command is scheduled in the next consecutive odd clock cycle. This aligns the data beats of the two commands so that they are properly interleaved. The third command is delayed by six clock cycles (three even and three odd clock cycles) from its normal timing, so that the first beat appears immediately after the second beat of the second command. The fourth command is two clocks after the third command. This "2-6" pattern is repeated throughout the memory transaction, and the result is that the data bus can be fully utilized, as will be shown in various timing diagrams below. The "6-2" timing pattern can also achieve similar results. The scheduler can effectively implement any of these paradigms.

[0020] More generally, it can be said that under this paradigm, alternating commands for read / write commands of multi-bank memory operations are scheduled to be delayed beyond a minimum timing delay by a multi-cycle window. Figure 1 In the embodiment shown, the length of this multi-cycle window is two clock cycles, but it may be longer for other embodiments if the characteristics of the particular memory device being addressed warrant it.

[0021] Figure 1 An example of such a scheduling paradigm is shown. As shown, the apparatus 100 includes a memory controller 110 coupled to a memory device 150 via an interface 140 including a command clock signal 142, a command bus 144, and a data bus 146. Figure 8Various possible additional components within device 100 are discussed. Fig. 9 It is shown that apparatus 100 may be any of a variety of types of electronic products.Memory device 150 may be any of a variety of DRAM devices, including those compliant with JEDEC JESD209-5, Low Power Double Data Rate 5 (LPDDR5).

[0022] The memory controller 110 includes a memory interface circuit 130 configured to couple to a memory device 150 via an interface 140. The memory device 150 includes a plurality of memory banks 152. The memory controller 110 also includes a control circuit 120 coupled to the memory interface circuit 130 and configured to initiate a multi-bank memory operation, such as a burst operation. The multi-bank memory operation is initiated by scheduling a sequence of bank-specific commands to be sent to the memory device 150 via a command bus 144.

[0023] An example of the timing for scheduling bank-specific commands to four banks (bank A to bank D) is shown in table 180. Generally speaking, bank-specific commands for a given memory bank include: a) a first activation command; b) a second activation command after two cycles of the command clock signal 142; and c) a read / write command with at least the minimum timing parameters specified for the memory device after the second activation command. As its name implies, the read / write command specifies the type of operation to be performed (i.e., whether it is a read operation or a write operation). Figure 1 Depicting a read operation. In this example, the minimum timing parameter is referred to as the RAS to CAS delay for a read operation, or tRCDr. In the example shown, tRCDr = 15 clock cycles. The amount of delay RL that specifies the delay between a read command and the data appearing on the bus is 17 clock cycles.

[0024] As can be seen from Table 180, every other read command during a multi-bank memory operation is scheduled to be delayed by more than the minimum timing parameter tRCDr. Here, the read commands for banks A and C are delayed by 2 clock cycles. The remaining read commands for banks B and D are delayed by no more than tRCDr. Note that there are similar timing parameters for writes (tRCDw).

[0025] The result of delaying alternating read / write commands during a multi-bank memory operation that begins with a first read / write command is that the commands are scheduled at a repeating 2-cycle / 6-cycle ("2 / 6") pace. In one iteration of the pace, read / write commands for a first given bank (e.g., bank A) and a second consecutive given bank (e.g., bank B) are scheduled two cycles apart. A single iteration of the pace also includes read / write commands for a second given bank (bank B) and a third consecutive given bank (bank C) being scheduled six cycles apart. In another embodiment, alternating read / write commands that begin with a second read / write command result in a repeating 6-cycle / 2-cycle ("6 / 2") pace. In this embodiment, accesses to banks A and B are scheduled 6 cycles apart, while accesses to banks B and C are scheduled 2 cycles apart.

[0026] It can also be seen from Table 180 that the control circuit 120 is configured to schedule an activation command in every other clock cycle of the command bus 144 to perform a multi-bank memory operation. In the illustrated example, the activation command is scheduled in an even clock cycle, and other commands are scheduled in an odd clock cycle. The combination of scheduling the activation command in every other clock cycle and scheduling the read / write command in the interval clock cycle makes the utilization rate of the bandwidth of the data bus 146 higher. In fact, for certain memory operations that address each of the multiple banks in the memory device 150 in a pass that starts with an initial bank and ends with a final bank, the control circuit 120 can schedule commands so that during a specific pass through the multiple banks, the data bus is fully utilized during the time period when the data for the initial bank and the data for the final bank are present on the data bus. In fact, Table 180 shows that once the data for the read operation begins to appear on the bus in cycle 36, the data bus 146 is fully utilized.

[0027] Now go to Figure 2 , depicted from Figure 1 1 is a block diagram of one embodiment of a memory controller 110 of the system. The memory controller 110 receives memory requests from various components in the system (e.g., processors such as central processing units (CPUs) within a processor cluster, graphics processing units (GPUs), peripheral devices, etc.) through a communication structure. In one embodiment, the communication structure may include multiple independent interconnects. For example, one interconnect may transmit memory requests from a CPU processor; another interconnect may transmit memory requests from a GPU; and another interconnect may transmit memory requests from a peripheral device. In another embodiment, the communication structure may include a single interconnect, and memory requests may be merged from various source components to the memory controller 110 through the interconnect.

[0028] The memory controller 110 may include one or more request queues 210 to temporarily store memory requests until they can be serviced. In one embodiment, the memory controller 110 may retain requests in the request queues 210 until they are completed (data is returned to the source component for reading, or completed for certain write requests). In another embodiment, some write requests (so-called posted writes) do not receive completions, but may still be tracked in the request queues until the write data has been written to memory (or to a memory cache as discussed below).

[0029] The arbiter circuit 220 can select among the memory requests in the queues 210A-210C to service. The arbiter circuit 220 can consider a variety of factors when selecting a memory request. For example, in one embodiment, the request can be assigned to a traffic class in a quality of service (QoS) mechanism, and the traffic class can be a factor in the selection. Over time, higher priority traffic classes can be selected more frequently than lower priority traffic classes. Balancing the priorities of the traffic classes can be fairness and forwarding progress factors to ensure that no traffic class or priority is blocked indefinitely. The life of the request (e.g., how long the request has been in the request queue) can also be a factor.

[0030] The request that wins the arbitration can access the memory cache 230, which stores data previously accessed from the memory. A memory request that hits the memory cache 230 can read or write the data in the cache and can be completed accordingly. The memory cache can reduce the waiting time of the memory request and can also save power that would have been spent on transmitting the memory request to the memory device. Other embodiments may not include a memory cache as desired.

[0031] Memory requests that miss in the memory cache 230 may be forwarded to a memory device controlled by the memory controller 110. The memory controller 110 may control one or more memory devices 150 within the memory, and may include a memory channel unit (MCU) 240 to interface to each memory device. The memory address space mapped to the memory controller 110 may be allocated to the memory devices controlled by the memory controller, and thus a given memory request may be provided to a given MCU 250 by the memory cache 230 based on the address of the memory request and which memory device is mapped to the memory device. For example, certain bits of the memory address may be decoded to identify a "plane", where each memory address having the same value for certain bits may be transmitted to the same MCU / memory device. In one embodiment, the memory cache 230 may also be divided into planes. Therefore, multiple memory requests to different planes may access the memory cache in parallel.

[0032] MCU 240 includes a request queue 242 for storing requests waiting to be transmitted to memory device 150, and a scheduler circuit 244 configured to schedule the requests for transmission. (Scheduler circuit 244 can be said to correspond to Figure 1 ) It is worth noting that a given memory request may include multiple transfers over the interface to the memory device to execute the request, such as in the case of a burst operation.

[0033] If the page including the data being accessed is not already open, an activate command is transmitted. Once the page is opened, a read or write command is sent, and then the data is transmitted (for writing) or received (for reading). As previously described, the scheduler circuit 244 can schedule the activate and read / write commands as well as certain other commands (e.g., a synchronization command for turning on a read / write clock in a memory device, which may optionally be turned off when the memory device is not being addressed; a refresh command for ensuring that data remains correctly stored in the memory device; etc.).

[0034] The scheduler circuit 244 is configured to schedule commands in a manner that complies with the specifications of the memory system, since different memories have different protocols and timing requirements. Within this framework, the scheduler circuit 244 is configured to attempt to schedule commands in a manner that efficiently utilizes the bandwidth of the memory device. For example, reads may be grouped together and writes may be grouped separately, since one or more clock cycles of bus turnaround are required on the data bus when switching between reads and writes. Within the group, memory requests may be subgrouped based on accessing different memory banks (and therefore different pages may be open in different memory banks) or accessing the same page in the same memory bank, so activation of the page may be shared between requests. In addition, scheduling of commands by the scheduler circuit 244 may be performed to increase data bandwidth, such as with respect to Figure 1 briefly described and as more fully described below.

[0035] The memory device 150 in the memory can be any suitable type of memory, including any DRAM memory. More specifically, the DRAM can be a double data rate (DDR) DRAM implemented according to industry standard specifications (such as DDR1, DDR2, DDR3, etc.) and / or one of the low power specifications of DDR DRAM (such as LP3, LP4, etc. in addition to the LP5 specification). In some embodiments, the memory device 150 can be a single in-line memory module (SIMM) or a dual in-line memory module (DIMM) including multiple memory chips mounted on an underlying substrate. In various embodiments, the memory device 150 may also include multiple memory banks.

[0036] Although the technology of the present disclosure was developed in response to the context of the LP5 memory standard, it is not intended to be limited to memories that comply with the standard. Instead, the technology of the present disclosure can be applied to other memory systems that encounter similar problems in improving the utilization of the data bus, including but not limited to future LP5 memory standards and other low-power double data rate RAM standards.

[0037] It should be noted that the MCU 240 may include a physical layer circuit (PHY) for driving and receiving signals through an interface to the memory device. Alternatively, the PHY circuit may be inserted between the MCU and the memory device.

[0038] Read data returned from the memory may be provided by the MCU 240 to a request queue 210 coupled to the communication fabric for return to the source component. Similarly, if a given write command includes a response, the response may be provided by the MCU 240 to the request queue 210, or to a corresponding set of output queues. For simplicity, the return data path is not shown in FIG. Figure 2 Shown in.

[0039] Now go to FIG. 3A to FIG. 3F , recall the various constraints imposed by the LP5 memory standard. First, a memory bank requires two activation cycles. Second, various timing parameters must be considered, including the timing between the second activation of the bank and the read or write to the bank (e.g., in one embodiment, tRCDr = 15 cycles for a read), and the timing between the read or write and the data (e.g., 17 cycles for a read in one embodiment). Third, due to the frequency of LP5 memory, the data for access appears on the data bus as two beats, each with two cycles, with idle time between the two beats. Finally, the LP5 standard specifies that in one mode, a synchronization command (which starts the data clock) will be scheduled to occur the cycle before the first read or write in a multi-bank memory operation. (As already noted, there are other options for synchronization in LP5, such as an always-on mode, but that mode consumes more power.)

[0040] Power consumption is one of several design considerations that are taken into account when attempting to schedule memory operations. In addition to being judicious in turning on the data bus clock, it is also important to ensure that the data bus is utilized to the maximum extent during memory operations, i.e., the number of data "holes" (i.e., bus cycles with no data) is kept to a minimum. A certain amount of non-utilization is inevitable, particularly when initiating a transaction or switching from a series of reads (e.g., a "read turn") to a series of writes (e.g., a "write turn"). Therefore, the inventors have sought to achieve as high a utilization of the memory data bus as possible during a single pass through the memory banks of a memory device. However, in doing so, care must be taken to ensure that no contention occurs on either the command bus or the data bus. In other words, a scheduling scheme that would result in two commands (or two beats of data from different memory banks) needing to appear on the command bus or the data bus at the same time cannot be adopted.

[0041] Given these various challenges, it is clear that there are many different possible ways to schedule LP5 memory transactions. However, as will be shown below, many of these possibilities will lead to situations that cause undesirable results, including data holes, command bus contention, and / or data bus contention. FIG. 3A to FIG. 3E Several of these possibilities are described. Figure 3F A scheduling paradigm is described that maximizes bus utilization without experiencing command or data bus contention.

[0042] FIG. 3A to FIG. 3F34. Table 35 is a table describing the timing of various aspects of read accesses to eight memory banks labeled A through H. (The timing for write accesses will be similar to that shown for reads.) Both the activity occurring on the command bus and the data bus are shown. On the command bus, the timing of the two activate commands for a given bank, the sync command before the first read, and the RD command are all shown; while on the data bus, the timing of two beats of data is shown. Recall that each beat of data is two clock cycles in length. Therefore, the data beat that begins in cycle 33 ends in cycle 34.

[0043] The timing of the read command is governed by the memory parameter tRCDr, which in our example is 15 clock cycles. As stated previously, this parameter means that a read (RD) command for a given bank may occur as soon as 15 clock cycles after the second activation for that bank. Thus, if the second activation for a bank is at clock cycle 2, an RD command may be issued for that bank at clock cycle 17. Similarly, the timing between the RD command and the corresponding data appearing on the data bus is given by the parameter RL, which in this example is equal to 17 clock cycles.

[0044] Figure 3A Table 310 is shown indicating the resulting timing if the activate commands were issued one after the other without a break (i.e., on cycles 0 and 1 for bank A, on cycles 2 and 3 for bank B, etc.). Table 310 shows that this approach will result in contention on both the command bus and the data bus. Specifically, the sync command will conflict with the second activate for bank H, which will be scheduled at cycle 15 because it is one cycle before RD at cycle 16. Furthermore, it can be seen that with this schedule, there will also be significant contention on the data bus. (Content on both the command bus and the data bus is Figure 3A ) Therefore this method is not applicable.

[0045] Figure 3B Table 320 is shown, which depicts an alternative method in which the first activation commands for the banks are spaced at four clock cycle intervals. Thus, the first activation command for bank A is at 0 cycles, the first activation command for bank B is at 4 cycles, etc. This example similarly experiences contention. It can be seen that the RD command for banks A to D conflicts with the first activation command for banks E to H. In addition, the second data beat for a given bank conflicts with the first data beat for the next bank.

[0046] Figure 3CTable 330 is shown, which depicts yet another method, in which the first activation command for the storage bank is not only separated by six clock cycle intervals, but the first activation command and the second activation command are also separated by the interval clock cycle. For example, the activation command for storage bank A is scheduled at cycles 0 and 2, while the activation command for storage bank B is scheduled at cycles 6 and 8, etc. Although this scheduling results in no competition on the command bus or the data bus, it also results in inefficiency on the data bus. It can be seen that this example results in data bus holes at cycles 36 to 37, 42 to 43, 48 to 49, 54 to 55, 60 to 61, 66 to 67, 72 to 73, and 78 to 79.

[0047] One discovery made by the inventors in solving this problem is that the activation command should be scheduled every other clock cycle, while other commands should be scheduled in alternate clock cycles. For example, even clock cycles can be reserved for activation commands, while other commands are reserved for odd clock cycles. (Of course, activation commands can also be scheduled in odd clock cycles, while other commands are scheduled in even clock cycles.) This method is Figure 3D As shown in Table 340 in . It can be seen that this approach still has two disadvantages. First, there is a competition between the timing of the synchronization command (cycle 16, one cycle before RD at cycle 17) and the first activation command for memory bank E.

[0048] The second discovery of the inventors is that every other read / write command is delayed beyond the minimum required timing. Figure 3E Table 350 describing such a method is shown. Figure 3E , every other RD command (starting with the first command) is delayed by more than the minimum system timing (e.g., more than tRCDr) by two cycles. Therefore, it can be seen that for accesses to banks A, C, E, and G, the delay between the second activation command and the RD command is 17 cycles. In contrast, for banks B, D, F, and H, the delay between the second activation command and the RD command is 15 cycles. This approach produces a "2-6" timing step. Therefore, the timing between the RD for banks A and B is two cycles, while the timing between the RD for banks B and C is six cycles. This pattern continues because the RD timing difference is two cycles between banks C and D, and six cycles between banks D and E. It is noteworthy that the contention on the data bus has now been eliminated. In addition, since the data on the data bus is fully interleaved during this time period, the data bus is also fully utilized between cycles 36 to 66.

[0049] This approach still has a scheduling problem. Under the LP5 standard, there are multiple ways to handle synchronization commands. The "always-on" synchronization mode allows synchronization commands to be scheduled as needed, but this approach means that the data bus will be turned on even when it is not needed, thus consuming power unnecessarily. However, scheduling the synchronization command in the most efficient way possible (i.e., in cycle 18, one cycle before the first RD command) conflicts with the second activation of memory bank E.

[0050] The inventors have recognized that the problem of synchronization command timing can be solved by adding a new operating mode for the memory device 150. The control circuit 120 can then be configured to set the memory device 150 to a "sync delay mode". In general, this sync delay mode delays the memory device's action on a received synchronization command by one or more cycles. Consider a situation where the memory specification indicates that the synchronization command will precede the read / write by an odd number of cycles, but doing so will place the synchronization in a cycle reserved for the activation command. The sync delay mode can be used to delay the synchronization command internally in the memory by a certain number of odd clock cycles, with the result that the synchronization command appears on the command bus 144 in an odd clock cycle, and the synchronization command will be acted on by the memory device in an even clock cycle (as specified by the memory).

[0051] In one embodiment using such a mode, the memory device 150 will internally delay received sync commands by one cycle. The effect is that instead of a sync command scheduled in cycle N causing the data bus clock to start in cycle N+1, a sync command scheduled in cycle N will cause the data bus clock to start in cycle N+2. This mode will allow sync commands to be scheduled on the command bus two cycles before a read or write, but due to the internal delay, the memory will effectively treat the sync as occurring one cycle before the read / write.

[0052] In alternative embodiments, other amounts of synchronization delay are possible. The proposed synchronization delay mode can also be used in settings other than the proposed 2 / 6 or 6 / 2 timing steps. The memory device implementing delayed synchronization includes a decoding circuit configured to decode various memory device commands, which memory device commands include commands to set a synchronization delay mode with a specified number of delay cycles. The decoding circuit is also configured to decode the synchronization command itself. Alternatively, instead of a synchronization delay mode command, the synchronization command format can include a desired number of delay cycles as a parameter, with no delay as the default.

[0053] After decoding the command, the decoding circuit is configured to route the command to the appropriate logic unit for executing the command in the memory device. For the synchronous command, the memory device includes a synchronous execution circuit configured to start the data bus clock. In one embodiment, the decoding circuit can delay the sending of the synchronous command until the specified delay is passed. In another embodiment, the synchronous execution circuit may include a multi-bit counter. When receiving the synchronous command, the decoding circuit may pass the synchronous command to the synchronous execution circuit together with the desired delay amount. Then, the synchronous execution circuit will program the counter with the specified delay, and then start the data bus clock after the counter reaches zero. (When the synchronous delay mode is not activated, the delay parameter will be zero and the counter may not be used.) Various other specific implementations of the memory device for realizing synchronous delay are also possible. Further note that the memory device may be configured to internally delay commands other than the synchronous command as needed for different situations, particularly when there is an inconsistency between the desired memory bus scheduling and the required memory device timing.

[0054] In any case, when sync delay mode is enabled, this allows adjusting the Figure 3E In the case where the memory device 150 operates in the sync delay mode, scheduling the sync command in cycle 17 will produce the same effect as scheduling the command in cycle 18 without the sync delay mode. Figure 3F The result of improved bus utilization and no contention is shown in . In addition, the scheduling paradigm is relatively straightforward to implement within the scheduler circuit 244 .

[0055] In addition, there is no loss of latency or efficiency in terms of switching from a write round to a read round (or vice versa). Consider a scenario where the first cycle in which a write round is occurring and a read can be performed is cycle 100. In a previous design, assuming a tRCDr value of 15 cycles, the first activation would be at cycle 83 and the second activation would be at cycle 85, which would allow a read operation at cycle 100. However, in one specific implementation of the present disclosure, the first read (or write) in a set of transactions is delayed by two clock cycles beyond its specified tRCDr value, which means that the first read / write will instead occur at tRCDr+2 cycles. But since the previous write activation at the end of the write round will occur a sufficient number of cycles earlier, the first activation and second activation for the initial read in the read round can occur at cycles 81 and 83, respectively. This timing will still allow the first read to occur at cycle 100 after a delay of tRCDr+2 cycles.

[0056] FIG. 4A to FIG. 4J Shown according to Figure 3FThe described scheduling example implements different portions of a single timing diagram for a read operation. Each of FIG. 4 shows 10 to 12 cycles of CCK corresponding to the command clock signal 142. Figure 4A At the beginning of cycle 0, and Figure 4J Ends at cycle 100. Sixteen banks (AP) are addressed in this multi-bank memory operation. The dashed arrows indicate where every other read command is delayed by two cycles beyond tRCDr (i.e., 17 cycles instead of 15 cycles after the second activation). Data begins to appear at cycle 36. When the second data beat for the last bank (bank P) is completed, the data bus 146 is maximized between cycle 36 and cycle 100.

[0057] FIG. 4A to FIG. 4J The specific implementation shown in has a repeated 2 / 6 pace. The delay between the number of cycles for scheduling RD commands for the first memory bank and the second memory bank is two cycles, while the delay between the number of RD cycles for the second memory bank and the third memory bank is six cycles. This pattern can be repeated until all memory banks are addressed.

[0058] FIG. 5A to FIG. 5J Different portions of a single timing diagram for a write operation also implemented according to the 2 / 6 timing mode are shown. In some cases, the minimum timing parameters for writes are different from the minimum timing parameters for reads. Here, tRCDw is 7 cycles, and WL is 9 cycles, WL being the time delay between when a write command is scheduled and when write data can be written on the bus. Once again, the data bus 146 is utilized to the maximum extent between cycles 20 to 83 (i.e., there are no data gaps).

[0059] As pointed out, FIG. 4A to FIG. 4J and FIG. 5A to FIG. 5J The operations depicted in FIG. 1 follow a 2 / 6 timing pace. Thus, the read / write commands for the first given memory bank to be addressed and the second consecutive given memory bank are scheduled to be two cycles apart from the command clock signal. Furthermore, the read / write commands for the second given memory bank to be addressed and the third consecutive given memory bank are scheduled to be six cycles apart from the command clock signal. This pattern is repeated throughout the memory operation.

[0060] on the other hand, FIG. 6A to FIG. 6J shows different portions of a single timing diagram for a write operation implemented according to the 6 / 2 timing mode. The write operation shown in this diagram has the same FIG. 5A to FIG. 5J Same timing parameters as in : tRCDw is 7 cycles, and WL is 9 cycles. FIG. 4A to FIG. 4J and FIG. 5A to FIG. 5JAgain, it is still the case that every other write command is delayed beyond the minimum timing parameter by two cycles. But unlike the 2 / 6 timing mode, where odd-numbered accesses are delayed and even-numbered accesses are not, for the 6 / 2 timing mode, the situation is reversed. Here, the initial access (to bank A) is not delayed because the write data appears on the bus seven cycles after the second activation. The second access (to bank B) is delayed by two cycles and is therefore scheduled for cycle 15. Unlike the 2 / 6 timing mode, FIG. 6A to FIG. 6J The 6 / 2 timing pattern shown in has two holes in the data bus between the initial data beat and the final data beat: there are gaps in clock cycles 20 to 21 and 82 to 83. Otherwise, the data bus bandwidth is fully utilized.

[0061] Therefore, in the 6 / 2 timing mode, the read / write commands for the first given memory bank to be addressed and the second consecutive given memory bank are scheduled to be six cycles of the command clock signal apart. In addition, the read / write commands for the second given memory bank to be addressed and the third consecutive given memory bank are scheduled to be two cycles of the command clock signal apart. This pattern is repeated throughout the memory operation.

[0062] Exemplary Methods

[0063] Figure 7 is a flow chart illustrating one embodiment of a method for implementing the disclosed memory scheduling techniques. Figure 7 The method shown can be used in conjunction with any of the computer circuits, systems, devices, elements or components disclosed herein. In various embodiments, some of the method elements shown can be performed concurrently in an order different from the order shown, or can be omitted. Additional method elements can also be performed as needed.

[0064] The method 700 begins at 710, where the memory controller initiates a pacing for a multi-bank memory operation, such as a burst operation. As described below, the pacing includes scheduling commands on the interface relative to a clock signal that clocks the interface to the memory. In one embodiment, the method 700 may be performed with respect to a synchronous DRAM device, such as a memory device that complies with the LP5 standard. The pacing includes 720 and 730, which are performed with respect to a given memory bank and a next memory bank in a sequence of memory banks addressed by the multi-bank memory operation, respectively. For example, 720 may be performed with respect to bank A in the memory, while 730 may be performed with respect to bank B.

[0065] In 720, the memory controller schedules a first activation command, a second activation command, and a type command that specifies the type of command to be executed (e.g., read or write). The second activation command is scheduled to occur two clock cycles after the first activation command. In addition, the type command is scheduled to occur in a first time period after the second activation command, where the first time period is equal to two clock cycles plus a minimum timing delay specified for the memory device. The minimum timing delay may correspond to, for example, a RAS to CAS delay that specifies a minimum amount of time that must elapse from the bank activation until the type command can appear on the command bus.

[0066] In some memory specifications, this minimum timing delay may be referred to as tRCDr for a read command and tRCDw for a write command. For example, if a read operation to memory bank A is scheduled in 720 and tRCDr=7 clock cycles, the read operation will be scheduled at least 9 clock cycles (7 tRCDr cycles plus 2 delay cycles) after the second activation command to memory bank A.

[0067] In 730, the memory controller schedules a third activation command, a fourth activation command, and another instance of the type command specified in 720. (The third activation command and the fourth activation command are different instances of the first activation command and the second activation command, respectively.) As in 720, the fourth activation command is scheduled to occur two clock cycles after the third activation command. The type command in 730 is scheduled to occur in a second time period after the fourth activation command, where the second time period is equal to the minimum timing delay. For example, if a read operation to memory bank B is scheduled in 730 and tRCDr=7 clock cycles, the read operation will be scheduled 7 clock cycles after the fourth activation command for memory bank B. Therefore, unlike 720, the type command in 730 is scheduled so that it is delayed by no more than the minimum system timing requirement.

[0068] Next, in step 740, the memory controller repeats the steps described in steps 720 and 730 for additional pairs of memory banks in the memory device to continue the multi-bank memory operation. For example, the next step may address banks C and D, where a type command to bank C is delayed by two cycles, but a type command to bank D is not delayed.

[0069] In various embodiments, the memory controller schedules activate commands on even cycles, while type commands such as reads and writes are scheduled to occur on alternate odd cycles.

[0070] In implementations where an activate command is scheduled every other clock cycle (e.g., bank A in cycles 0 and 2, bank B in cycles 4 and 6, etc.), this can cause problems for the implementation of sync commands because the most power efficient sync mode in the LP5 standard specifies that sync commands should be scheduled in the clock cycle immediately preceding a command of the corresponding type, such as a read or write. This presents a potential problem in examples where a read / write command is preceded by a cycle reserved for an activate command (e.g., a read / write command scheduled for cycle 11 cannot be preceded by a sync command in cycle 10 because cycle 10 and other even cycles are reserved for activate commands).

[0071] Thus, the memory device may be equipped with a synchronization delay mode in which the memory device internally delays the received synchronization signal by one clock cycle upon receipt. This allows the paradigm of retaining every other clock cycle for the activate command to work in the context of LP5 memory. In such embodiments, the method 700 may also include the memory controller setting the synchronization delay mode for the memory device and then scheduling the synchronization command two clock cycles before the corresponding type command for the initial memory bank addressed in the multi-bank memory operation.

[0072] One effect of method 700 can be to improve the utilization of the memory data bus during multi-bank memory operation. In some memories such as LP5, the frequency for moving data into or out of the memory is high enough so that the data associated with the memory access includes two data beats, each of which is two clock cycles long. Also due to timing, the two beats are separated by two clock cycles. This allows the interleaving of data from different banks. In fact, once the initial waiting time of the memory device has passed and data for multi-bank memory operations begins to appear on the data bus, the implementation scheme of application method 700 can lead to full utilization of the data bus.

[0073] Exemplary Devices

[0074] Reference now Figure 8, which shows a block diagram of an exemplary embodiment of device 800. In some embodiments, elements of device 800 may be included in a system on a chip. In some embodiments, device 800 may be included in a mobile computing device that may be battery powered. Therefore, the power consumption of device 800 may be an important design consideration. In the illustrated embodiment, device 800 includes structure 810, computing complex 820, input / output (I / O) bridge 850, cache / memory controller 845, graphics unit 875, and display unit 865. In some embodiments, in addition to or in place of the components shown, device 800 may include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0075] The structure 810 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various elements of the device 800. In some embodiments, portions of the structure 810 may be configured to implement various different communication protocols. In other embodiments, the structure 810 may implement a single communication protocol, and elements coupled to the structure 810 may be internally converted from the single communication protocol to other communication protocols.

[0076] In the illustrated embodiment, the computing complex 820 includes a bus interface unit (BIU) 825, a cache 830, and cores 835 and 840. In various embodiments, the computing complex 820 may include various numbers of processors, processor cores, and caches. For example, the computing complex 820 may include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, the cache 830 is a group-associative L2 cache. In some embodiments, the cores 835 and 840 may include internal instruction and data caches. In some embodiments, a consistency unit (not shown) in the structure 810, cache 830, or elsewhere in the device 800 may be configured to maintain consistency between the various caches of the device 800. The BIU 825 may be configured to manage communications between the computing complex 820 and other elements of the device 800. Processor cores (such as cores 835 and 840) may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions.

[0077] The cache / memory controller 845 may be configured to manage data transfers between the structure 810 and one or more caches and memories. For example, the cache / memory controller 845 may be coupled to an L3 cache, which in turn may be coupled to system memory. In other embodiments, the cache / memory controller 845 may be coupled directly to the memory. In some embodiments, the cache / memory controller 845 may include one or more internal caches.

[0078] As used herein, the term "coupled to" may indicate one or more connections between elements, and a coupling may include intermediate elements. Figure 8 In FIG, graphics unit 875 may be described as being "coupled to" memory via structure 810 and cache / memory controller 845. In contrast, in Figure 8 In the illustrated embodiment, graphics unit 875 is "directly coupled" to structure 810 because there are no intervening elements.

[0079] Graphics unit 875 may include one or more processors, such as one or more graphics processing units (GPUs). For example, graphics unit 875 may receive graphics-oriented instructions, such as Metal or Instructions. The graphics unit 875 may execute dedicated GPU instructions or perform other operations based on the received graphics-oriented instructions. The graphics unit 875 may generally be configured to process large blocks of data in parallel and may construct images in a frame buffer for output to a display, which may be included in the device or may be a separate device. The graphics unit 875 may include transformation, lighting, triangle, and rendering engines in one or more graphics processing pipelines. The graphics unit 875 may output pixel information for displaying an image. In various embodiments, the graphics unit 875 may include a programmable shader circuit, which may include a highly parallel execution core configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computational tasks (which may be graphics-related or may not be graphics-related).

[0080] The display unit 865 may be configured to read data from the frame buffer and provide a stream of pixel values ​​for display. In some embodiments, the display unit 865 may be configured as a display pipeline. In addition, the display unit 865 may be configured to blend multiple frames to produce an output frame. In addition, the display unit 865 may include one or more interfaces (e.g., a touch screen or an external display) for coupling to a user display (e.g., or embedded DisplayPort (eDP).

[0081] The I / O bridge 850 may include various elements configured to implement, for example, universal serial bus (USB) communications, security, audio, and low-power always-on functionality. The I / O bridge 850 may also include, for example, interfaces such as pulse width modulation (PWM), general purpose input / output (GPIO), serial peripheral interface (SPI), and inter-integrated circuit (I2C). Various types of peripherals and devices may be coupled to the device 800 via the I / O bridge 850.

[0082] In some embodiments, the device 800 includes a network interface circuit (not explicitly shown), which can be connected to the structure 810 or the I / O bridge 850. The network interface circuit can be configured to communicate via various networks, which can be wired networks, wireless networks, or both. For example, the network interface circuit can be configured to communicate via a wired local area network, a wireless local area network (e.g., via WiFi) or a wide area network (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuit is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuit is configured to communicate using device-to-device communication (e.g., Bluetooth or WiFi Direct) and the like. In various embodiments, the network interface circuit can provide the device 800 with connections to various types of other devices and networks.

[0083] Example Applications

[0084] Now go to Fig. 9 , various types of systems that may include any of the circuits, devices, or systems discussed above are shown. Systems or devices 900 that may incorporate or otherwise utilize one or more of the techniques described herein may be used in a wide variety of fields. For example, system or device 900 may be used as part of the hardware of a system such as a desktop computer 910, a laptop computer 920, a tablet computer 930, a cellular or mobile phone 940, or a television 950 (or a set-top box coupled to a television).

[0085] Similarly, the disclosed elements can be used in a wearable device 960, such as a smart watch or a health monitoring device. In many embodiments, a smart watch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. The wearable device can also be designed to perform only health monitoring functions, such as monitoring the user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices that can be implanted in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0086] The system or device 900 may also be used in various other contexts. For example, the system or device 900 may be used in the context of a server computer system (such as a dedicated server) or on shared hardware that implements a cloud-based service 970. Further, the system or device 900 may be implemented in a wide range of dedicated everyday devices, including common devices 980 in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is generally referred to as the "Internet of Things" (IoT). Elements may also be implemented in various modes of transportation. For example, the system or device 900 may be used for control systems, guidance systems, entertainment systems, etc. of various types of vehicles 990.

[0087] Fig. 9 The applications shown in are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other exemplary applications include, but are not limited to: portable game devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0088] Exemplary computer readable media

[0089] The disclosure has described various exemplary circuits in detail above. It is intended that the disclosure encompass not only embodiments including such circuits, but also computer-readable storage media including design information specifying such circuits. Thus, the disclosure is intended to support claims that encompass not only apparatus including the disclosed circuits, but also storage media that specify the circuits in a format recognized by a manufacturing system configured to produce hardware (e.g., an integrated circuit) that includes the disclosed circuits. Claims to such storage media are intended to cover, for example, entities that generate a circuit design but do not manufacture the design itself.

[0090] Fig.10 1010 is a block diagram illustrating an exemplary non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, semiconductor manufacturing system 1020 is configured to process design information 1015 stored on non-transitory computer-readable medium 1010 and manufacture integrated circuit 1030 based on design information 1015.

[0091] The non-transitory computer-readable storage medium 1010 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1010 may be an installation medium, such as a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register, or other similar type of memory element, etc. The non-transitory computer-readable storage medium 1010 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1010 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0092] The design information 1015 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 1015 may be used by the semiconductor manufacturing system 1020 to manufacture at least a portion of the integrated circuit 1030. The format of the design information 1015 may be recognizable by at least one semiconductor manufacturing system 1020. In some embodiments, the design information 1015 may also include one or more cell libraries that specify the synthesis, layout, or both of the integrated circuit 1030. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies the cell library elements and their connectivity. The design information 1015 obtained separately may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, the design information 1015 may specify the circuit elements to be manufactured, but not their physical layout. In this case, the design information 1015 may need to be combined with the layout information to actually manufacture the specified circuit.

[0093] In various embodiments, integrated circuit 1030 may include one or more custom macrocells, such as memory, analog or mixed signal circuits, etc. In this case, design information 1015 may include information related to the included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0094] Semiconductor manufacturing system 1020 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1020 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0095] In various embodiments, integrated circuit 1030 is configured to operate according to the circuit design specified by design information 1015, which may include performing any of the functions described herein. For example, integrated circuit 1030 may include Figure 1 or Figure 2 Any of the various elements shown in . In addition, integrated circuit 1030 can be configured to perform various functions described herein in conjunction with other components. In addition, the functionality described herein can be performed by multiple connected integrated circuits.

[0096] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0097] ***

[0098] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," etc. do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or substitutions that fall within the spirit or scope of this disclosure.

[0099] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why a particular implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuits outside the scope of the present disclosure, which, in combination with one of the disclosed embodiments, negate or weaken one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or weaken the disclosed advantages. Even if a specific implementation of the technology is assumed, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, any potential advantages described herein should not be understood as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to show one or more types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0100] Unless otherwise indicated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described for a particular feature. The embodiments disclosed by the present invention are intended to be illustrative and non-restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalent forms, which will be apparent to those skilled in the art who are aware of the effective effects of the present disclosure.

[0101] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this patent application (or a patent application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0102] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and may be claimed in this or another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0103] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0104] ***

[0105] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0106] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" item refers to a collection of two or more items.

[0107] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0108] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0109] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," thus covering 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0110] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0111] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. In addition, unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0112] The phrase "based on" or is used to describe one or more factors that influence a determination. This term does not exclude that there may be additional factors that may influence the determination. That is, a determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0113] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B, A is performed." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0114] ***

[0115] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to an intangible thing.

[0116] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0117] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After being appropriately programmed, the FPGA may then be considered "configured to" perform the particular function.

[0118] For purposes of U.S. patent applications based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” structure to phrase the claim element.

[0119] Different "circuits" may be described in the present disclosure. These circuits or "circuitry" constitute hardware, which includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits can be custom designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuit systems.

[0120] Thus, the disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For a person skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0121] In various embodiments, as described in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement relative to each other and such circuits / units / components and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by coding a description of a circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without excessive experimentation and using the application of ordinary technicians. HDL descriptions are often expressed in a way that can be displayed as functional. However, for those skilled in the art, the HDL description is a way to convert the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is transmitted to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuitry. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0122] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0123] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

Claims

1. A memory device, comprising: a plurality of memory bank circuits, a given memory bank circuit of the plurality of memory bank circuits comprising a corresponding set of memory cell circuits; a command bus circuit configured to receive a plurality of memory commands; a data bus circuit configured to transfer data to or from one or more of the memory cell circuits in response to a memory command of the plurality of memory commands; and A memory pipeline circuit, wherein the memory pipeline circuit is configured to: receiving, via the command bus circuit, a synchronization command executable by the memory device to enable a clock signal of the data bus circuit; enabling a clock signal of the data bus circuit after a delay period based at least on an indication of the synchronous delay mode; as well as Based at least on the absence of the indication of the synchronous delay mode, the clock signal of the data bus circuit is enabled without the delay period.

2. The memory device according to claim 1, wherein: the synchronization command including an operand indicating a number of command bus cycles to wait before initiating the clock signal of the data bus; as well as The memory pipeline circuit is further configured to determine whether the synchronous delay mode is indicated based on the value of the operand.

3. The memory device according to claim 1, wherein: The memory pipeline circuit is further configured to: receiving a mode command before receiving the synchronization command; and Based at least on the execution of the mode command, the memory device is caused to enable the synchronization delay mode.

4. The memory device according to claim 1, wherein: The memory pipeline circuit includes a command decoding circuit and a command execution circuit.

5. The memory device according to claim 4, wherein: The command decoding circuit is configured to: decoding the synchronization command; and A determination is made whether to route the synchronization command to the command execution circuit after the delay period based at least on the indication of the synchronization delay pattern.

6. The memory device according to claim 4, wherein: The command decoding circuit is configured to: decoding the synchronization command; and Regardless of the indication of the synchronization delay mode, the synchronization command is routed to the command execution circuit without the delay period.

7. The memory device according to claim 6, wherein: The command execution circuit is configured to: enabling the clock signal of the data bus circuit after the delay period based at least on the indication of the synchronous delay mode; and Based at least on the absence of the indication of the synchronous delay mode, the clock signal of the data bus circuit is enabled without the delay period.

8. The memory device according to claim 7, wherein: The command execution circuit includes a counter circuit; and Wherein, the command execution circuit is configured to use the counter circuit to wait for the delay time period.

9. A method comprising: A specific series of commands for accessing a plurality of memory banks in the memory circuit is received by the memory circuit within a first plurality of command bus cycles, comprising: receiving a set of activation commands for a specific memory bank among the plurality of memory banks; receiving a synchronization command after a specific number of command bus cycles since receiving the set of activation commands; and Based at least on the indication of the synchronization delay mode, the data bus clock signal is activated after a delay of one or more command bus cycles from receipt of the synchronization command.

10. The method according to claim 9, further comprising: Receiving, by the memory circuit in a second plurality of command bus cycles, a different series of commands for accessing the plurality of memory banks in the memory circuit, comprising: receiving a different set of activation commands for the specific storage body; receiving a different synchronization command after a different number of command bus cycles since receiving the different set of activate commands; and The data bus clock signal is activated without delay on the subsequent command bus cycle.

11. The method according to claim 9, further comprising: After the delay of one or more command bus cycles, a read command is received for the particular memory bank.

12. The method according to claim 11, further comprising: The data requested by the read command is sent on the data bus using the activated data bus clock signal.

13. The method according to claim 9, wherein: The synchronization command includes an indication of a number of command bus cycles to delay before initiating the data bus clock signal.

14. The method according to claim 9, further comprising: Prior to receiving the particular series of commands, an indication to enter the synchronization delay mode is received.

15. An apparatus comprising: a memory interface circuit configured to couple to a memory device via a command bus including a command clock signal and a data bus including a data clock signal, wherein the memory device includes a plurality of memory banks; and a control circuit coupled to the memory interface circuit and configured to: sending a set of activation commands indicative of a particular memory bank of the memory device; sending a synchronization command a plurality of command clock cycles after sending a last activation command in the set of activation commands, the synchronization command causing the memory device to pause a determined number of command clock cycles and then start the data clock signal; as well as After the determined number of command clock cycles, a read command for the particular memory bank is sent.

16. The device according to claim 15, wherein: The determined number of command clock cycles is greater than one.

17. The device according to claim 15, wherein: The control circuit is further configured to include an operand in the synchronization command, wherein the operand indicates the determined number of command clock cycles to pause.

18. The device according to claim 17, wherein: The control circuit is further configured to omit the operand in the synchronization command, and wherein omitting the operand causes the memory device to start the data clock signal without delay.

19. The device according to claim 15, wherein: The control circuit is further configured to include a sync delay mode command prior to sending the sync command, wherein the sync delay mode command causes the memory device to pause the determined number of command clock cycles.

20. The device according to claim 15, wherein: The control circuit is further configured to receive data requested by the read command on the data bus using the data clock signal.

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