Multi-core heterogeneous chip starting control method and starting control system

Abstract

The invention provides a multi-core heterogeneous chip starting control method and system, and the method comprises the steps: enabling a small core to read a small core starting code from a plug-in nonvolatile memory, and completing the starting of the small core when a BROM in a multi-core heterogeneous chip fails; and then copying the large-core repair code from the plug-in nonvolatile memory to the large-core random access memory through the small core to assist the large core to finish starting, so that the risk of failure of the multi-core heterogeneous chip caused by a BROM design error can be avoided. In a multi-core heterogeneous chip, a large-core circuit is relatively complicated, so that a boot program is also complicated and is easy to make mistakes, therefore, a mechanism that a small core can also start a large core is added, and when the BROM code design of the large core is wrong, the roles of the large core and the small core responsible for starting are exchanged, so that the small core can start and guide the whole system, and a double-insurance effect is achieved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a multi-core heterogeneous chip startup control method and startup control system. Background Art

[0002] Generally, a read-only ROM memory (generally called BootROM or BROM) is integrated inside the SoC chip to store the default initialization code that runs when the chip is powered on. This initialization code is used to handle firmware upgrades and boot the system from different storage devices (such as NandFlash, eMMC, SDCARD, etc.). It should be noted that the initialization code in the BROM must be determined before the chip is put into production, and the code cannot be changed, or the cost of changing it is very high.

[0003] The Chinese patent with publication number CN117215823A provides a chip boot code repair method and repair system, which can avoid the problem of chip unavailability caused by boot code design defects. At present, robot main control chips generally adopt large and small core heterogeneous CPU design, such as STMicroelectronics' STM32MP157 chip, the large core adopts a dual-core Arm Cortex-A7 CPU to run the Linux operating system, and the small core adopts an Arm Cortex-M4 CPU to run RTOS. However, the above-mentioned Chinese patent does not take into account the applicability of its technical solution in the design of heterogeneous large and small core chips, which needs to be improved. Summary of the invention

[0004] The present application provides a multi-core heterogeneous chip startup control method and startup control system, and the specific technical solutions are as follows: A multi-core heterogeneous chip startup control method, the multi-core heterogeneous chip startup control method comprising the following steps: step S1, after the multi-core heterogeneous chip is powered on, the multi-core heterogeneous chip runs a large core startup code, and then detects whether the multi-core heterogeneous chip starts abnormally during the running of the large core startup code, if not, continues to run the large core startup code until the multi-core heterogeneous chip starts normally, if so, enters step S2; step S2, the multi-core heterogeneous chip enables the small core to run the small core startup code stored in a non-volatile memory to complete the startup of the small core, and then enters step S3; step S3, based on the abnormal position of the large core startup code, the multi-core heterogeneous chip copies the large core startup code and / or the large core repair code stored in the non-volatile memory to the large core random access memory through the small core to repair the abnormal part of the large core startup code.

[0005] Further, in the step S1, the method for detecting whether the multi-core heterogeneous chip starts abnormally during the execution of the large core startup code includes: before the large core startup code runs normally, the watchdog records the time consumed by the current startup once at a preset time interval, and then compares it with the first preset startup timeout time. If the time consumed by the current startup is greater than or equal to the first preset startup timeout time, the multi-core heterogeneous chip starts abnormally during the execution of the large core startup code; if the time consumed by the current startup is less than the first preset startup timeout time, the multi-core heterogeneous chip does not start abnormally during the execution of the large core startup code.

[0006] Furthermore, in step S2, the non-volatile memory is Flash, which is mounted on the small core and communicates with the small core through the XIP mechanism.

[0007] Further, in step S3, based on the abnormal position of the large core startup code, the multi-core heterogeneous chip copies the large core startup code and / or the large core repair code stored in the non-volatile memory to the large core random access memory through the small core to repair the abnormal part of the large core startup code. The method includes: based on the abnormal position of the large core startup code, making a repair mark at the corresponding position of the large core repair code stored in the non-volatile memory, and when the large core startup code is not completely abnormal, copying the non-abnormal part of the large core startup code and the large core repair code with the repair mark in the non-volatile memory to the large core random access memory to repair the abnormal part of the large core startup code.

[0008] Further, in step S3, based on the abnormal position of the large core startup code, the multi-core heterogeneous chip copies the large core startup code and / or the large core repair code stored in the non-volatile memory to the large core random access memory through the small core to repair the abnormal part of the large core startup code. The method includes: based on the abnormal position of the large core startup code, making a repair mark at the corresponding position of the large core repair code stored in the non-volatile memory, and when all the large core startup codes are abnormal, all the large core repair codes stored in the non-volatile memory are copied to the large core random access memory to repair the large core startup code.

[0009] Furthermore, after the abnormal part of the large core startup code is repaired, the multi-core heterogeneous chip sets the large core reset startup address to the large core random access memory through the small core and controls the large core to reset. After reset, the repaired large core startup code in the large core random access memory is run to enable the multi-core heterogeneous chip to start normally.

[0010] Furthermore, in step S1, the method of continuing to run the big core startup code until the multi-core heterogeneous chip starts normally includes: after the big core startup code runs normally, the multi-core heterogeneous chip copies the small core startup code to the small core random access memory through the big core for execution; if there is no startup abnormality in the multi-core heterogeneous chip during the execution of the small core startup code, it is detected whether the small core has an external non-volatile memory; if not, the small core is put into a state of waiting for reset; if so, the small core is made to run the preset code stored in the non-volatile memory through the XIP mechanism, and then enters a low power consumption mode.

[0011] Furthermore, after the multi-core heterogeneous chip copies the small core startup code to the small core random access memory through the big core and runs it, if the multi-core heterogeneous chip starts abnormally during the running of the small core startup code, then based on the abnormal position of the small core startup code, the multi-core heterogeneous chip enables the small core to copy the small core startup code and / or the small core repair code stored in the non-volatile memory to the small core random access memory to repair the abnormal part of the small core startup code.

[0012] Furthermore, the method for detecting whether the multi-core heterogeneous chip starts abnormally during the execution of the small core startup code includes: before the small core startup code runs normally, the watchdog records the time consumed by the current startup once every preset time interval, and then compares it with the second preset startup timeout time. If the time consumed by the current startup is greater than or equal to the second preset startup timeout time, the multi-core heterogeneous chip starts abnormally during the execution of the small core startup code; if the time consumed by the current startup is less than the second preset startup timeout time, the multi-core heterogeneous chip does not start abnormally during the execution of the small core startup code.

[0013] Furthermore, based on the abnormal position of the small core startup code, the method in which the multi-core heterogeneous chip enables the small core to copy the small core startup code and / or the small core repair code stored in the non-volatile memory to the small core random access memory to repair the abnormal part of the small core startup code includes: based on the abnormal position of the small core startup code, making a repair mark at the corresponding position of the small core repair code stored in the non-volatile memory, and when the small core startup code is not entirely abnormal, copying the non-abnormal part of the small core startup code and the small core repair code with the repair mark in the non-volatile memory to the small core random access memory to repair the abnormal part of the small core startup code.

[0014] Furthermore, based on the abnormal position of the small core startup code, the method in which the multi-core heterogeneous chip enables the small core to copy the small core startup code and / or the small core repair code stored in the non-volatile memory to the small core random access memory to repair the abnormal part of the small core startup code includes: based on the abnormal position of the small core startup code, making a repair mark at the corresponding position of the small core repair code stored in the non-volatile memory, and when all the small core startup codes are abnormal, copying all the small core repair codes stored in the non-volatile memory to the small core random access memory to repair the small core startup code.

[0015] Furthermore, after the abnormal part of the small core startup code is repaired, the small core reset startup address is set to the small core random access memory and the small core is controlled to reset. After reset, the repaired small core startup code in the small core random access memory is run to enable the multi-core heterogeneous chip to start normally.

[0016] A multi-core heterogeneous chip startup control system, the multi-core heterogeneous chip startup control system is used to implement the multi-core heterogeneous chip startup control method, the multi-core heterogeneous chip startup control system includes: a non-volatile memory, used to store a large core repair code and a small core repair code, a multi-core heterogeneous chip, the multi-core heterogeneous chip includes a large core, a small core and a large-core interactive bus, the large core and the small core communicate through the large-core interactive bus, wherein the non-volatile memory is externally mounted on the small core.

[0017] Furthermore, the non-volatile memory is Flash, which is mounted on the small core and communicates with the small core through an XIP mechanism.

[0018] Furthermore, the small core includes a small core CPU, a Flash controller, a small core random access memory and a small core bus, wherein the small core CPU, the Flash controller and the small core random access memory all communicate through the small core bus, and the Flash controller communicates with the external Flash through the XIP mechanism.

[0019] Furthermore, the big core includes a big core CPU, a read-only memory, a big core random access memory, a memory controller and a big core bus, wherein the big core CPU, the read-only memory, the big core random access memory and the memory controller all communicate through the big core bus, and the big core bus communicates with the small core bus through the big and small core interactive bus.

[0020] A multi-core heterogeneous chip startup control method described in the present application, when the BROM inside the multi-core heterogeneous chip fails, first allows the small core to read the small core startup code from the external non-volatile memory and complete the startup of the small core, and then the small core copies the large core repair code from the external non-volatile memory to the large core random access memory to assist the large core in completing the startup, which can avoid the risk of failure of the multi-core heterogeneous chip due to BROM design errors. In multi-core heterogeneous chips, the large core circuit is more complex, which makes the startup boot program also complicated and error-prone. Therefore, this application adds a mechanism for the small core to start the large core. When the large core BROM code design error occurs, the roles of the large and small cores responsible for startup are swapped, so that the small core can start and boot the entire system, which has a double insurance effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a flow chart of a multi-core heterogeneous chip startup control method according to an embodiment of the present application.

[0022] Figure 2 This is a structural diagram of a multi-core heterogeneous chip startup control system described in an embodiment of the present application. DETAILED DESCRIPTION

[0023] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0024] It should be understood that when used in this application, the term "comprising" indicates the presence of the described features, integral bodies, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their collections. It should also be understood that the term "and / or" used in this application refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0025] As used in this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0026] In addition, in the description of the present application, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. The reference to "one embodiment" or "some embodiments" described in the specification of the present application means that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in the differences in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0027] The Chinese patent with publication number CN117215823A provides a chip boot code repair method and a boot control system, which can avoid the problem of chip unavailability caused by boot code design defects. At present, robot main control chips generally adopt large and small core heterogeneous CPU design, such as STMicroelectronics' STM32MP157 chip, the large core adopts a dual-core Arm Cortex-A7CPU to run the Linux operating system, and the small core adopts an Arm Cortex-M4 CPU to run the RTOS. However, the above-mentioned Chinese patent does not take into account the applicability of its technical solution in the design of heterogeneous large and small core chips, which needs to be improved.

[0028] In order to solve the above technical problems, the embodiment of the present application provides a multi-core heterogeneous chip startup control method. When the BROM inside the multi-core heterogeneous chip fails, the small core is first allowed to read the small core startup code from the external non-volatile memory and complete the startup of the small core, and then the small core copies the large core repair code from the external non-volatile memory to the large core random access memory to assist the large core in completing the startup, which can avoid the risk of failure of the multi-core heterogeneous chip due to BROM design errors. In a multi-core heterogeneous chip, the large core circuit is relatively complex, which makes the startup boot program also complicated and prone to errors. Therefore, the present application adds a mechanism that the small core can also start the large core. When the large core BROM code design error occurs, the roles of the large and small cores responsible for startup are swapped, so that the small core can start and boot the entire system, which has a double insurance effect.

[0029] like Figure 1 As shown, the multi-core heterogeneous chip startup control method includes the following steps: Step S1, after the multi-core heterogeneous chip is powered on, the large core startup code is run, and then it is detected whether the multi-core heterogeneous chip is started abnormally during the running of the large core startup code. If not, the large core startup code continues to be run until the multi-core heterogeneous chip is started normally. If yes, the process proceeds to step S2; Step S2, the multi-core heterogeneous chip enables the small core to run the small core startup code stored in the non-volatile memory to complete the startup of the small core, and then enters step S3; Step S3, based on the abnormal position of the large core startup code, the multi-core heterogeneous chip copies the large core startup code and / or the large core repair code stored in the non-volatile memory to the large core random access memory through the small core to repair the abnormal part of the large core startup code.

[0030] It should be noted that the boot code (including the big core boot code and the small core boot code) in the embodiments of the present application refers to a section of code stored in the chip's read-only memory (ROM), generally referred to as BootROM (Boot Read-Only Memory) code or BROM code, which stores the most important basic input and output programs of the device, system setting information, self-test programs after power-on, and system self-startup programs. The BROM code is the code that runs first after the chip is powered on. After the BROM code runs successfully, the chip reads the Bootloader from the NAND Flash. After the Bootloader runs successfully, it then reads the FW firmware from the NAND Flash. When the FW firmware runs successfully, the chip starts to work normally. It is not difficult to understand that when there is a problem with the BROM code, the subsequent boot steps cannot be performed. In addition, the BROM code cannot be changed. Once there is a design defect in the BROM code, it may cause the entire chip to be scrapped, resulting in losses.

[0031] As one of the implementation modes, in step S1, the method for detecting whether the multi-core heterogeneous chip starts abnormally during the operation of the large core startup code includes: before the large core startup code runs normally, the watchdog records the time consumed by the current startup once every preset time interval, and then compares it with the first preset startup timeout time, if the time consumed by the current startup is greater than or equal to the first preset startup timeout time, the multi-core heterogeneous chip starts abnormally during the operation of the large core startup code, if the time consumed by the current startup is less than the first preset startup timeout time, the multi-core heterogeneous chip does not start abnormally during the operation of the large core startup code. Using the chip internal watchdog to detect whether the chip starts abnormally has the advantages of reliability, flexibility and easy implementation.

[0032] As one of the implementation modes, in step S2, the non-volatile memory is Flash, and the Flash is externally mounted on the small core, and communicates with the small core through the XIP mechanism. The use of external Flash to store the repair code provides a way to modify the startup code or repair code, and is highly flexible. Among them, the XIP mechanism (executed in place, local execution), the operating system adopts this mechanism, and can directly run directly in the code storage space without copying the kernel or execution code to the memory, which can save available memory and reduce loading time. It should be noted that although the embodiment of the present application has an additional Flash externally mounted, some solutions themselves also need to mount Flash to store information such as the MAC address of the network card. Therefore, the solution described in the embodiment of the present application will not significantly increase the cost. In the chip that has an external Flash, it has the effect of improving the utilization rate of Flash and has a high practical value.

[0033] As one of the implementation modes, in step S3, based on the abnormal position of the large core startup code, the multi-core heterogeneous chip copies the large core startup code and / or the large core repair code stored in the non-volatile memory to the large core random access memory through the small core to repair the abnormal part of the large core startup code. The method includes: based on the abnormal position of the large core startup code, a repair mark is made at the corresponding position of the large core repair code stored in the non-volatile memory, and when the large core startup code is not completely abnormal, the non-abnormal part of the large core startup code and the large core repair code with a repair mark in the non-volatile memory are copied to the large core random access memory to repair the abnormal part of the large core startup code. In the embodiment of the present application, the repair mark is used to mark the part of the large core repair code used to repair the large core startup code, which is convenient for multi-core heterogeneous chip identification. It should be noted that the essence of the large core repair code is the backup of the large core startup code, and the essence of the repair is replacement, that is, the large core repair code is used to replace the abnormal part of the large core startup code. In addition, the large core repair code is stored in the external non-volatile memory. If there is an error in the large core repair code (or a version update is required), it can be modified at any time.

[0034] As one of the implementation modes, in step S3, based on the abnormal position of the large core startup code, the multi-core heterogeneous chip copies the large core startup code and / or the large core repair code stored in the non-volatile memory to the large core random access memory through the small core to repair the abnormal part of the large core startup code. The method includes: based on the abnormal position of the large core startup code, a repair mark is made at the corresponding position of the large core repair code stored in the non-volatile memory, and when the large core startup code is all abnormal, the large core repair code stored in the non-volatile memory is all copied to the large core random access memory to repair the large core startup code. In the embodiment of the present application, since the large core startup code is all abnormal, the large core startup code is replaced with the entire large core repair code to achieve the effect of repairing the large core startup code.

[0035] As one of the implementation methods, after the abnormal part of the large core startup code is repaired, the multi-core heterogeneous chip sets the large core reset startup address to the large core random access memory through the small core and controls the large core to reset. After the reset, the repaired large core startup code in the large core random access memory is run to enable the multi-core heterogeneous chip to start normally. As mentioned above, the BROM code cannot be changed, so the BROM code is repaired in the large core random access memory, and then the code is run to guide the system to start. Among them, the type of large core random access memory includes but is not limited to SRAM or DRAM.

[0036] In one embodiment, it is assumed that the size of the large core startup code is 64K. After the chip is powered on, the necessary modules are initialized first. If the large core startup code successfully runs the first 60K, and the last 4K code has a problem and cannot run, resulting in a startup timeout, indicating that the abnormal position of the large core startup code is at the last 4K code, then the small core makes a repair mark at the last 4K code of the large core repair code in Flash, such as marking a devil number, and then copies the last 4K code to the large core random access memory. At the same time, the first 60K of the large core startup code is also copied to the large core random access memory, and is merged with the 4K code with the repair mark into a complete large core startup code, so that the large core startup code repair is completed. If the large core startup code cannot be run, indicating that the entire large core startup code is abnormal, the entire 64K large core repair code is marked as a repair, and then copied to the large core random access memory, and the large core startup code is replaced as a whole, which has the effect of repairing the large core startup code.

[0037] As one of the implementation modes, in the step S1, the method of continuing to run the big core startup code until the multi-core heterogeneous chip starts normally includes: after the big core startup code runs normally, the multi-core heterogeneous chip copies the small core startup code to the small core random access memory through the big core to run, if the multi-core heterogeneous chip does not start abnormally during the running of the small core startup code, then detect whether the small core is externally mounted with a non-volatile memory, if not, then make the small core enter a state of waiting for reset, if so, then make the small core run the preset code stored in the non-volatile memory through the XIP mechanism, and then enter a low power consumption mode. In the normal startup process, the big core should first run the BROM program to start the system, after the big core is started, the big core is responsible for copying the small core startup code to the small core random access memory and resetting the small core to make the small core run, if there is no abnormality, the multi-core heterogeneous chip finally enters a low power consumption mode, such as a WIFI state, and then waits for new commands.

[0038] As one of the implementation modes, after the multi-core heterogeneous chip copies the small core startup code to the small core random access memory through the large core for execution, if the multi-core heterogeneous chip starts abnormally during the execution of the small core startup code, based on the abnormal position of the small core startup code, the multi-core heterogeneous chip causes the small core to copy the small core startup code and / or the small core repair code stored in the non-volatile memory to the small core random access memory to repair the abnormal part of the small core startup code. In a multi-core heterogeneous chip, the small core circuit is relatively simple compared to the complex large core circuit, but errors in the boot program may also occur. In the embodiment of the present application, when the small core starts abnormally, the small core repair code stored in the non-volatile memory is used to repair the small core startup code, thereby avoiding the problem of chip unavailability caused by design defects in the small core startup code and reducing the risk of chip investment.

[0039] As one of the implementation modes, the method for detecting whether the multi-core heterogeneous chip starts abnormally during the running of the small core startup code includes: before the small core startup code runs normally, the watchdog records the time consumed by the current startup at a preset time interval, and then compares it with the second preset startup timeout time, if the time consumed by the current startup is greater than or equal to the second preset startup timeout time, the multi-core heterogeneous chip starts abnormally during the running of the small core startup code, if the time consumed by the current startup is less than the second preset startup timeout time, the multi-core heterogeneous chip does not start abnormally during the running of the small core startup code. Using the chip internal watchdog to detect whether the chip starts abnormally has the advantages of reliability, flexibility and easy implementation.

[0040] As one of the implementation methods, based on the abnormal position of the small core startup code, the multi-core heterogeneous chip enables the small core to copy the small core startup code and / or the small core repair code stored in the non-volatile memory to the small core random access memory to repair the abnormal part of the small core startup code. The method includes: based on the abnormal position of the small core startup code, a repair mark is made at the corresponding position of the small core repair code stored in the non-volatile memory, and when the small core startup code is not completely abnormal, the non-abnormal part of the small core startup code and the small core repair code with a repair mark in the non-volatile memory are copied to the small core random access memory to repair the abnormal part of the small core startup code. In an embodiment of the present application, the repair mark is used to mark the part of the small core repair code used to repair the small core startup code, which is convenient for multi-core heterogeneous chip identification. It should be noted that the essence of the small core repair code is a backup of the small core startup code, and the contents of the two are consistent, and the essence of the repair is replacement, that is, the small core repair code is used to replace the abnormal part of the small core startup code.

[0041] As one of the implementation methods, based on the abnormal position of the small core startup code, the multi-core heterogeneous chip enables the small core to copy the small core startup code and / or the small core repair code stored in the non-volatile memory to the small core random access memory to repair the abnormal part of the small core startup code. The method includes: based on the abnormal position of the small core startup code, a repair mark is made at the corresponding position of the small core repair code stored in the non-volatile memory, and when the small core startup code is all abnormal, the small core repair code stored in the non-volatile memory is all copied to the small core random access memory to repair the small core startup code. In the embodiment of the present application, since the small core startup code is all abnormal, the small core startup code is replaced with the entire small core repair code to achieve the effect of repairing the small core startup code.

[0042] As one of the implementation methods, after the abnormal part of the small core startup code is repaired, the small core reset startup address is set to the small core random access memory and the small core is controlled to reset. After the reset, the repaired small core startup code in the small core random access memory is run to enable the multi-core heterogeneous chip to start normally. As mentioned above, the BROM code cannot be changed, so the BROM code is repaired in the small core random access memory, and then the code is run to guide the system to start. Among them, the type of small core random access memory includes but is not limited to SRAM or DRAM.

[0043] like Figure 2As shown, an embodiment of the present application provides a multi-core heterogeneous chip startup control system, which is used to implement the multi-core heterogeneous chip startup control method, and the multi-core heterogeneous chip startup control system includes: a non-volatile memory for storing a large core repair code and a small core repair code, a multi-core heterogeneous chip, the multi-core heterogeneous chip includes a large core, a small core and a large-core and small-core interactive bus, the large core and the small core communicate through the large-core and small-core interactive bus, wherein the non-volatile memory is externally mounted on the small core.

[0044] As one implementation method, the non-volatile memory is Flash, which is externally mounted on the small core and communicates with the small core through the XIP mechanism. Using the external Flash to store the repair code provides a way to modify the startup code or the repair code, which is highly flexible.

[0045] As one implementation mode, the small core includes a small core CPU, a Flash controller, a small core random access memory (small core SRAM) and a small core bus, wherein the small core CPU, the Flash controller and the small core random access memory all communicate through the small core bus, and the Flash controller communicates with the external Flash through the XIP mechanism.

[0046] As one of the implementation modes, the big core includes a big core CPU, a read-only memory (BROM), a big core random access memory (big core SRAM), a memory controller (DDR controller) and a big core bus, wherein the big core CPU, the read-only memory, the big core random access memory and the memory controller all communicate through the big core bus, and the big core bus communicates with the small core bus through a big and small core interactive bus.

[0047] A multi-core heterogeneous chip startup control system described in an embodiment of the present application, when the BROM inside the multi-core heterogeneous chip fails, first allows the small core to read the small core startup code from the external non-volatile memory and complete the startup of the small core, and then the small core copies the large core repair code from the external non-volatile memory to the large core random access memory to assist the large core in completing the startup, which can avoid the risk of failure of the multi-core heterogeneous chip due to BROM design errors. In a multi-core heterogeneous chip, the large core circuit is relatively complex, which makes the startup boot program also complicated and prone to errors. Therefore, the embodiment of the present application adds a mechanism that the small core can also start the large core. When the large core BROM code design error occurs, the roles of the large and small cores responsible for startup are swapped, allowing the small core to start and boot the entire system, which has a double insurance effect.

[0048] It will be understood by those skilled in the art that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the references to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory ROM, programmable memory PROM, electrically programmable memory DPROM, electrically erasable programmable memory DDPROM or flash memory. Volatile memory may include random access memory RAM or external cache memory.

[0049] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0050] The above embodiments only express several embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application.

Claims

1. A multi-core heterogeneous chip startup control method, characterized in that: The multi-core heterogeneous chip startup control method comprises the following steps: Step S1, after the multi-core heterogeneous chip is powered on, the large core startup code is run, and then it is detected whether the multi-core heterogeneous chip is started abnormally during the running of the large core startup code. If not, the large core startup code continues to be run until the multi-core heterogeneous chip is started normally. If yes, the process proceeds to step S2; Step S2, the multi-core heterogeneous chip enables the small core to run the small core startup code stored in the non-volatile memory to complete the startup of the small core, and then enters step S3; Step S3, based on the abnormal position of the big core startup code, the multi-core heterogeneous chip copies the big core startup code and / or the big core repair code stored in the non-volatile memory to the big core random access memory through the small core to repair the abnormal part of the big core startup code, and then starts the multi-core heterogeneous chip normally based on the repaired big core startup code.

2. A multi-core heterogeneous chip startup control method according to claim 1, characterized in that: In step S1, the method for detecting whether the multi-core heterogeneous chip is abnormally started during the execution of the large core startup code includes: Before the big core startup code runs normally, the watchdog records the time consumed by the current startup at a preset time interval, and then compares it with the first preset startup timeout time. If the time consumed by the current startup is greater than or equal to the first preset startup timeout time, the multi-core heterogeneous chip startup is abnormal during the running of the big core startup code. If the time consumed by the current startup is less than the first preset startup timeout time, the multi-core heterogeneous chip does not start abnormally during the running of the big core startup code.

3. The multi-core heterogeneous chip startup control method according to claim 1, characterized in that: In step S2, the non-volatile memory is Flash, which is mounted on the small core and communicates with the small core through the XIP mechanism.

4. The method for controlling startup of a multi-core heterogeneous chip according to claim 1, characterized in that: In step S3, based on the abnormal position of the large core startup code, the multi-core heterogeneous chip copies the large core startup code and / or the large core repair code stored in the non-volatile memory to the large core random access memory through the small core to repair the abnormal part of the large core startup code, including: Based on the abnormal position of the large core startup code, a repair mark is made at the corresponding position of the large core repair code stored in the non-volatile memory. When the large core startup code is not completely abnormal, the non-abnormal part of the large core startup code and the large core repair code with the repair mark in the non-volatile memory are copied to the large core random access memory to repair the abnormal part of the large core startup code.

5. The method for controlling startup of a multi-core heterogeneous chip according to claim 1, characterized in that: In step S3, based on the abnormal position of the large core startup code, the multi-core heterogeneous chip copies the large core startup code and / or the large core repair code stored in the non-volatile memory to the large core random access memory through the small core to repair the abnormal part of the large core startup code, including: Based on the abnormal position of the large core startup code, a repair mark is made at the corresponding position of the large core repair code stored in the non-volatile memory. When all the large core startup codes are abnormal, all the large core repair codes stored in the non-volatile memory are copied to the large core random access memory to repair the large core startup code.

6. A multi-core heterogeneous chip startup control method according to claim 4 or 5, characterized in that: After the abnormal part of the big core startup code is repaired, the multi-core heterogeneous chip sets the big core reset startup address to the big core random access memory through the small core and controls the big core to reset. After reset, the repaired big core startup code in the big core random access memory is run to enable the multi-core heterogeneous chip to start normally.

7. The method for controlling startup of a multi-core heterogeneous chip according to claim 3, characterized in that: In step S1, the method of continuing to run the large core startup code until the multi-core heterogeneous chip starts normally includes: After the big core startup code runs normally, the multi-core heterogeneous chip copies the small core startup code to the small core random access memory through the big core for execution. If there is no startup abnormality in the multi-core heterogeneous chip during the execution of the small core startup code, it detects whether the small core has an external non-volatile memory. If not, the small core is put into a state of waiting for reset. If so, the small core runs the preset code stored in the non-volatile memory through the XIP mechanism, and then enters a low power consumption mode.

8. The method for controlling startup of a multi-core heterogeneous chip according to claim 7, characterized in that: After the multi-core heterogeneous chip copies the small core startup code to the small core random access memory through the big core and runs it, if the multi-core heterogeneous chip starts abnormally during the running of the small core startup code, then based on the abnormal position of the small core startup code, the multi-core heterogeneous chip enables the small core to copy the small core startup code and / or the small core repair code stored in the non-volatile memory to the small core random access memory to repair the abnormal part of the small core startup code.

9. A multi-core heterogeneous chip startup control method according to claim 8, characterized in that: The method for detecting whether a multi-core heterogeneous chip is abnormally started during the execution of a small core startup code includes: Before the small core startup code runs normally, the watchdog records the time consumed by the current startup at a preset time interval, and then compares it with the second preset startup timeout time. If the time consumed by the current startup is greater than or equal to the second preset startup timeout time, the multi-core heterogeneous chip startup is abnormal during the running of the small core startup code. If the time consumed by the current startup is less than the second preset startup timeout time, the multi-core heterogeneous chip does not start abnormally during the running of the small core startup code.

10. The method for controlling startup of a multi-core heterogeneous chip according to claim 8, characterized in that: Based on the abnormal position of the small core startup code, the method in which the multi-core heterogeneous chip enables the small core to copy the small core startup code and / or the small core repair code stored in the non-volatile memory to the small core random access memory to repair the abnormal part of the small core startup code includes: Based on the abnormal position of the small core startup code, a repair mark is made at the corresponding position of the small core repair code stored in the non-volatile memory. When the small core startup code is not completely abnormal, the non-abnormal part of the small core startup code and the small core repair code with the repair mark in the non-volatile memory are copied to the small core random access memory to repair the abnormal part of the small core startup code.

11. The method for controlling startup of a multi-core heterogeneous chip according to claim 8, characterized in that: Based on the abnormal position of the small core startup code, the method in which the multi-core heterogeneous chip enables the small core to copy the small core startup code and / or the small core repair code stored in the non-volatile memory to the small core random access memory to repair the abnormal part of the small core startup code includes: Based on the abnormal position of the small core startup code, a repair mark is made at the corresponding position of the small core repair code stored in the non-volatile memory. When all the small core startup codes are abnormal, all the small core repair codes stored in the non-volatile memory are copied to the small core random access memory to repair the small core startup code.

12. A multi-core heterogeneous chip startup control method according to claim 10 or 11, characterized in that: After the abnormal part of the small core startup code is repaired, the small core reset startup address is set to the small core random access memory and the small core is controlled to reset. After reset, the repaired small core startup code in the small core random access memory is run to enable the multi-core heterogeneous chip to start normally.

13. A multi-core heterogeneous chip startup control system, characterized in that: The multi-core heterogeneous chip startup control system is used to implement the multi-core heterogeneous chip startup control method according to any one of claims 1 to 12, and the multi-core heterogeneous chip startup control system includes: Non-volatile memory, used to store large core repair code and small core repair code, A multi-core heterogeneous chip includes a large core, a small core and a large-core-large-core interactive bus, wherein the large core and the small core communicate with each other via the large-core-large-core interactive bus, wherein a non-volatile memory is externally mounted on the small core.

14. A multi-core heterogeneous chip startup control system according to claim 13, characterized in that: The non-volatile memory is Flash, which is externally mounted on the small core and communicates with the small core through the XIP mechanism.

15. The multi-core heterogeneous chip startup control system according to claim 14, characterized in that: The small core includes a small core CPU, a Flash controller, a small core random access memory and a small core bus, wherein: The small core CPU, Flash controller and small core random access memory all communicate through the small core bus. The Flash controller communicates with the external Flash through the XIP mechanism.

16. A multi-core heterogeneous chip startup control system according to claim 15, characterized in that: The large core includes a large core CPU, a read-only memory, a large core random access memory, a memory controller and a large core bus, wherein: The big-core CPU, read-only memory, big-core random access memory, and memory controller all communicate through the big-core bus. The big core bus communicates with the small core bus through the big and small core interaction bus.

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