Cable connection correctness detection method and server system

Abstract

The invention provides a cable connection correctness detection method and a server system, and the method comprises the steps: distributing an Nth characteristic signal to an Nth first connector through a data processing assembly, and transmitting the Nth characteristic signal to an Nth second connector through a cable of the Nth first connector, the N characteristic signals are obtained by converting N-bit data, and the Nth characteristic signal is used for representing the value of the Nth-bit data; acquiring a read-back signal fed back to the programmable logic device by the board card to be detected based on all the characteristic signals, and converting the read-back signal into read-back data; and determining whether each cable is correctly connected or not based on the value of each bit of data and the value of N bits of data in the read-back data. According to the technical scheme, line sequence detection of multiple board cards can be achieved only through one CPLD, participation of a substrate management controller is not needed, and excessive occupation of base plate management controller pin resources is avoided.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a method for detecting correctness of cable connection and a server system. Background Art

[0002] With the rapid development of server products, there are many different cables in the whole system that connect different or the same boards to achieve signal transmission needs. It is very important to accurately judge whether the cable connection position is correct in the current configuration, whether the cable contact is in place, and distinguish different configurations according to the cable.

[0003] In the prior art, when a board is plugged into a server mainboard via a cable, a baseboard management controller in the server mainboard is mainly used to access the complex programmable logic devices of the server mainboard and the backplane board via a bus protocol to determine whether the current cable is correctly inserted.

[0004] However, this method may easily lead to excessive use of the pin resources of the baseboard management controller, since the number of available communication pins of the baseboard management controller is limited in the whole product. Summary of the invention

[0005] The present application provides a method and a server system for detecting the correctness of cable connection, which are used to solve the problem that the existing cable detection occupies too many pin resources of the baseboard management controller.

[0006] In a first aspect, an embodiment of the present application provides a method for detecting the correctness of a cable connection, which is applied to a switch board, wherein the switch board is provided with a data processing component and M first connectors, each first connector is connected to the data processing component through a signal line, each first connector is connected to a second connector of a board to be detected through a cable, and the board to be detected is connected to the data processing component through an integrated circuit bus, M is a positive integer, and the method comprises:

[0007] The Nth characteristic signal is distributed to the Nth first connector through the data processing component, and the Nth characteristic signal is sent to the Nth second connector through the cable of the Nth first connector, the N characteristic signals are obtained by converting N bits of data, the Nth characteristic signal is used to characterize the value of the Nth bit of data, and N is a positive integer less than or equal to M;

[0008] Acquire a readback signal fed back to the data processing component by the board to be detected based on all characteristic signals, and convert the readback signal into readback data;

[0009] Based on the value of each bit of data and the value of the N bits of data in the read-back data, it is determined whether each cable is connected correctly.

[0010] In a possible design of the first aspect, the method further includes:

[0011] Acquire the number of second connectors connected to the chip provided on the board to be detected;

[0012] Determining a total number of the cables based on the number of the second connectors;

[0013] The total number is taken as the value of N.

[0014] In another possible design of the first aspect, determining whether each cable is correctly connected based on a value of each bit of data and a value of N bits of data in the readback data includes:

[0015] Determine whether the value of the Nth bit of data is the same as the value of the Nth bit of data in the read-back data;

[0016] If they are the same, make sure the Nth cable is connected correctly;

[0017] If they are different, it is determined that the Nth cable is incorrectly connected.

[0018] In another possible design of the first aspect, the board to be detected is at least one of an expansion card, an expansion backplane, and a backplane.

[0019] In another possible design of the first aspect, the board to be detected includes at least two identical first expansion cards and second expansion cards;

[0020] The Kth second connector on the first expansion card is connected to the Kth first connector via the Kth cable, and the first expansion card is connected to the data processing component via an integrated circuit bus;

[0021] The Lth second connector on the second expansion card is connected to the K+Lth first connector via the K+Lth cable, and the second expansion card is connected to the data processing component via an integrated circuit bus. K and L are both positive integers, and the sum of K and L is less than or equal to N.

[0022] In another possible design of the first aspect, the method further includes:

[0023] Converting N bits of data into K pull-up signals and L pull-down signals, the Kth pull-up signal is used to represent the value of the Kth bit of data, and the Lth pull-down signal is used to represent the value of the K+Lth bit of data;

[0024] The values ​​of K-bit data represented by the K pull-up signals and the values ​​of L-bit data represented by the L pull-down signals are configured to be different.

[0025] In another possible design of the first aspect, the board to be detected further includes an extended backplane and at least two identical first backplanes and second backplanes;

[0026] The Nth second connector of the expansion backplane is connected to the Nth first connector through the Nth cable;

[0027] The Xth second connector of the first backplane is connected to the N+Xth second connector of the extension backplane through the Xth cable;

[0028] The Yth second connector of the second backplane is connected to the N+Yth second connector of the extension backplane through the Yth cable, the extension backplane is connected to the data processing component through at least one integrated circuit bus, the first backplane and the second backplane are connected to the data processing component through at least one integrated circuit bus, and X and Y are positive integers.

[0029] In another possible design of the first aspect, the method further includes:

[0030] Converting the N-bit data into E first signals and F second signals, the E-th first signal is used to represent the value of the E-th bit of data, and the F-th second signal is used to represent the value of the E+F-th bit of data;

[0031] The values ​​of the E-bit data represented by the E first signals and the values ​​of the E+F-bit data represented by the F pull-down signals are configured to be different.

[0032] In another possible design of the first aspect, the data processing component includes a complex programmable logic device and a chip, the complex programmable logic device is connected to the chip via a first integrated circuit bus, the complex programmable logic device is connected to the board to be tested via a second integrated circuit bus, and the chip is connected to the first connector via a signal line.

[0033] In a second aspect, an embodiment of the present application provides a server system, comprising: a server mainboard and a board to be detected plugged into the server mainboard, the server mainboard being configured to execute the method described above to detect whether the connection between the board to be detected and the server mainboard is correct.

[0034] The cable connection correctness detection method and server system provided in the embodiments of the present application can realize line sequence detection of multiple boards with only one CPLD, without the involvement of the baseboard management controller, thus avoiding excessive occupation of baseboard management controller pin resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] Figure 1 This is a schematic diagram of the hardware structure for current cable connection correctness detection;

[0037] Figure 2 A schematic diagram of the hardware structure of the server system provided in the embodiment of the present application;

[0038] Figure 3 A schematic diagram of the system hardware structure of the cable detection method provided in an embodiment of the present application;

[0039] Figure 4 A schematic diagram of a process for detecting the correctness of a cable connection provided in an embodiment of the present application;

[0040] Figure 5 A schematic diagram of the flow of a cable detection method provided in an embodiment of the present application.

[0041] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0043] Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application. In addition, although the disclosure in this application is introduced according to one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete technical solution separately.

[0044] It should be understood that the terms "first", "second", "third", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, for example, they can be implemented according to an order other than those given in the diagrams or descriptions of the embodiments of this application.

[0045] In addition, the terms "include" and "have" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such products or devices.

[0046] The term "module" as used in this application refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that is capable of performing the functions associated with that element.

[0047] Below, some terms in the embodiments of the present application are explained to facilitate understanding by those skilled in the art:

[0048] Switch board (SW board) is a hardware component used for data exchange in network equipment.

[0049] Complex Programmable Logic Device (CPLD): Used to implement complex digital logic circuits.

[0050] High-speed connector, a physical connection device used for high-speed data transmission.

[0051] Pulse width modulation (PWM) is a pulse signal used to control signal strength by changing the duration of the pulse.

[0052] Backplane (BP), the backplane of the server is a key component inside the server. It acts as a bridge for communication between the components inside the server and is responsible for data transmission and connecting various hardware components, such as processors, memory, hard drives, expansion cards, etc.

[0053] Expansion card (RISER card) is used to provide additional slots or interfaces.

[0054] Short-circuit loopback directly connects the signal sending end and receiving end to form a loop for testing or signal feedback.

[0055] Baseboard Management Controller (BMC) is a microcontroller used to monitor and manage the status of server hardware.

[0056] Inter-Integrated Circuit (I2C) is a serial communication protocol used for data transmission between devices.

[0057] Pins are used to establish physical connections with other electronic components.

[0058] Detecet_ID, referred to as DET_ID signal, is the signal of the signal line in the cable.

[0059] With the rapid development of server AI products, there are many different cables in the whole system that connect different or the same boards to realize signal transmission. Therefore, it is very important to accurately judge whether the cable connection position is correct in the current configuration, whether the cable contact is in place, and distinguish different configurations according to the cable.

[0060] Among them, server AI products refer to products that use artificial intelligence technology to enhance server performance. These products may include functions such as using AI algorithms for data processing, optimizing resource allocation, or improving security. A complete system refers to a complete computer system, including hardware and software, that can run independently and perform tasks. In the server field, a complete system usually refers to a complete server hardware configuration, including processors, memory, storage devices, etc.

[0061] In addition, cables are physical media used to connect different hardware components. They can transmit electrical signals or data signals. There are many types of cables, including but not limited to power cables, data cables, network cables, etc. A board is an expansion card installed on the computer motherboard to increase or enhance the computer's functions. Common boards include graphics cards, sound cards, network cards, etc.

[0062] In addition, whether the contact is in place usually refers to whether the connection point between the cable and the board or other hardware components is correctly inserted and secure to ensure that the signal can be transmitted smoothly.

[0063] For example, Figure 1 The following is a schematic diagram of the hardware structure for current cable connection correctness detection. Figure 1 As shown, there are four detection forms as follows:

[0064] (1) The CPLD on the SW board has two IO to high-speed connectors, one for sending PWM pulse signals and one for receiving PWM wave returns, which means that the high-speed connector has a cable connection.

[0065] (2) For boards with CPLD, such as backplanes, the cable connection status is determined by the PWM pulse signal between the two CPLDs.

[0066] (3) For boards such as RISER, these two IOs are directly short-circuited and looped back.

[0067] (4) The BMC is required to access the CPLD of the SW board and the backplane through the I2C protocol to obtain whether the current cables are inserted and whether some cables are correct.

[0068] At present, there are several main problems: ① For boards without CPLD, the system cannot confirm the connection method of the high-speed cable. If cable 3 and cable 4 in the figure above are inserted in the wrong position during assembly, the system cannot identify the problem, which will cause the device to be unable to identify. ② Different duty cycles are required for different high-speed connectors. At the same time, for the reliability of the system, the larger the duty cycle step, the better. When there are many high-speed connectors in the system, the duty cycle is not enough, and this method cannot be used to detect the cable. ③ The frequency of the sent PWM wave is fast, which will cause crosstalk to other signals, and the crosstalk exists for a long time. ④ The sending of PWM pulses and pulse detection occupies more CPLD logic and pin resources. ⑤ The number of I2Cs available in the BMC chip of the current whole machine product is limited. This solution needs to occupy the BMC's I2C pins, wasting BMC I2C resources. ⑥ The BMC and CPLD dual logic chips participate in cable detection, wasting resources.

[0069] In response to the above problems, this application provides a cable connection correctness detection solution, which can effectively solve the problems of the existing cable detection method that cannot identify the wrong cable insertion, the same board cannot be distinguished, and the signal crosstalk is large. In addition, by using the fewer pins of the CPLD single logic chip to solve the line sequence detection of multiple cables, there is no need for BMC logic participation, and the occupation of BMC I2C pins is avoided.

[0070] For example, Figure 2 A schematic diagram of the hardware structure of the server system provided in the embodiment of the present application is shown in FIG. Figure 2 As shown, the server system includes a switch board, an expansion backplane, two backplanes and two expansion cards. The expansion backplane and the expansion card are connected to the switch board through cables, and the backplane is connected to the expansion backplane through cables, and finally realizes communication with the switch board. In addition, the expansion backplane, the backplane and the expansion card can also communicate with the switch board through another I2C protocol.

[0071] The technical solution of the present application is described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0072] Figure 3 A schematic diagram of the system hardware structure of the cable detection method provided in the embodiment of the present application is shown in FIG. Figure 3As shown, the switch board SW includes a data processing component and M first connectors. Each first connector is connected to the data processing component through a signal line, each first connector is connected to the second connector of the board to be detected through a cable, and the board to be detected is connected to the data processing component through an integrated circuit bus, and M is a positive integer. Exemplarily, the value of M can be 32, which corresponds to Figure 3 SW in connector 1 to connector 32.

[0073] The data processing component includes a complex programmable logic device CPLD and a chip PCA9555. The complex programmable logic device CPLD is connected to the chip PCA9555 through a first integrated circuit bus IIC1 / IIC2, and the complex programmable logic device CPLD is connected to the chip PCA9555 through another second integrated circuit bus (e.g. Figure 3 IIC3, IIC4, IIC5, IIC6, IIC7) in the chip are connected to the board to be detected, and the chip PCA9555 is connected to each first connector through signal lines DET_ID1 to DET_ID32.

[0074] In this embodiment, referring to the above Figure 3 On the SW board, the CPLD uses 14 PINs to connect 7 IIC signals to implement cable detection for level 2 controller-less boards and the same board used in different positions in the chassis (including a total of 32 cables).

[0075] Among them, IIC1 and IIC2 are given to the two PCA9555 expansion chips on the SW board to write DET_ID1~DET_ID8, DET_ID17~DET_ID32 signals. IIC3 is given to the PCA9555 expansion chip on the RISER BP to read back the DET_ID1~DET_ID8 signals and write the DET_ID9~DET_ID16 signals. IIC4 is given to the PCA9555 expansion chip on the first BP1 to read back the DET_ID1~DET_ID4 signals written on the first BP1. IIC5 is given to the PCA9555 expansion chip on the second BP1 to read back the DET_ID1~DET_ID4 signals written on the second BP1. IIC6 and IIC7 are given to two identical boards RISER1 respectively, to read back the DET_ID1~DET_ID8 signals on RISER1;

[0076] In this embodiment, the types of connectors and cables are not limited. The PCA9555 expansion chip can be changed to other chips with expansion functions, such as TCA9555. This expansion function can also be achieved by using chips such as 74H138C decoder to convert IIC signals into three ordinary GPIO signals.

[0077] In this embodiment, Figure 4 A schematic diagram of a process for detecting the correctness of a cable connection provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, it mainly includes the following steps:

[0078] Step S410: distribute the Nth characteristic signal to the Nth first connector through the data processing component, and send the Nth characteristic signal to the Nth second connector through the cable of the Nth first connector, the N characteristic signals are obtained by converting the N-bit data, the Nth characteristic signal is used to characterize the value of the N-bit data, and N is a positive integer less than or equal to M;

[0079] Step S420, obtaining a readback signal fed back to the data processing component by the board to be detected based on all characteristic signals, and converting the readback signal into readback data;

[0080] Step S430: Determine whether each cable is connected correctly based on the value of each bit of data and the value of the N bits of data in the read-back data.

[0081] In this embodiment, the above Figure 3 For example, the main process of cable connection correctness detection is divided into the following steps:

[0082] 1. The CPLD on the SW board sends I2C data to the chip on the board to be tested. For example Figure 3 The PCA9555 chip of RISER BP and the PCA9555 chip of RISER1.

[0083] 2. The PCA9555 chip of RISER BP and the PCA9555 chip of RISER1 convert the data into the actual CABLE ID signal;

[0084] 3. The actual CABLE ID signal is transmitted via the second integrated circuit bus (e.g. Figure 3 IIC3, IIC4, IIC5, IIC6, IIC7) in the SW are returned to the SW CPLD in the SW for reception and converted into received I2C data (i.e. read-back data);

[0085] 4. The PCA9555 chip on the SW board sends the original I2C data (i.e. the original N is data) back to the SW CPLD for reception;

[0086] 5. Compare the original I2C data sent by CPLD with the received I2C data to see if they are consistent;

[0087] 6. If they match, the SW board and RISER BP / 2 RISER1 cables are installed properly and connected correctly;

[0088] 7. If they are not consistent, the SW board and RISER BP / 2 RISER1 cables are connected incorrectly. Reconnect them and perform steps 1-5 again.

[0089] In this embodiment, the value of N can be flexibly configured according to actual needs. In some implementations, the total number of corresponding cables can be determined based on the number of second connectors connected to the chips set on the board to be detected, and then the total number of cables is used as the value of N.

[0090] For example, continue to refer to the above Figure 3 , for example, if the board to be detected is RISER BP, the chip it is equipped with is PCA9555 chip, and the chip of RISER BP corresponds to 8-way cable, then the value of N is 8. If the board to be detected is RISER1 or RISER2, the chip it is equipped with is PCA9555 chip, and the chips of RISER1 and RISER2 correspond to 8-way cable, then the value of N is 8. If the board to be detected is BP1 and BP2, the chip it is equipped with is PCA9555 chip, and the chips of BP1 and BP2 correspond to 4-way cable, then the value of N is 8.

[0091] In addition, in some real-time methods, it is possible to detect whether each cable is connected correctly by comparing each bit by bit. Specifically, it is possible to detect whether the value of the Nth bit of data is the same as the value of the Nth bit of data in the readback data; if they are the same, it is determined that the Nth cable is connected correctly; if they are not the same, it is determined that the Nth cable is connected incorrectly.

[0092] In this embodiment, Figure 3 Take the RISER BP in the example of the board to be tested, the chip in the SW is connected to the RISER BP through the first connector (eg Figure 3 Connectors 1-8 in SW, connectors 17-32 in SW) and a second connector in the board (e.g. Figure 3 The first connector and the second connector are connected one by one, and the first connector and the second connector are connected by a cable (for example Figure 3 CABLE1 to CABLE8 in the display).

[0093] Among them, the value of N is 8, then the original I2C data received by the chip in the SW board is 8-bit data, and it is divided into 8 characteristic signals. Among them, assuming that the 8-bit data is 10000000, then the value represented by the 8th characteristic signal is 1, and the values ​​represented by the 1st to 7th characteristic signals are all 0.

[0094] Continue to refer Figure 3There are 8 cables to transmit these 8 characteristic signals. If one cable is not connected correctly, the characteristic signal may not be transmitted to RISER BP. For example, if CABLE1 is not connected properly, then connector 1 in SW and connector 1 in RISER BP may not communicate, and the eighth characteristic signal will not be received by RISER BP. In this way, the readback data returned by RISER BP to SW may be "00000000". By comparing the original N-bit data "10000000" and the readback data "00000000", it is found that the value of the 8th bit data is different. In this way, it can be determined that CABLE1 is connected incorrectly.

[0095] In actual situations, the value of the original N-bit data can be freely configured, for example, "11111111" or "11110000". By configuring different values, it can be verified whether each cable is connected correctly.

[0096] The embodiments of the present application effectively solve the problems that the existing cable detection methods cannot identify the wrong cable insertion, the same boards cannot be distinguished, and the signal crosstalk is large. It supports the line sequence detection of the 2-level controllerless board, and does not require the participation of the BMC. The line sequence detection of multiple boards can be realized by only the CPLD of one of the boards, avoiding the occupation of BMC pin resources. In addition, since the detection method does not use PWM, the crosstalk problem caused by PWM is also avoided.

[0097] The cable connection correctness detection process is described in detail below through some embodiments.

[0098] In some embodiments, the boards to be detected are at least two identical first expansion cards (i.e. Figure 3 The first RISER1 in the Figure 3 Taking another RISER1 in FIG. 1 as an example, the Kth second connector on the first expansion card is connected to the Kth first connector via the Kth cable, and the first expansion card is connected to the data processing component via the integrated circuit bus. The Lth second connector on the second expansion card is connected to the K+Lth first connector via the K+Lth cable, and the second expansion card is connected to the data processing component via the integrated circuit bus. Wherein, K and L are both positive integers, and the sum of K and L is less than or equal to N.

[0099] In this embodiment, continue to refer to the above Figure 3 The expansion card on the left side of the whole machine is called the first expansion card. There are 8 second connectors on the first expansion card (i.e. connectors 1-8 on RISE1). The 8 second connectors are connected to the first connectors on the SW board (i.e. connectors 17-24) one by one through cables, so there are a total of 8 cables (i.e. CABLE17-CABLE24).

[0100] In addition, the expansion card located on the right side of the whole machine is called the second expansion card. The second expansion card also has 8 second connectors (i.e., connectors 1-8 on RISE1). The 8 second connectors are connected to the first connectors (i.e., connectors 25-32) on the SW board one by one through cables, so there are a total of 8 cables (i.e., CABLE25-CABLE32).

[0101] When RISER1 is used in different positions of the whole machine, the DET_ID signal on the first connector in the SW can be divided into a pull-up signal and a pull-down signal by default to distinguish the positions of the two expansion cards, as shown above. Figure 3 The DET_ID of CABLE17 to CABLE25 is a pull-up signal by default, and the DET_ID of CABLE26 to CABLE32 is a pull-down signal by default; this allows the system to distinguish whether the two same RISER1s are on the left or right side of the chassis.

[0102] Further, in some embodiments, when the board to be detected is at least two identical first expansion cards (i.e. Figure 3 The first RISER1 in the Figure 3 Another RISER1 in the chassis), the value of each bit of data needs to be configured to be different as much as possible to distinguish whether the two same expansion cards are on the left or right side of the chassis. That is, when N bits of data are converted into K pull-up signals and L pull-down signals, since the Kth pull-up signal is used to represent the value of the Kth bit of data, and the Lth pull-down signal is used to represent the value of the K+Lth bit of data, the value of the K-bit data represented by the K pull-up signals and the value of the L-bit data represented by the L pull-down signals can be configured to be different.

[0103] Specifically, the above Figure 3 For example, the values ​​of K and L are both 8, the DET_ID of CABLE17 to CABLE24 defaults to a pull-up signal, and the DET_ID of CABLE25 to CABLE32 defaults to a pull-down signal. The value represented by the pull-up signal may be "00001111", and the value represented by the pull-down signal may be "11111000".

[0104] For example, continue to refer to the above Figure 3, CPLD sends I2C data (corresponding to DET_ID17-24, DET_ID25-32) through IIC2, and sends it to two identical RISER1 PCA9555 chips through CABLE17-24 and CABLE25-32 cables respectively; RISER1 PCA9555 chip converts data into DET_ID17-24 and DET_ID25-32 readback signals; DET_ID17-24 and DET_ID25-32 readback signals are returned to SW chip through IIC6 and IIC7, and converted into I2C data and sent back to SW CPLD for reception; through the returned data and the sent data, determine whether the position of the two identical expansion cards RISER1 is on the right or on the left. Therefore, the position of the two identical expansion cards can be determined by setting the characteristic signal with a specific value.

[0105] In addition to realizing line sequence detection, the embodiments of the present application can also perform position detection. That is, when there are multiple identical expansion cards, if these expansion cards are located in different positions in the chassis, the insertion positions of the identical expansion cards can be distinguished by configuring characteristic signals with specific values. This can solve the problem of disk sequence confusion caused by the inability to distinguish the insertion positions when expansion cards are multiplexed.

[0106] In some embodiments, the board to be detected is an expansion backplane (i.e. Figure 3 Take RISER BP in the example, and continue to refer to the above Figure 3 , when checking the correctness of the connection between RISER BP and SW, it can be achieved through the following steps: the CPLD on the SW board sends I2C data through IIC1 (corresponding to DET_ID1-8, and DET_ID1 is set to 1, DET_ID2-7 are all set to 0, that is, 10000000), and sends it to the PCA9555 chip in RISER BP via the cable CABLE1-8.

[0107] Among them, the PCA9555 chip in RISER BP converts the data into DET_ID1-8 readback signals; the DET_ID1-8 readback signals are returned to the SW chip through IIC3, and converted into I2C data and sent back to the CPLD for reception; the I2C data sent by the CPLD (i.e. 10000000) is compared with the I2C data finally received (whether it is 10000000), so as to determine whether CABLE1 is connected correctly.

[0108] In addition, the CPLD on the SW board uses the IIC signal to set the DET_ID signal output by the PCA9555 chip in the RISER BP and the DET_ID signal output by the RISER1 PCA9555 chip in a polling manner, that is, first set DET_ID1 to 1 and the rest to 0, then set DET_ID2 to 1 and the rest to 0, and so on, to achieve polling detection of 32 CABLE cables.

[0109] The number of DET_ID signals on the CABLE can be adjusted according to the number of CABLEs that need to be detected to reduce the number of polling times.

[0110] Further, based on the above embodiments, in some embodiments, taking the board to be detected as an extended backplane and at least two identical first and second backplanes as an example, the backplane is generally first connected to the extended backplane through a cable, and then the extended backplane is connected to the SW board through a cable. That is, the Nth second connector of the extended backplane is connected to the Nth first connector through the Nth cable; the Xth second connector of the first backplane is connected to the N+Xth second connector of the extended backplane through the Xth cable; the Yth second connector of the second backplane is connected to the N+Yth second connector of the extended backplane through the Yth cable, the extended backplane is connected to the data processing component through at least one integrated circuit bus, and the first backplane and the second backplane are connected to the data processing component through at least one integrated circuit bus.

[0111] Wherein, X and Y are positive integers.

[0112] Refer to the above Figure 3 , X and Y are both 4, and the two identical BP1s are connected to the RISER BP through cables. The first backplane at the rear window of the whole machine is connected to the RISER BP through cables CABLE9-CABLE12, and is also connected to the CPLD through IIC4. At this time, the first backplane has 4 second connectors (i.e. Figure 3 Connectors 1-4 in the rear window position BP1 of the whole machine).

[0113] In addition, the backplane at the front window of the whole machine is connected to the RISER BP through cables CABLE13-CABLE16, and is also connected to the CPLD through IIC5. At this time, the second backplane has 4 second connectors (i.e. Figure 3 Connectors 1-4 in the front window position BP1 of the whole machine).

[0114] Further, in some embodiments, when the board to be tested includes two identical backplanes (i.e. Figure 3The first backplane BP1 and the second backplane BP1 in the device need to configure the value of each bit of data to be as different as possible to distinguish whether the two identical backplanes are at the rear window position or the front window position of the whole device. That is, DET_ID9-12 can be set to represent "1010", and DET_ID13-16 can be set to represent "0101" to distinguish whether the two identical BP1s are at the front window position or the rear window position.

[0115] Among them, two identical BP1s can use IIC3 to write DET_ID9~DET_ID12 as 1010 (that is, the characteristic signal DET_ID9 represents the value of the first bit of data as "0", the characteristic signal DET_ID10 represents the value of the second bit of data as 1, the characteristic signal DET_ID11 represents the value of the third bit of data as "0", and the characteristic signal DET_ID12 represents the value of the fourth bit of data as "1"). Similarly, two identical BP1s can be distinguished by writing DET_13~DET_16 as 0101 to distinguish whether they are at the front window or the rear window of the chassis.

[0116] Among them, I2C data (corresponding to DET_ID9-12) is sent through IIC3 and sent to the PCA9555 chip in BP1 via CABLE9-12. The PCA9555 chip in BP1 converts the data into DET_ID9-12 readback signal; the DET_ID9-12 readback signal is returned to the chip of the mainboard through IIC4, and converted into I2C data and sent back to the CPLD in SW for reception. The position of BP1 is determined by the returned data and the sent I2C data.

[0117] In addition to detecting whether the backplane cables are accurately connected, the embodiments of the present application can also detect the position of the same backplane. That is, when there are multiple identical backplanes, if these backplanes are in different positions in the chassis, the insertion positions of the same backplane can be distinguished by configuring characteristic signals with specific values.

[0118] Figure 5 A schematic diagram of a cable detection method provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, it includes the following steps:

[0119] (1) The CPLD on the SW board sends I2C data to the PCA9555 chip in RISER BP or the PCA9555 chip in RISER1.

[0120] The I2C data may be an N-bit data, such as the eight-bit data 10000000. The I2C data will be converted into a characteristic signal before being sent, and each characteristic signal represents a value. For example, if the I2C data is the eight-bit data 10000000, then the first characteristic signal may represent the first-bit value "0", the second characteristic signal may represent the second-bit value "0", and so on, the eighth characteristic signal may represent the eighth-bit value "1".

[0121] (2) The PCA9555 chip in RISER BP or the PCA9555 chip in RISER1 converts the data into actual CABLE ID signals.

[0122] (3) The actual CABLE ID signal is returned to the PCA9555 chip on the SW board through the CABLE connection and received.

[0123] (4) The PCA9555 chip on the SW board sends the received I2C data back to the CPLD.

[0124] (5) Compare the I2C data sent and received by the CPLD to see if they are consistent.

[0125] (6) If they are consistent, the SW board, RISER BP, and two RISER1 cables are installed properly and connected correctly.

[0126] (7) If they are not consistent, the SW board, RISER BP, and two RISER1 cables are incorrectly connected. Reconnect them and perform steps 1-5 again.

[0127] An embodiment of the present application also provides a server system, including a server mainboard and a board to be detected plugged into the server mainboard, and the server mainboard is configured to execute the above method to detect whether the connection between the board to be detected and the server mainboard is correct.

[0128] The board to be detected may be at least one of an expansion card RASER, an expansion backplane RASER BP and a backplane BP.

[0129] In this embodiment, the specific definition of the server system can refer to the definition of the detection method for the correctness of the cable connection in the above text, which will not be repeated here. Each module in the above server system can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above modules can be embedded in or independent of the processor in the display device in the form of hardware, or can be stored in the memory in the display device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0130] It is to be understood that the various numerical numbers involved in the embodiments of the present application are only for the convenience of description and are not intended to limit the scope of the embodiments of the present application. In the embodiments of the present application, the size of the sequence number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for detecting the correctness of a cable connection, characterized in that: Applied to a switch board, the switch board is provided with a data processing component and M first connectors, each first connector is connected to the data processing component through a signal line, each first connector is connected to a second connector of a board to be detected through a cable, the board to be detected is connected to the data processing component through an integrated circuit bus, M is a positive integer, and the method comprises: The Nth characteristic signal is distributed to the Nth first connector through the data processing component, and the Nth characteristic signal is sent to the Nth second connector through the cable of the Nth first connector, the N characteristic signals are obtained by converting N bits of data, the Nth characteristic signal is used to characterize the value of the Nth bit of data, and N is a positive integer less than or equal to M; Acquire a readback signal fed back to the data processing component by the board to be detected based on all characteristic signals, and convert the readback signal into readback data; Based on the value of each bit of data and the value of the N bits of data in the read-back data, it is determined whether each cable is connected correctly.

2. The method according to claim 1, characterized in that The method further comprises: Acquire the number of second connectors connected to the chip provided on the board to be detected; Determining a total number of the cables based on the number of the second connectors; The total number is taken as the value of N.

3. The method according to claim 2, characterized in that The determining whether each cable is correctly connected based on the value of each bit of data and the value of N bits of data in the read-back data includes: Determine whether the value of the Nth bit of data is the same as the value of the Nth bit of data in the read-back data; If they are the same, make sure the Nth cable is connected correctly; If they are different, it is determined that the Nth cable is incorrectly connected.

4. The method according to any one of claims 1 to 3, characterized in that The board to be detected is at least one of an expansion card, an expansion backplane and a backplane.

5. The method according to claim 4, characterized in that The board to be detected includes at least two identical first expansion cards and second expansion cards; The Kth second connector on the first expansion card is connected to the Kth first connector via the Kth cable, and the first expansion card is connected to the data processing component via an integrated circuit bus; The Lth second connector on the second expansion card is connected to the K+Lth first connector via the K+Lth cable, and the second expansion card is connected to the data processing component via an integrated circuit bus. K and L are both positive integers, and the sum of K and L is less than or equal to N.

6. The method according to claim 5, characterized in that The method further comprises: Converting N bits of data into K pull-up signals and L pull-down signals, the Kth pull-up signal is used to represent the value of the Kth bit of data, and the Lth pull-down signal is used to represent the value of the K+Lth bit of data; The values ​​of K-bit data represented by the K pull-up signals and the values ​​of L-bit data represented by the L pull-down signals are configured to be different.

7. The method according to claim 4, characterized in that The board to be tested also includes an extended backplane and at least two identical first backplanes and second backplanes; The Nth second connector of the expansion backplane is connected to the Nth first connector through the Nth cable; The Xth second connector of the first backplane is connected to the N+Xth second connector of the extension backplane through the Xth cable; The Yth second connector of the second backplane is connected to the N+Yth second connector of the extension backplane through the Yth cable, the extension backplane is connected to the data processing component through at least one integrated circuit bus, the first backplane and the second backplane are connected to the data processing component through at least one integrated circuit bus, and X and Y are positive integers.

8. The method according to claim 7, characterized in that The method further comprises: Converting the N-bit data into E first signals and F second signals, the E-th first signal is used to represent the value of the E-th bit of data, and the F-th second signal is used to represent the value of the E+F-th bit of data; The values ​​of the E-bit data represented by the E first signals and the values ​​of the E+F-bit data represented by the F pull-down signals are configured to be different.

9. The method according to any one of claims 1-3 and 5-8, characterized in that: The data processing component includes a complex programmable logic device and a chip. The complex programmable logic device is connected to the chip via a first integrated circuit bus, the complex programmable logic device is connected to the board to be detected via a second integrated circuit bus, and the chip is connected to the first connector via a signal line.

10. A server system, characterized in that: The server system comprises: a server mainboard and a board to be detected plugged into the server mainboard, wherein the server mainboard is configured to execute the method as described in any one of claims 1 to 9 to detect whether the connection between the board to be detected and the server mainboard is correct.

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