Processor state monitoring method and device, equipment and medium

Abstract

The embodiment of the invention discloses a processor state monitoring method and device, equipment and a medium, and the method comprises the steps: responding to a system starting instruction of a target processor, and triggering a first core body to start initialization; in the initialization process of the first core body, the first core body sets a startup delay timer and controls the second core body to start initialization; before the start-up delay timer ends, if the first core body receives a heartbeat packet sent by the second core body, the first core body is triggered to set a heartbeat packet timer; before the heartbeat packet timer ends, monitoring whether the first core body receives the heartbeat packet sent by the second core body or not; and if the first core body receives the heartbeat packet sent by the second core body, updating the heartbeat packet timer. According to the embodiment of the invention, the second core body is monitored through the first core body, so that the accuracy of monitoring the state of the processor of the heterogeneous multi-core architecture is improved, the system crash is effectively prevented, and the stability of the system is enhanced.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to a processor status monitoring method, device, equipment and medium. Background Art

[0002] The realization of the functions of intelligent electronic devices is inseparable from the processor. As the core component of electronic devices, the processor is responsible for executing instructions and processing data, and is the key to the realization of various functions of intelligent electronic devices. In intelligent electronic devices, the role of the processor is particularly prominent because it can quickly and accurately process data from different sources to ensure the normal operation and efficient work of the equipment. Therefore, it is essential to monitor the status of the processor.

[0003] In the related art, the accuracy of the state monitoring of the processor with heterogeneous multi-core architecture is not high. Therefore, how to improve the accuracy of the state monitoring of the processor with heterogeneous multi-core architecture is an urgent problem to be solved. Summary of the invention

[0004] The embodiments of the present application solve the technical problem of low accuracy of state monitoring of processors with heterogeneous multi-core architecture in the prior art by providing a processor state monitoring method, apparatus, device and medium, thereby achieving the technical effect of improving the accuracy of state monitoring of processors with heterogeneous multi-core architecture.

[0005] In a first aspect, the present application provides a processor state monitoring method, which is applied to a target processor of a heterogeneous multi-core architecture, wherein the target processor includes a first core body and a second core body, and the method includes:

[0006] In response to a system startup instruction of the target processor, triggering the first core body to start initialization;

[0007] During the initialization of the first core body, the first core body sets a power-on delay timer and controls the second core body to start initialization;

[0008] Before the power-on delay timer expires, if the first core receives a heartbeat packet sent by the second core, the first core is triggered to set a heartbeat packet timer;

[0009] Before the heartbeat packet timer ends, monitoring whether the first core body receives the heartbeat packet sent by the second core body;

[0010] If the first core body receives the heartbeat packet sent by the second core body, the heartbeat packet timer is updated, and the process continues to return to the step of monitoring whether the first core body receives the heartbeat packet sent by the second core body before the heartbeat packet timer ends.

[0011] Furthermore, after the first core body sets a power-on delay timer and controls the second core body to start initialization, the method further includes:

[0012] Before the power-on delay timer ends, if the first core body does not receive the heartbeat packet sent by the second core body, the first core body is triggered to control the second core body to restart.

[0013] Further, before the heartbeat packet timer ends, monitoring whether the first core body receives the heartbeat packet sent by the second core body includes:

[0014] Before the heartbeat packet timer ends, if the first core body does not receive the heartbeat packet sent by the second core body, the first core body is triggered to control the second core body to restart.

[0015] Further, after triggering the first core body to start initialization, the method also includes:

[0016] The first core body obtains the actual power supply voltage corresponding to the target processor;

[0017] When the actual power supply voltage exceeds the first range and is within the second range, triggering the first core body to disconnect the voltage communication with the second core body; the second range includes the second range;

[0018] When the actual power supply voltage exceeds the second range, the first core is triggered to write a shutdown instruction to the shared memory to control the second core to shut down.

[0019] Further, after triggering the first core body to start initialization, the method also includes:

[0020] The first core obtains the actual operating temperature of the target processor;

[0021] When the actual operating temperature exceeds the preset temperature threshold, the first core body is triggered to generate a system-enhanced cooling instruction to control the cooling system of the target processor to increase the cooling intensity.

[0022] Further, in response to a system startup instruction of the target processor, triggering the first core body to start initialization includes:

[0023] In response to a system startup instruction of the target processor, triggering the first core to start an independent watchdog;

[0024] The first nucleus monitors whether the status of the independent watchdog is normal;

[0025] When the first core detects that the state of the independent watchdog is abnormal, the first core generates a system startup instruction for restarting the target processor.

[0026] Further, after triggering the first core body to start initialization, the method also includes:

[0027] Identify preset operation events corresponding to the first core body and the second core body respectively; the preset operation events include at least one of a wake-up event, a start event, and an abnormal event;

[0028] Generate a log record according to the preset running events corresponding to the first core body and the second core body respectively.

[0029] In a second aspect, the present application provides a processor state monitoring device, which is applied to a target processor of a heterogeneous multi-core architecture, wherein the target processor includes a first core body and a second core body, and the device includes:

[0030] A startup module, configured to trigger startup initialization of the first core in response to a system startup instruction of the target processor;

[0031] An initialization module, used for setting a power-on delay timer for the first core body during the initialization of the first core body, and controlling the second core body to start initialization;

[0032] A heartbeat packet monitoring module, used for triggering the first core to set a heartbeat packet timer if the first core receives a heartbeat packet sent by the second core before the power-on delay timer expires;

[0033] Before the heartbeat packet timer ends, monitoring whether the first core body receives the heartbeat packet sent by the second core body;

[0034] If the first core body receives the heartbeat packet sent by the second core body, the heartbeat packet timer is updated, and the process continues to return to the step of monitoring whether the first core body receives the heartbeat packet sent by the second core body before the heartbeat packet timer ends.

[0035] Furthermore, the device also includes a restart module, which is used to:

[0036] After the first core body sets the power-on delay timer and controls the second core body to start initialization, before the power-on delay timer ends, if the first core body does not receive the heartbeat packet sent by the second core body, the first core body is triggered to control the second core body to restart.

[0037] Furthermore, the restart module is used to:

[0038] Before the heartbeat packet timer ends, if the first core body does not receive the heartbeat packet sent by the second core body, the first core body is triggered to control the second core body to restart.

[0039] Furthermore, the device also includes a voltage anomaly monitoring module, which is used to:

[0040] After the first core body is triggered to start initialization, the first core body obtains the actual power supply voltage corresponding to the target processor;

[0041] When the actual power supply voltage exceeds the first range and is within the second range, triggering the first core body to disconnect the voltage communication with the second core body; the second range includes the second range;

[0042] When the actual power supply voltage exceeds the second range, the first core is triggered to write a shutdown instruction to the shared memory to control the second core to shut down.

[0043] Furthermore, the device also includes a temperature anomaly monitoring module, which is used to:

[0044] After triggering the first core body to start initialization, the first core body obtains the actual operating temperature of the target processor;

[0045] When the actual operating temperature exceeds the preset temperature threshold, the first core body is triggered to generate a system-enhanced cooling instruction to control the cooling system of the target processor to increase the cooling intensity.

[0046] Furthermore, the device also includes a watchdog monitoring module, which is used to:

[0047] In response to a system startup instruction of the target processor, triggering the first core to start an independent watchdog;

[0048] The first nucleus monitors whether the status of the independent watchdog is normal;

[0049] When the first core detects that the state of the independent watchdog is abnormal, the first core generates a system startup instruction for restarting the target processor.

[0050] Furthermore, the device also includes a log recording module, which is used to:

[0051] After the first core body is triggered to start initialization, the preset operation events corresponding to the first core body and the second core body are identified; the preset operation events include at least one of a wake-up event, a start event, and an abnormal event;

[0052] Generate a log record according to the preset running events corresponding to the first core body and the second core body respectively.

[0053] In a third aspect, the present application provides an electronic device, including:

[0054] processor;

[0055] a memory for storing processor-executable instructions;

[0056] The processor is configured to execute to implement a processor state monitoring method as provided in the first aspect.

[0057] In a fourth aspect, the present application provides a non-temporary computer-readable storage medium. When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to implement a processor status monitoring method as provided in the first aspect.

[0058] In a fifth aspect, the present application provides a computer program product, including computer instructions, which are executed by a processor to implement a processor status monitoring method provided in the first aspect.

[0059] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0060] In the embodiment of the present application, in response to the system startup instruction of the target processor, the first core body is triggered to start initialization; during the initialization of the first core body, the first core body sets a power-on delay timer and controls the second core body to start initialization; before the power-on delay timer ends, if the first core body receives a heartbeat packet sent by the second core body, the first core body is triggered to set a heartbeat packet timer; before the heartbeat packet timer ends, the first core body is monitored to see if it receives a heartbeat packet sent by the second core body; if the first core body receives a heartbeat packet sent by the second core body, the heartbeat packet timer is updated, and the heartbeat packet timer is continued to return to execute the step of monitoring whether the first core body receives a heartbeat packet sent by the second core body before the heartbeat packet timer ends. It can be seen that the embodiment of the present application monitors the second core body through the first core body, timely discovers and handles abnormal conditions of the target processor of the heterogeneous multi-core architecture during operation, improves the accuracy of state monitoring of the processor of the heterogeneous multi-core architecture, effectively prevents system crashes, enhances the stability of the system, and ensures the stability, reliability and security of the target processor of the heterogeneous multi-core architecture during operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0062] Figure 1 A schematic diagram of the structure of a target processor with a heterogeneous multi-core architecture provided in an embodiment of the present application;

[0063] Figure 2 A flowchart of a processor status monitoring method provided in an embodiment of the present application;

[0064] Figure 3 A schematic diagram of the interaction process between the M core and the A core provided in an embodiment of the present application;

[0065] Figure 4 A schematic diagram of the relationship between a first range and a second range of a power supply voltage provided in an embodiment of the present application;

[0066] Figure 5 A schematic diagram of the structure of a processor status monitoring device provided in an embodiment of the present application;

[0067] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] The embodiment of the present application solves the technical problem of low accuracy in status monitoring of processors with heterogeneous multi-core architecture in the prior art by providing a processor status monitoring method.

[0069] The technical solution of the embodiment of the present application is to solve the above technical problems, and the overall idea is as follows:

[0070] In the embodiment of the present application, in response to the system startup instruction of the target processor, the first core body is triggered to start initialization; during the initialization of the first core body, the first core body sets a power-on delay timer and controls the second core body to start initialization; before the power-on delay timer ends, if the first core body receives a heartbeat packet sent by the second core body, the first core body is triggered to set a heartbeat packet timer; before the heartbeat packet timer ends, the first core body is monitored to see if it receives a heartbeat packet sent by the second core body; if the first core body receives a heartbeat packet sent by the second core body, the heartbeat packet timer is updated, and the heartbeat packet timer is continued to return to execute the step of monitoring whether the first core body receives a heartbeat packet sent by the second core body before the heartbeat packet timer ends. It can be seen that the embodiment of the present application monitors the second core body through the first core body, timely discovers and handles abnormal conditions of the target processor of the heterogeneous multi-core architecture during operation, improves the accuracy of state monitoring of the processor of the heterogeneous multi-core architecture, effectively prevents system crashes, enhances the stability of the system, and ensures the stability, reliability and security of the target processor of the heterogeneous multi-core architecture during operation.

[0071] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0072] First of all, the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0073] The embodiment of the present application provides a processor state monitoring method, which is applied to a target processor of a heterogeneous multi-core architecture, wherein the target processor includes a first core body and a second core body, such as Figure 1 The second nuclear body is also called a slave nuclear body, and there can be multiple of them. Figure 1 Only one slave core is shown in FIG. The first core body may include multiple cores, such as Figure 1 The second core body can also include multiple cores, but in Figure 1 For example, S32G is a processor with a heterogeneous multi-core architecture, the first core body is an M core, the second core body is an A core, and the first core body includes cores such as core 0, core 1, core 2, and core 3.

[0074] Compared with the second core body, the first core body can be called the main core, that is, the control level of the first core body is higher than that of the second core body. For multiple cores in the first core body, one core can be designated as the main core in the first core body, for example Figure 1 The core 0 in the processor is used as the main core, and the control level of the core 0 is higher than that of the core 1 and the core 2. The processor state monitoring method provided by the embodiment of the present application is usually executed by the first core body, and specifically can be executed by the main core in the first core body.

[0075] A processor status monitoring method provided in an embodiment of the present application includes steps S21 to S25.

[0076] Step S21, in response to a system startup instruction of the target processor, triggering the startup initialization of the first core body;

[0077] Step S22, during the initialization of the first core body, the first core body sets a power-on delay timer and controls the second core body to start initialization;

[0078] Step S23, before the power-on delay timer ends, if the first core receives a heartbeat packet sent by the second core, the first core is triggered to set a heartbeat packet timer;

[0079] Step S24, before the heartbeat packet timer ends, monitoring whether the first core body receives the heartbeat packet sent by the second core body;

[0080] Step S25, if the first core body receives the heartbeat packet sent by the second core body, the heartbeat packet timer is updated, and the process continues to return to the step of monitoring whether the first core body receives the heartbeat packet sent by the second core body before the heartbeat packet timer ends.

[0081] Regarding step S21, in response to the system startup instruction of the target processor, the first core body startup initialization is triggered.

[0082] The system startup instruction may be generated by the user in a preset manner. For example, the system startup instruction may be generated by the user by touching a mechanical button, or may be generated by the user through voice control.

[0083] In response to the system startup instruction, the first core enters an initialization phase, which includes loading necessary operating systems, drivers, and applications.

[0084] Specifically, in response to the system startup instruction of the target processor, the first core is triggered to start the independent watchdog. The independent watchdog is a timer, and its corresponding target timeout time can be determined according to the clock source, the pre-scaling coefficient and the reload value. The pre-scaling coefficient corresponds to the pre-scaling device, and the reload value corresponds to the reload register. The target timeout time of the independent watchdog is set by setting the pre-scaling device and the reload register. The calculation formula of the target timeout time is:

[0085] T iwdg =T lsi *PR*(RL+1)

[0086] Among them, T iwdg is the target timeout period, T lsi is the constant cycle, PR is the pre-division coefficient, and RL is the pre-load value.

[0087] The independent watchdog is essentially a timer that counts down from the target timeout period. During the normal operation of the target processor, the value of the independent watchdog will be periodically refreshed to a specific value, such as the target timeout period, so as to prevent the independent watchdog counter from being reduced to 0.

[0088] The first core monitors whether the state of the independent watchdog is normal, mainly the main core inside the first core monitors whether the state of the independent watchdog is normal. When the timer of the independent watchdog is not 0, it means that the state of the independent watchdog is normal. If the timer of the independent watchdog becomes 0, it means that the state of the independent watchdog is abnormal. The abnormal state of the independent watchdog may be caused by the program falling into an infinite loop, processor overload, CPU usage, memory occupancy and power consumption.

[0089] When the first core detects that the state of the independent watchdog is abnormal, the first core generates a system startup instruction for restarting the target processor, trying to restore the system to a normal state, and improving the overall stability and reliability of the target processor system. In response to the system startup instruction, the target processor will shut down all cores, reset the hardware state, and go through the initialization, configuration, and application loading stages again. The main core of the first core will re-monitor the state of other cores and the execution of tasks to ensure the normal operation of the system.

[0090] The embodiment of the present application has the ability to prevent dead loops and processor overloads through the configuration and activation of the watchdog timer, thereby improving the security of the system.

[0091] When the first core detects that the status of the independent watchdog is abnormal, it is necessary to record the cause of the abnormality and the restart event to generate a log for subsequent viewing, later problem location, subsequent analysis, troubleshooting and tracking, so as to formulate corresponding maintenance measures.

[0092] Regarding step S22, during the initialization of the first core body, the first core body sets a power-on delay timer and controls the second core body to start initialization.

[0093] During the countdown of the power-on delay timer, the second core is in the stage of completing initialization. The time set by the power-on delay timer can be determined according to the time required for the second core to complete initialization, which is usually longer than the time required for the second core to complete initialization. The initialization of the second core usually includes loading the necessary operating system, driver and application programs.

[0094] After the first core sets the power-on delay timer and controls the second core to start initialization, before the power-on delay timer ends, if the first core does not receive the heartbeat packet sent by the second core, it means that the initialization of the second core fails, and the first core will be triggered to control the second core to restart, trying to restore the second core to normal, thereby improving the overall stability and reliability of the target processor system. The operation of independently restarting the second core ensures that the system can quickly resume normal operation when the second core is in an abnormal state, reducing the system recovery time.

[0095] Before the power-on delay timer ends, if the first core body does not receive the heartbeat packet sent by the second core body, in this case, it is also necessary to record the cause of the exception and the restart event to generate a log for subsequent viewing, later problem location, subsequent analysis, troubleshooting and tracking, so as to formulate corresponding maintenance measures.

[0096] Regarding step S23, before the power-on delay timer ends, if the first core receives a heartbeat packet sent by the second core, the first core is triggered to set a heartbeat packet timer.

[0097] Before the power-on delay timer ends, it is necessary to monitor whether the first core body receives the heartbeat packet sent by the second core body. If the first core body receives the heartbeat packet sent by the second core body, it means that the second core body has completed the initialization normally and is in the normal operation stage. After receiving the heartbeat packet sent by the second core body, the first core body will be triggered to cancel the power-on delay timer, and the first core body will be triggered to set the heartbeat packet timer. Before the heartbeat packet timer ends, it is necessary to monitor whether the first core body receives the heartbeat packet sent by the second core body.

[0098] Regarding step S24, before the heartbeat packet timer ends, it is monitored whether the first core body receives the heartbeat packet sent by the second core body.

[0099] Before the heartbeat packet timer ends, it is necessary to monitor whether the first core body receives the heartbeat packet sent by the second core body.

[0100] Regarding step S25, if the first core body receives the heartbeat packet sent by the second core body, the heartbeat packet timer is updated, and the process continues to return to execute the step of monitoring whether the first core body receives the heartbeat packet sent by the second core body before the heartbeat packet timer ends.

[0101] If the first core receives the heartbeat packet sent by the second core, it means that the second core is in normal operation. After receiving the heartbeat packet sent by the second core, the first core will be triggered to update the heartbeat packet timer, and then continue to wait for the next heartbeat packet sent by the second core, and so on. Receiving the heartbeat packet sent by the second core before the heartbeat packet timer countdown ends means that the second core is in normal state.

[0102] If the heartbeat packet sent by the second core is not received before the heartbeat packet timer countdown ends, it means that the second core is in an abnormal state, and the first core will be triggered to control the second core to restart, trying to restore the second core to normal, thereby improving the overall stability and reliability of the target processor system. The operation of independently restarting the second core ensures that the system can quickly resume normal operation when the second core is in an abnormal state, reducing the system recovery time.

[0103] Before the heartbeat packet timer countdown ends, if the first core body does not receive the heartbeat packet sent by the second core body, in this case, it is also necessary to record the cause of the exception and the restart event to generate a log for subsequent viewing, later problem location, subsequent analysis, troubleshooting and tracking, so as to formulate corresponding maintenance measures.

[0104] It can be seen that the embodiment of the present application performs heartbeat monitoring on the second core through the first core, and the first core can understand the operating status of the second core in real time to ensure the overall stability and reliability of the target processor system.

[0105] The present application embodiment takes the S32G chip as an example to illustrate the above process as a whole, wherein the first core body is the M core and the second core body is the A core. Figure 3 As shown in the figure, Mcore represents M core and Acore represents A core. M core controls A core to enter the initialization phase, and M core starts delay T1 (that is, the power-on delay timer). Before the countdown of T1 ends, if M core receives the heartbeat packet of A core, it means that A core has started normally. Then M core continues to start the operation timeout T2 (that is, the heartbeat packet timer), and T2 can be set to 1 second.

[0106] If the M core receives the heartbeat packet from the A core within the current second, it means that the A core is operating normally within the current second. If the M core does not receive the heartbeat packet from the A core within a certain second, it means that the A core is abnormal within this second, and the M core will control the A core to restart.

[0107] When the M core is restarted (or every time it is started), the startup reason will be recorded locally. The M core can actively send the current startup reason to the A core, and the A core can also actively obtain the startup reason from the M core, and the A core will also save the startup reason. Both the M core and the A core save the startup reason, and the relevant data can be double-backed up to deal with the loss of data in the M core or the A core, thereby improving data security.

[0108] The M core may be started due to local wake-up (also called hard-line wake-up), remote wake-up (including network messages, diagnostic messages, etc.), and chip built-in timer wake-up (mainly used for scheduled wake-up functions, such as: the owner wants to start charging at a certain time tonight). The reason for the M core being woken up is sent to the A core, and the A core can store logs. The M core also has a log recording function, but it is stored in the A core, which is equivalent to data backup.

[0109] For example, in the case of abnormal voltage, core A needs to be restarted after the voltage is restored. At this time, core A must record that it was started after the voltage returned to normal. The voltage detection is placed in core M, so core M reports the startup reason to core A, which is convenient for core A to record and locate the problem later.

[0110] Further, after triggering the first core body to start initialization, the method also includes steps S31 to S33.

[0111] Step S31, the first core obtains the actual power supply voltage corresponding to the target processor;

[0112] Step S32, when the actual power supply voltage exceeds the first range and is within the second range, triggering the first core body to disconnect the voltage communication with the second core body; the second range includes the second range;

[0113] Step S33, when the actual power supply voltage exceeds the second range, trigger the first core to write a shutdown instruction to the shared memory to control the second core to shut down.

[0114] The first core obtains the actual power supply voltage corresponding to the power supply of the target processor, and then determines whether the actual power supply voltage is normal, specifically, whether the actual power supply voltage exceeds a first range. If it exceeds the first range, it means that the voltage is abnormal.

[0115] In the case where the actual power supply voltage exceeds the first range, it is also necessary to determine whether the actual power supply voltage exceeds the second range. If it does not exceed the second range, it is necessary to control the first core body to disconnect the voltage communication with the second core body. The reason is that the data transmission between the first core body and the second core body is mainly achieved through voltage fluctuations. In the case of abnormalities in the actual power supply voltage, the data communicated through voltage between the first core body and the second core body may be wrong. In order to avoid other chain problems caused by erroneous voltage communication data, the first core body will be controlled to disconnect the voltage communication with the second core body to improve communication security and communication accuracy.

[0116] When the actual power supply voltage exceeds the second range, the second core needs to be controlled to shut down. However, since the voltage communication between the first core and the second core has been disconnected when the actual power supply voltage exceeds the first range but does not exceed the second range, the first core needs to write an instruction to shut down the second core into the shared memory, and the second core can automatically shut down after reading the shutdown instruction from the shared memory, so as to reduce the damage to the second core caused by the voltage anomaly.

[0117] By monitoring the power supply voltage in real time and taking corresponding control measures, the first core body can adapt to changes in the external environment, prevent voltage anomalies from causing damage to the core, and improve the optimization level of power management.

[0118] like Figure 4 As shown, it is a schematic diagram of the relationship between the first range, the second range and the actual power supply voltage. Among them, the horizontal axis is the serial number of the actual power supply voltage measured at different time points, and the vertical axis is the voltage amplitude. The normal working range is also the first range, specifically the range of 9V-16V. As long as the actual power supply voltage is within the range of 9V-16V, it is in a normal state. The communication disconnection range is also the second range, specifically including 7V-9V and 16V-18V. When the actual power supply voltage is within the second range, it is necessary to disconnect the voltage communication between the first core body and the second core body. When the actual power supply voltage exceeds the first range and the second range, it is necessary to control the second core body to shut down.

[0119] It can be seen that the first core body monitors the power supply voltage in real time to ensure that it remains within the normal communication and operation range. Once the voltage is detected to be outside the normal range, the first core body will actively disconnect the communication connection between the first core body and the second core body. This measure can prevent chain problems caused by communication anomalies and ensure that other parts of the target processor system continue to operate stably. If the voltage deviates further from the safe range, the first core body will issue an instruction to shut down the second core body. This operation is intended to prevent voltage anomalies from causing damage to the second core body, ensure the integrity of key computing resources, and thus protect the stability of the entire system.

[0120] Further, after triggering the first core body to start initialization, the method also includes step S41-step S42.

[0121] Step S41, the first core obtains the actual operating temperature of the target processor;

[0122] Step S42, when the actual operating temperature exceeds the preset temperature threshold, triggering the first core body to generate a system-enhanced cooling instruction to control the cooling system of the target processor to increase the cooling intensity.

[0123] The first core obtains the actual operating temperature of the target processor and compares the actual operating temperature with the preset temperature threshold. If the operating temperature exceeds the preset temperature threshold, the first core generates a system-enhanced cooling instruction, thereby controlling the cooling system corresponding to the target processor to increase the cooling intensity.

[0124] The real-time monitoring of chip temperature by the First Core and the automatic adjustment of the cooling system ensure that the system can operate stably under various environmental conditions.

[0125] It can be seen that in the embodiment of the present application, the first core body monitors the temperature status of the entire processor in real time to cope with the temperature rise that may be caused by the long-term operation or abnormal conditions of the target processor. When the temperature is detected to be too high, the first core body will automatically adjust the cooling system to increase the cooling intensity, such as increasing the flow rate of the coolant, to ensure that the operating temperature of the target processor is maintained within a controllable safety range, thereby improving the operating reliability of the target processor.

[0126] Further, after triggering the first core body to start initialization, the method also includes step S51-step S52.

[0127] Step S51, identifying preset operation events corresponding to the first core body and the second core body respectively; the preset operation events include at least one of a wake-up event, a start event, and an abnormal event;

[0128] Step S52: Generate a log record according to the preset running events corresponding to the first core body and the second core body respectively.

[0129] The preset operation events include, but are not limited to, abnormal performance indicators, communication disconnection, core shutdown instructions, voltage monitoring, second core shutdown, and heat dissipation adjustment events. When the first core or the second core has a corresponding preset operation event, a corresponding log record is generated.

[0130] That is to say, when any abnormal situation occurs in the first core body or the second core body, the first core body will perform logging measures. The first core body or the second core body will record all key operations and abnormal conditions. These records will serve as system logs to facilitate subsequent analysis, troubleshooting and tracking, so as to take corresponding maintenance measures. During the log recording and processing process, appropriate security measures can also be taken to protect sensitive information from being leaked.

[0131] For example, the first core or the second core will record all heat dissipation adjustment events triggered by abnormal temperature, including time, temperature threshold, measures taken, etc. These records will serve as system logs to support the tracking and analysis of abnormal conditions, providing detailed data support for the analysis, troubleshooting and tracking of abnormal conditions, helping maintenance personnel to quickly locate the source of the problem and take corresponding maintenance measures, which is to facilitate subsequent analysis and auditing, so as to improve the maintainability and traceability of the system.

[0132] In summary, the embodiment of the present application responds to the system startup instruction of the target processor, triggering the startup initialization of the first core body; during the initialization of the first core body, the first core body sets a power-on delay timer and controls the startup initialization of the second core body; before the power-on delay timer ends, if the first core body receives a heartbeat packet sent by the second core body, the first core body is triggered to set a heartbeat packet timer; before the heartbeat packet timer ends, monitor whether the first core body receives the heartbeat packet sent by the second core body; if the first core body receives the heartbeat packet sent by the second core body, the heartbeat packet timer is updated, and the heartbeat packet timer is continued to return to execute the step of monitoring whether the first core body receives the heartbeat packet sent by the second core body before the heartbeat packet timer ends. It can be seen that the embodiment of the present application monitors the second core body through the first core body, timely discovers and handles abnormal conditions of the target processor of the heterogeneous multi-core architecture during operation, improves the accuracy of state monitoring of the processor of the heterogeneous multi-core architecture, effectively prevents system crashes, enhances the stability of the system, and ensures the stability, reliability and security of the target processor of the heterogeneous multi-core architecture during operation.

[0133] In addition, the embodiment of the present application can also monitor external environmental changes (such as power supply voltage fluctuations, chip temperature rise, etc.) through the first core body, take corresponding power supply control and temperature adjustment measures, and ensure the normal operation of the target processor of the heterogeneous multi-core architecture in various environments. Furthermore, the first core body or the second core body records the occurrence and processing of abnormal events in detail, provides log access and analysis tools, and facilitates subsequent troubleshooting and performance optimization.

[0134] Based on the same inventive concept, the present application embodiment provides the following Figure 5 A processor state monitoring device is shown, which is applied to a target processor of a heterogeneous multi-core architecture, wherein the target processor includes a first core body and a second core body, and the device includes:

[0135] A startup module 51, configured to trigger startup initialization of the first core in response to a system startup instruction of a target processor;

[0136] Initialization module 52, used for setting a power-on delay timer for the first core body during the initialization of the first core body, and controlling the second core body to start initialization;

[0137] A heartbeat packet monitoring module 53, configured to trigger the first core to set a heartbeat packet timer if the first core receives a heartbeat packet sent by the second core before the power-on delay timer expires;

[0138] Before the heartbeat packet timer ends, monitoring whether the first core body receives the heartbeat packet sent by the second core body;

[0139] If the first core body receives the heartbeat packet sent by the second core body, the heartbeat packet timer is updated, and the process continues to return to the step of monitoring whether the first core body receives the heartbeat packet sent by the second core body before the heartbeat packet timer ends.

[0140] Furthermore, the device also includes a restart module, which is used to:

[0141] After the first core body sets the power-on delay timer and controls the second core body to start initialization, before the power-on delay timer ends, if the first core body does not receive the heartbeat packet sent by the second core body, the first core body is triggered to control the second core body to restart.

[0142] Furthermore, the restart module is used to:

[0143] Before the heartbeat packet timer ends, if the first core body does not receive the heartbeat packet sent by the second core body, the first core body is triggered to control the second core body to restart.

[0144] Furthermore, the device also includes a voltage anomaly monitoring module, which is used to:

[0145] After the first core body is triggered to start initialization, the first core body obtains the actual power supply voltage corresponding to the target processor;

[0146] When the actual power supply voltage exceeds the first range and is within the second range, triggering the first core body to disconnect the voltage communication with the second core body; the second range includes the second range;

[0147] When the actual power supply voltage exceeds the second range, the first core is triggered to write a shutdown instruction to the shared memory to control the second core to shut down.

[0148] Furthermore, the device also includes a temperature anomaly monitoring module, which is used to:

[0149] After triggering the first core body to start initialization, the first core body obtains the actual operating temperature of the target processor;

[0150] When the actual operating temperature exceeds the preset temperature threshold, the first core body is triggered to generate a system-enhanced cooling instruction to control the cooling system of the target processor to increase the cooling intensity.

[0151] Furthermore, the device also includes a watchdog monitoring module, which is used to:

[0152] In response to a system startup instruction of the target processor, triggering the first core to start an independent watchdog;

[0153] The first nucleus monitors whether the status of the independent watchdog is normal;

[0154] When the first core detects that the state of the independent watchdog is abnormal, the first core generates a system startup instruction for restarting the target processor.

[0155] Furthermore, the device also includes a log recording module, which is used to:

[0156] After the first core body is triggered to start initialization, the preset operation events corresponding to the first core body and the second core body are identified; the preset operation events include at least one of a wake-up event, a start event, and an abnormal event;

[0157] Generate a log record according to the preset running events corresponding to the first core body and the second core body respectively.

[0158] Based on the same inventive concept, the present application embodiment provides the following Figure 6 An electronic device as shown includes:

[0159] Processor 61;

[0160] A memory 62 for storing instructions executable by the processor 61;

[0161] The processor 61 is configured to execute to implement a processor status monitoring method as provided above.

[0162] Based on the same inventive concept, an embodiment of the present application provides a non-temporary computer-readable storage medium. When the instructions in the storage medium are executed by the processor 61 of the electronic device, the electronic device can execute a processor status monitoring method as provided above.

[0163] Based on the same inventive concept, an embodiment of the present application provides a computer program product, including computer instructions, which are executed by the processor 61 to implement a processor status monitoring method provided above.

[0164] Since the electronic device introduced in this embodiment is an electronic device used to implement the information processing method in the embodiment of the present application, based on the information processing method introduced in the embodiment of the present application, a person skilled in the art can understand the specific implementation of the electronic device of the present embodiment and its various variations, so how the electronic device implements the method in the embodiment of the present application is not described in detail here. As long as a person skilled in the art implements the electronic device used by the information processing method in the embodiment of the present application, it belongs to the scope of protection of this application.

[0165] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0166] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0167] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0168] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1The steps for the functions specified in one or more boxes.

[0169] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0170] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A processor status monitoring method, characterized in that: A target processor applied to a heterogeneous multi-core architecture, the target processor comprising a first core body and a second core body, the method comprising: In response to a system startup instruction of the target processor, triggering the first core body to start initialization; During the initialization of the first core body, the first core body sets a power-on delay timer and controls the second core body to start initialization; Before the power-on delay timer ends, if the first core receives a heartbeat packet sent by the second core, the first core is triggered to set a heartbeat packet timer; Before the heartbeat packet timer ends, monitoring whether the first core body receives the heartbeat packet sent by the second core body; If the first core body receives the heartbeat packet sent by the second core body, the heartbeat packet timer is updated, and the process continues to return to the step of monitoring whether the first core body receives the heartbeat packet sent by the second core body before the heartbeat packet timer ends.

2. The method according to claim 1, characterized in that After the first core body sets a power-on delay timer and controls the second core body to start initialization, the method further includes: Before the power-on delay timer ends, if the first core body does not receive the heartbeat packet sent by the second core body, the first core body is triggered to control the second core body to restart.

3. The method according to claim 1, characterized in that Before the heartbeat packet timer ends, monitoring whether the first core body receives the heartbeat packet sent by the second core body includes: Before the heartbeat packet timer ends, if the first core body does not receive the heartbeat packet sent by the second core body, the first core body is triggered to control the second core body to restart.

4. The method according to claim 1, characterized in that After triggering the first core body to start initialization, the method further includes: The first core obtains an actual power supply voltage corresponding to the target processor; When the actual power supply voltage exceeds a first range and is within a second range, triggering the first core to disconnect voltage communication with the second core; the second range includes the second range; When the actual power supply voltage exceeds the second range, the first core is triggered to write a shutdown instruction to the shared memory to control the shutdown of the second core.

5. The method according to claim 1, characterized in that After triggering the first core body to start initialization, the method further includes: The first core obtains the actual operating temperature of the target processor; When the actual operating temperature exceeds a preset temperature threshold, the first core body is triggered to generate a system-enhanced temperature reduction instruction to control the cooling system of the target processor to increase cooling intensity.

6. The method according to claim 1, characterized in that The triggering of the first core body startup initialization in response to the system startup instruction of the target processor includes: In response to the system startup instruction of the target processor, triggering the first core to start an independent watchdog; The first core monitors whether the state of the independent watchdog is normal; When the first core detects that the state of the independent watchdog is abnormal, the first core generates the system startup instruction for restarting the target processor.

7. The method according to claim 1, characterized in that After triggering the first core body to start initialization, the method further includes: Identify preset operation events corresponding to the first core body and the second core body respectively; the preset operation events include at least one of a wake-up event, a start event, and an abnormal event; Generate a log record according to the preset running events corresponding to the first core body and the second core body respectively.

8. A processor status monitoring device, characterized in that: A target processor applied to a heterogeneous multi-core architecture, the target processor comprising a first core body and a second core body, the device comprising: A startup module, configured to trigger startup initialization of the first core in response to a system startup instruction of the target processor; an initialization module, configured to, during the process of initializing the first core body, set a power-on delay timer for the first core body and control the second core body to start initialization; A heartbeat packet monitoring module, configured to trigger the first core to set a heartbeat packet timer if the first core receives a heartbeat packet sent by the second core before the power-on delay timer expires; Before the heartbeat packet timer ends, monitoring whether the first core body receives the heartbeat packet sent by the second core body; If the first core body receives the heartbeat packet sent by the second core body, the heartbeat packet timer is updated, and the process continues to return to the step of monitoring whether the first core body receives the heartbeat packet sent by the second core body before the heartbeat packet timer ends.

9. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute to implement a processor status monitoring method as claimed in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to implement a processor status monitoring method as claimed in any one of claims 1 to 7.

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