DSP + FPGA + ARM-based navigation acquisition and calculation hardware system and method
By adopting the three-core architecture of DSP+FPGA+ARM on the navigation acquisition and calculation hardware platform, the shortcomings of traditional platforms in internal control and external interface design are solved, efficient data processing and real-time communication are achieved, and the reliability of the system is improved. and computational efficiency.
Patent Information
- Application Number
- CN202411019420.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-29
- Publication Date
- 2024-12-13
AI Technical Summary
The traditional navigation acquisition and solution hardware platform has shortcomings in internal control, external interface design, etc., which is difficult to meet the needs of high real-time and high precision, and is also highly cost and complex.
Adopting a three-core architecture based on DSP+FPGA+ARM, the data acquisition module is responsible for the ARM chip, and the navigation and solution module is composed of DSP chip and FPGA chip, which realizes information interaction and data transmission through parallel bus, and uses FPGA's dual-port RAM for high speed Data communication reduces DSP resource consumption and improves computing efficiency.
It realizes miniaturized and integrated design, reduces power consumption, improves the reliability and computing efficiency of the system, and meets the requirements of high precision and real-time.
Smart Images
Figure CN119127776A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of navigation acquisition and solution, and relates to a navigation acquisition and solution hardware system and method, in particular to a navigation acquisition and solution hardware system and method based on DSP+FPGA+ARM. Background Art
[0002] Navigation acquisition and solution systems often involve a large number of matrix operations and floating-point operations, so their hardware platforms need to have strong floating-point computing capabilities, good real-time performance, and high stability. Nowadays, the navigation acquisition and solution hardware solutions widely used in engineering are mainly divided into the following two categories:
[0003] (1) Single processor architecture. This architecture uses a single processor as the core and uses its own general peripheral interface for data interaction to achieve navigation and external communication functions. This structure usually uses general-purpose processors such as ARM and PowerPC, and has the characteristics of small size, low cost, and easy implementation. However, due to the limitation of a single core, its data computing capability is relatively low, and it is mainly used in the field of navigation and solving where accuracy and real-time requirements are not high.
[0004] (2) Multi-processor architecture. This architecture consists of two or more processors working together to complete various tasks of navigation acquisition and solution. Multiple processors are flexibly matched to split and execute complex tasks such as navigation solution, internal control and external communication, thereby improving the computing and communication efficiency of the entire navigation acquisition and solution system. This architecture involves communication and mutual control between multiple cores, which increases the complexity and cost of the hardware platform. It is suitable for navigation solution fields that require high multi-function, real-time and accuracy.
[0005] Traditional multi-processor architecture hardware platforms are mostly built with DSP as the core and FPGA as the auxiliary device. The computing performance can generally be guaranteed, but there are deficiencies in internal control and external interface design.
[0006] After searching, no prior art documents identical or similar to the present invention were found. Summary of the invention
[0007] The purpose of the present invention is to overcome the shortcomings of the prior art and propose a navigation acquisition and solution hardware system and method based on DSP+FPGA+ARM, which not only meets the requirements of strong real-time performance and high calculation accuracy of navigation acquisition and solution, but also can realize miniaturization and integrated design, greatly reduce power consumption and improve reliability.
[0008] The present invention solves the practical problem by adopting the following technical solutions:
[0009] A navigation acquisition and solution hardware system based on DSP+FPGA+ARM, comprising: a data acquisition module and a navigation solution module; the data acquisition module is used for data acquisition and external communication, and comprises an ARM chip, a debugging circuit, a reset circuit and an external interface circuit; the navigation solution module is used for data processing, and comprises a DSP chip, an FPGA chip, a storage circuit, a debugging circuit and a reset circuit; the DSP chip serves as a data main processor unit, and the FPGA chip is used for auxiliary data processing.
[0010] Moreover, the ARM chip is directly connected to the FPGA unit in the navigation solution module through the parallel EPI bus, and the external navigation information is packaged and distributed to realize the information interaction between the data acquisition module and the navigation solution module;
[0011] Moreover, the DSP chip and FPGA chip in the navigation solution module are directly connected through a parallel EMIFA bus, and the torque and other control quantities obtained by the DSP chip are transmitted to the FPGA chip in real time, and then the FPGA chip transmits the torque and other control quantities to the ARM chip, and then the ARM chip transmits them to the external module, thereby achieving the control of the external module; at the same time, the DSP chip has two external asynchronous serial ports, which can exchange data with the host computer; and by designing two dual-port RAMs inside the FPGA chip, it is used to realize data transmission between the DSP chip in the navigation solution module and the ARM chip in the data acquisition module.
[0012] Moreover, the external interface circuit of the data acquisition module is used for data acquisition and external communication, and is formed by logically programming the ARM chip and combining it with an external interface chip; the external interface circuit includes several CAN buses, RS232 serial ports, RS422 / 485 serial ports, GPIO interfaces, ADC / DAC interfaces and PWM interfaces.
[0013] Moreover, the storage circuit in the navigation solution module is used for data and program storage, and is formed by expanding the navigation solution module through the bus; the storage circuit includes 32MB NOR Flash configured through the SPI bus, 128MB NAND Flash configured through the EMIF bus and 128MB SDRAM configured through the DDR2 bus.
[0014] Moreover, the debugging circuits in the data acquisition module and the navigation solution module are used for program development and debugging, including ARM program burning JTAG port and ARM debugging port; FPGA program burning JTAG port and FPGA debugging port; DSP program burning JTAG port and DSP debugging port.
[0015] Moreover, the three processors, namely the DSP chip, the FPGA chip and the ARM chip, all have IO ports connected to light emitting diodes, and the light emitting diodes can be used as debugging nodes to verify various functions of the program.
[0016] Moreover, the reset circuit in the data acquisition module and the navigation solution module utilizes the IO port of the FPGA chip to generate a total reset signal, which is sent to the DSP chip and the ARM chip synchronously after delay to achieve the reset of both.
[0017] A navigation acquisition and solution method based on DSP+FPGA+ARM includes the following steps:
[0018] Step 1: After ARM is powered on and reset, the GPIO, timer, EPI bus, ADC / DAC, PWM, UART, and CAN bus are initialized first, and the external interface circuit formed is used to collect data of external information. After the collection is completed, the flag bit is sent, and the external collection data is sent to the FPGA unit of the navigation solution module through the EPI bus to prepare for the subsequent real-time solution;
[0019] Step 2: After the DSP is powered on and reset, the GPIO, timer, EMIF bus, and UART are initialized first. In the GPIO interrupt service program, the solution flag is set. The flag is judged in the main program. If it meets the requirements, data is received through the EMIFA bus, the solution process is started, and the solution results are sent to the host computer for real-time display.
[0020] Advantages and beneficial effects of the present invention:
[0021] 1. Aiming at the shortcomings of the traditional navigation acquisition and solution platform, the present invention introduces an ARM processor with better capabilities in internal control and external interface design, and proposes a navigation acquisition and solution hardware system based on DSP+FPGA+ARM, which separates data acquisition and navigation solution. Among them, the data acquisition part is based on ARM, which has rich peripheral interfaces and storage resources. The navigation solution part is based on DSP, which can make full use of the powerful computing power of DSP to complete high-intensity, high-precision real-time data processing; FPGA is used to assist DSP in data processing, and with its flexible logic design capabilities and excellent parallel processing capabilities, it enhances the flexibility of hardware platform control and calculation.
[0022] 2. The present invention adopts a three-core architecture of DSP+FPGA+ARM, which separates data acquisition and navigation solution, avoids frequent interruptions of the computing core DSP, and improves computing efficiency. Among them, the data acquisition part is based on ARM, which has rich peripheral interfaces and storage resources. The navigation solution part is based on DSP, which can make full use of the powerful computing power of DSP to complete high-intensity, high-precision real-time data processing. FPGA is used to assist DSP in data processing, and with its flexible logic design capabilities and excellent parallel processing capabilities, it enhances the flexibility of platform control and calculation.
[0023] 3. The core ARM of the data acquisition module and the core DSP of the navigation solution module of the present invention communicate through a parallel bus, using the dual-port RAM inside the FPGA as a carrier to achieve high-speed data communication, which can greatly reduce the resource consumption of the DSP and allow the DSP to focus more on the data processing and calculation process of the navigation solution. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 This is a structural block diagram of the navigation acquisition and solution hardware system of the present invention;
[0025] Figure 2 This is the data acquisition module core ARM main program flow chart of the present invention;
[0026] Figure 3 This is the main program flow chart of the core DSP of the navigation solution module of the present invention. DETAILED DESCRIPTION
[0027] The following further describes the embodiments of the present invention:
[0028] A navigation acquisition and solution hardware system based on DSP+FPGA+ARM, such as Figure 1 As shown, it includes: a data acquisition module and a navigation solution module; the data acquisition module is used for data acquisition and external communication, including an ARM chip, a debugging circuit, a reset circuit and an external interface circuit; the navigation solution module is used for data processing, including a DSP chip, an FPGA chip, a storage circuit, a debugging circuit and a reset circuit; the DSP chip serves as the main data processor unit, and the FPGA chip is used for auxiliary data processing.
[0029] In this embodiment, the ARM chip is directly connected to the FPGA unit in the navigation solution module through the parallel EPI bus, and the external navigation information is packaged and distributed to realize the information interaction between the data acquisition module and the navigation solution module;
[0030] In this embodiment, the DSP chip and the FPGA chip in the navigation solution module are directly connected through a parallel EMIFA bus, and the torque and other control quantities calculated by the DSP chip are transmitted to the FPGA chip in real time, and then the FPGA chip transmits the torque and other control quantities to the ARM chip, and then the ARM chip transmits them to the external module, thereby achieving the control of the external module; at the same time, the DSP chip has two external asynchronous serial ports, which can interact with the host computer for data; and by designing two dual-port RAMs inside the FPGA chip, it is used to realize data transmission between the DSP chip in the navigation solution module and the ARM chip in the data acquisition module.
[0031] In this embodiment, the external interface circuit of the data acquisition module is used for data acquisition and external communication, and is composed by logically programming the ARM chip and combining it with an external interface chip; the external interface circuit includes several CAN buses, RS232 serial ports, RS422 / 485 serial ports, GPIO interfaces, ADC / DAC interfaces and PWM interfaces.
[0032] In this embodiment, the storage circuit in the navigation solution module is used for data and program storage, and is formed by expanding the navigation solution module through a bus; the storage circuit includes a 32MB NOR Flash configured via an SPI bus, a 128MB NAND Flash configured via an EMIF bus, and a 128MB SDRAM configured via a DDR2 bus.
[0033] In this embodiment, the debugging circuits in the data acquisition module and the navigation solution module are used for program development and debugging, including ARM program burning JTAG port and ARM debug port; FPGA program burning JTAG port and FPGA debug port; DSP program burning JTAG port and DSP debug port.
[0034] In this embodiment, in order to increase the testability of the system, the three processors, namely the DSP chip, the FPGA chip and the ARM chip, all have IO ports connected to light-emitting diodes (the IO ports are set as inputs), and the light-emitting diodes can be used as debugging nodes to verify the various functions of the program.
[0035] In this embodiment, the reset circuit in the data acquisition module and the navigation solution module uses the IO port of the FPGA chip to generate a total reset signal, which is sent to the DSP chip and the ARM chip synchronously after a delay to achieve the reset of both and ensure the synchronization of the program. At the same time, the platform is designed with a manual reset switch to test the function.
[0036] In this embodiment, the ARM chip in the data acquisition module synchronously collects external information data and sends it to the FPGA chip of the navigation solution module through the parallel EPI bus; after the FPGA chip receives the data and solution instructions sent by the ARM chip, it sends them to the DSP chip in real time through the parallel EMIFA bus; after the DSP chip receives the data and solution instructions sent by the FPGA chip, it performs platform solution, and sends the calculation results to the host computer for display through the external serial port, and at the same time sends the solved data information back to the ARM chip through the FPGA chip; the DSP chip receives the control instructions of the host computer, completes various working mode switching, and sends the host computer instructions to the ARM chip in the same way; the ARM communicates data and instructions with external devices of the hardware platform through the external interface circuit.
[0037] The functions and effects of each module are further explained below:
[0038] The ARM chip is used as the core of control data communication, and the communication control and calculation independence of the hardware platform are achieved through unified management of various external interfaces and navigation solution modules.
[0039] The use of FPGA chips to assist the platform's data flow control logic and data processing tasks enhances the flexibility of the hardware platform's control and calculation.
[0040] The use of DSP chip as the core of the navigation solution ensures that the hardware platform has powerful computing capabilities and can meet the processing needs of huge amounts of data.
[0041] The three processors used are fully interconnected in hardware, ensuring the flexibility of the platform in communication and computing structure.
[0042] The data acquisition module uses the ARM chip as the core of controlling data communication, and forms an external interface circuit by logically programming the ARM chip and combining it with an external interface chip. The ARM chip is directly connected to the FPGA unit in the navigation solution module through a parallel EPI bus to ensure the communication capability between the data acquisition module and the navigation solution module.
[0043] The navigation solution module is a dual-core processor, including a DSP chip and an FPGA chip, which are directly connected through a parallel EMIFA bus to ensure the real-time data transmission and the reliability of the solution. At the same time, the DSP chip has two asynchronous serial ports, which have the function of data interaction with the host computer. By designing two dual-port RAMs inside the FPGA, data transmission between the core DSP unit of the navigation solution module and the core ARM unit of the data acquisition module is realized.
[0044] The external interface circuit includes several CAN buses, RS232 serial ports, RS422 / 485 serial ports, GPIO interfaces, ADC / DAC interfaces, and PWM interfaces. The three data communication modes of CAN bus, RS232 serial port, and RS422 / 485 serial port all require corresponding transceivers for matching. Since they are communicating with external devices, isolation is required. Most designs use an isolated power supply module for power supply, and use an optical coupler for photoelectric isolation before connecting the transceiver chip for implementation. The present invention uses an isolated transceiver module to implement the above functions, and encapsulates the above functions in one module. The module is small in size, has few external devices, integrates isolation and ESD bus protection functions, and has the characteristics of extremely low electromagnetic radiation EME and strong anti-interference ability.
[0045] The navigation solution process involves a large number of matrix operations and trigonometric function operations, so not only does the processor need to have a large amount of data buffer, but also a large amount of memory space needs to be applied to the processor. In order to prevent the limited on-chip storage space of the core DSP of the navigation solution module from failing to meet the algorithm's requirements for data and program storage space, the hardware platform of the present invention has expanded 32MB of NOR Flash, 128MB of NAND Flash, and 128MB of SDRAM storage circuits. The NOR Flash is used for program storage, the NAND Flash is used for off-chip data storage and backup, and the SDRAM is used for internal data storage.
[0046] The debugging circuit includes ARM program burning JTAG port and ARM debugging port; FPGA program burning JTAG port and FPGA debugging port; DSP program burning JTAG port and DSP debugging port. In order to increase the testability of the platform, for the three processors of DSP, FPGA and ARM, there are IO ports connected to light-emitting diodes (IO ports are set as inputs), and these LEDs can be used as debugging nodes to verify the functions of the program. In addition, the multi-channel CAN bus expanded by ARM can be used as a debugging interface to view the process variables and output results of the program by connecting to the host computer. It is not only convenient for debugging the hardware platform, but also can output the data that the system needs to observe, and assist the system in troubleshooting.
[0047] The reset circuit uses the IO port of the FPGA chip to generate a total reset signal, which is sent to the DSP chip and the ARM chip synchronously after a delay to achieve the reset of both and ensure the synchronization of the program. At the same time, the platform is designed with a manual reset switch to test the function.
[0048] The ARM chip of the data acquisition module synchronously collects external information data and sends it to the FPGA chip of the navigation solution module through the parallel EPI bus; the FPGA receives the data and solution instructions sent by the ARM, and sends them to the DSP chip in real time through the parallel EMIFA bus; the DSP receives the data and solution instructions sent by the FPGA, performs platform solution, and sends the calculation results to the host computer for display through the external expansion serial port, and sends the solved data information back to the ARM chip through the FPGA; the DSP chip receives the control instructions of the host computer, completes the switching of various working modes, and sends the host computer instructions to the ARM chip in the same way; the ARM communicates data and instructions with external devices of the hardware platform through the external interface circuit.
[0049] A navigation acquisition and solution method based on DSP+FPGA+ARM, such as Figure 2 and Figure 3 As shown, the following steps are included:
[0050] Step 1: After ARM is powered on and reset, the GPIO, timer, EPI bus, ADC / DAC, PWM, UART, and CAN bus are initialized first, and the external interface circuit formed is used to collect data of external information. After the collection is completed, the flag bit is sent, and the external collection data is sent to the FPGA unit of the navigation solution module through the EPI bus to prepare for the subsequent real-time solution;
[0051] Step 2: After the DSP is powered on and reset, the GPIO, timer, EMIF bus, and UART are initialized first. In the GPIO interrupt service program, the solution flag is set. The flag is judged in the main program. If it meets the requirements, data is received through the EMIFA bus, the solution process is started, and the solution results are sent to the host computer for real-time display.
[0052] It should be emphasized that the embodiments of the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation manner. Any other implementation manners derived by those skilled in the art based on the technical solution of the present invention also fall within the scope of protection of the present invention.
Claims
1. A navigation acquisition and solution hardware system based on DSP+FPGA+ARM, characterized by: include: Data acquisition module and navigation solution module; The data acquisition module is used for data acquisition and external communication, including an ARM chip, a debugging circuit, a reset circuit and an external interface circuit; The navigation solution module is used for data processing, and includes a DSP chip, an FPGA chip, a storage circuit, a debugging circuit and a reset circuit; the DSP chip serves as a main data processor unit, and the FPGA chip is used for auxiliary data processing.
2. The navigation acquisition and solution hardware system based on DSP+FPGA+ARM according to claim 1, characterized in that: The ARM chip is directly connected to the FPGA unit in the navigation solution module through the parallel EPI bus, packages and distributes the external navigation information, and realizes the information interaction between the data acquisition module and the navigation solution module.
3. The navigation acquisition and solution hardware system based on DSP+FPGA+ARM according to claim 1, characterized in that: The DSP chip and FPGA chip in the navigation solution module are directly connected through a parallel EMIFA bus, and the torque and other control quantities obtained by the DSP chip are transmitted to the FPGA chip in real time, and then the FPGA chip transmits the torque and other control quantities to the ARM chip, and then the ARM chip transmits them to the external module, thereby achieving the control of the external module; at the same time, the DSP chip has two external asynchronous serial ports, which can exchange data with the host computer; and two dual-port RAMs are designed inside the FPGA chip to realize data transmission between the DSP chip in the navigation solution module and the ARM chip in the data acquisition module.
4. The navigation acquisition and solution hardware system based on DSP+FPGA+ARM according to claim 1, characterized in that: The external interface circuit of the data acquisition module is used for data acquisition and external communication, and is formed by logically programming the ARM chip and combining it with an external interface chip; the external interface circuit includes several CAN buses, RS232 serial ports, RS422 / 485 serial ports, GPIO interfaces, ADC / DAC interfaces and PWM interfaces.
5. The navigation acquisition and solution hardware system based on DSP+FPGA+ARM according to claim 1, characterized in that: The storage circuit in the navigation solution module is used for data and program storage, and is formed by expanding the navigation solution module through a bus; the storage circuit includes a 32MB NOR Flash configured through an SPI bus, a 128MB NAND Flash configured through an EMIF bus, and a 128MB SDRAM configured through a DDR2 bus.
6. The navigation acquisition and solution hardware system based on DSP+FPGA+ARM according to claim 1, characterized in that: The debugging circuits in the data acquisition module and the navigation solution module are used for program development and debugging, including ARM program burning JTAG port and ARM debugging port; FPGA program burning JTAG port and FPGA debugging port; DSP program burning JTAG port and DSP debugging port.
7. The navigation acquisition and solution hardware system based on DSP+FPGA+ARM according to claim 1, characterized in that: The three processors, namely the DSP chip, the FPGA chip and the ARM chip, all have IO ports connected to light emitting diodes, and the light emitting diodes can be used as debugging nodes to verify various functions of the program.
8. The navigation acquisition and solution hardware system based on DSP+FPGA+ARM according to claim 1, characterized in that: The reset circuit in the data acquisition module and the navigation solution module utilizes the IO port of the FPGA chip to generate a total reset signal, which is sent to the DSP chip and the ARM chip synchronously after a delay to achieve the reset of both.
9. A navigation acquisition and solution method based on DSP+FPGA+ARM, characterized in that: The following steps are involved: Step 1: After ARM is powered on and reset, the GPIO, timer, EPI bus, ADC / DAC, PWM, UART, and CAN bus are initialized first, and the external interface circuit formed is used to collect data of external information. After the collection is completed, the flag bit is sent, and the external collection data is sent to the FPGA unit of the navigation solution module through the EPI bus to prepare for the subsequent real-time solution; Step 2: After the DSP is powered on and reset, the GPIO, timer, EMIF bus, and UART are initialized first. In the GPIO interrupt service program, the solution flag is set. The flag is judged in the main program. If it meets the requirements, data is received through the EMIFA bus, the solution process is started, and the solution results are sent to the host computer for real-time display.