Main board firmware trusted measurement method, server and readable storage medium

Abstract

The invention discloses a trusted measurement method for mainboard firmware, a server and a readable storage medium, and the method comprises the steps: detecting a reset signal of a mainboard when a substrate management controller monitors that the mainboard is in an unsafe operation state; when it is detected that the reset signal of the mainboard is in a reset completion state, sending a reset control signal of a first state to the mainboard so as to control the mainboard to be maintained in the reset completion state; carrying out trusted measurement on the BIOS firmware of the mainboard; and if the measurement result is that the BIOS firmware is credible, sending a reset control signal of a second state to the mainboard to control the mainboard to release a reset state, and enabling the mainboard to enter a starting process. Therefore, under the condition that a hardware circuit of the mainboard is not modified, trusted measurement can be carried out on the unsafe state in the operation process of the mainboard based on the substrate management controller, the hardware cost is reduced, and the operation safety of the whole computing system is improved.

Description

Technical Field

[0001] The present application relates to the field of information security technology, and in particular to a trust measurement method for motherboard firmware, a server, and a readable storage medium. Background Art

[0002] With the development of big data and cloud computing, trusted computing has become an increasingly important research topic in the field of information security. The main goal of a trusted computing system is to build a computing environment that users can expect, thereby ensuring that computing resources will not be maliciously tampered with or stolen.

[0003] In existing server devices, in order to improve the security of the computing environment, one solution is to directly retain the original design of the baseboard management controller (BMC) and the motherboard in the server, insert a trusted board through standard interfaces such as PCIE / miniPCIE / USB, and perform trusted measurement in conjunction with the security software installed in the operating system; another solution is to modify the design of the motherboard and add a trusted platform control module (TPCM) module to the motherboard. The TPCM module will measure the basic input output system (BIOS) and the GRand Unified Bootloader (GRUB) before the motherboard starts. In this solution, only the TPCM module on the entire motherboard is trusted, and the BIOS and GRUB are measured during the power-on process through the TPCM module and the corresponding matching switching chip. However, this solution can cover relatively few operating conditions, generally only for the power-on startup of the motherboard, and other more complex conditions in other operations, such as active reset and passive reset of the motherboard, are not involved. Whether it is an external trusted board or adding a TPCM module to the mainboard, the hardware design cost will increase. Summary of the invention

[0004] The purpose of this application is to provide a trust measurement method, server and readable storage medium for motherboard firmware, which can realize trust measurement of unsafe states during motherboard operation based on a baseboard management controller, reduce hardware costs, and improve the security of the entire computing system operation.

[0005] To achieve the above objectives: In a first aspect, an embodiment of the present application provides a trust measurement method for motherboard firmware, which is applied to a baseboard management controller, wherein the baseboard management controller is used to monitor and manage the operating status of the motherboard, and the method includes: When it is detected that the mainboard is in an unsafe operating state, detecting a reset signal of the mainboard; When detecting that the reset signal of the mainboard is in the reset completion state, sending a reset control signal of a first state to the mainboard to control the mainboard to maintain in the reset completion state; Performing a trust measurement on the BIOS firmware of the mainboard; If the measurement result shows that the BIOS firmware is credible, a reset control signal in the second state is sent to the mainboard to control the mainboard to release the reset state and allow the mainboard to enter a startup process.

[0006] In one embodiment, after the step of sending a reset control signal of the first state to the mainboard, the method further includes: switching the access rights of the BIOS firmware of the mainboard to the main control of the baseboard management controller; After the step of sending the reset control signal of the second state to the mainboard, the method further includes: switching the access permission of the BIOS firmware of the mainboard to the mainboard master control.

[0007] In one implementation, the mainboard being in an unsafe operation state includes: the mainboard being in a power-on startup state, an active reset state, or a passive reset state.

[0008] In one embodiment, the active reset state comprises a hot reset state; Monitor the heartbeat signal of the mainboard via a USB interface or IPMI protocol; When it is detected that the heartbeat signal of the mainboard is abnormal, it is confirmed that the mainboard enters the hot reset state, and a reset control signal of the first state is sent to the mainboard to notify the mainboard to perform a reset operation and maintain the reset completion state.

[0009] In one embodiment, the passive reset state includes a process in which the mainboard is remotely reset by the baseboard management controller; Before detecting the reset signal of the mainboard, the method further includes: When the baseboard management controller is triggered to remotely reset the mainboard, a reset control signal in a third state is sent to the mainboard to control the mainboard to perform a reset operation.

[0010] In one embodiment, before detecting the reset signal of the mainboard, the method further includes: Detecting a power-on completion signal of the mainboard to confirm that the mainboard has completed powering on; The current state of the reset control signal is obtained to confirm that the reset control signal is in an initial state.

[0011] In one implementation, the initial state of the reset control signal is a first level signal; The first state of the reset control signal is a second level signal; The second state of the reset control signal is a first level pulse signal; The third state of the reset control signal is a second level pulse signal.

[0012] In a second aspect, an embodiment of the present application provides a trust measurement method for motherboard firmware, which is applied to a motherboard, and the method includes: In response to the received reset command, performing a reset operation according to a reset timing; When the reset operation is completed, the reset signal is set to a reset completion state; In response to the reset control signal of the first state, maintaining the reset completion state, and waiting for the baseboard management controller to perform a trust measurement on the BIOS firmware of the mainboard; In response to the reset control signal in the second state, the reset state is released and the startup process is entered.

[0013] In a third aspect, an embodiment of the present application provides a server, comprising: a baseboard management controller and a mainboard; Wherein, the baseboard management controller is used to execute the trust measurement method of the mainboard firmware as described in the first aspect; The mainboard is used to execute the trust measurement method of mainboard firmware as described in the second aspect.

[0014] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the trust measurement method of the mainboard firmware as described above is implemented.

[0015] The trust measurement method, server and readable storage medium of the motherboard firmware provided in the embodiment of the present application detect the reset signal of the motherboard when the BMC detects that the motherboard is in an unsafe operation state; when it is detected that the reset signal of the motherboard is in the reset completion state, a reset control signal of the first state is sent to the motherboard to control the motherboard to maintain the reset completion state; and the trust measurement of the BIOS firmware of the motherboard is performed; if the measurement result shows that the BIOS firmware is trustworthy, a reset control signal of the second state is sent to the motherboard to control the motherboard to release the reset state, so that the motherboard enters the startup process. In this way, under the condition that the motherboard does not modify the hardware circuit, the trust measurement of the unsafe state during the operation of the motherboard can be realized based on the BMC, which reduces the hardware cost and improves the safety of the operation of the entire computing system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 Schematic diagram of the process of the trust measurement method of the motherboard firmware provided in the embodiment of the present application Figure 1 .

[0018] Figure 2 Schematic diagram of the process of the trust measurement method of the motherboard firmware provided in the embodiment of the present application Figure 2 .

[0019] Figure 3 A schematic diagram of a trust measurement process during power-on startup provided in an embodiment of the present application.

[0020] Figure 4 A schematic diagram of a trust measurement process during active reset provided in an embodiment of the present application.

[0021] Figure 5 A schematic diagram of a trust measurement process for remotely resetting a mainboard provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0023] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0024] It should be understood that, although the terms first, second, third, etc. may be used to describe various information in this article, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this article, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "at the time of..." or "when..." or "in response to determination". Furthermore, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising", "including" indicate that there are described features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Thus, “A, B, or C” or “A, B and / or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B, and C.” An exception to this definition will occur only when a combination of elements, functions, steps, or operations are inherently mutually exclusive in some manner.

[0025] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and it can be performed in other orders. Moreover, at least a portion of the steps in the figure may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0026] It should be noted that in this article, step codes such as S101, S102, etc. are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the sequence. When implementing the step, those skilled in the art may execute S102 first and then S101, etc., but these should all be within the scope of protection of this application.

[0027] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0028] In the subsequent description, the suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present application, and have no specific meanings. Therefore, "module", "component" or "unit" can be used in a mixed manner.

[0029] See also Figure 1 , is a trust measurement method for motherboard firmware provided in an embodiment of the present application. The method can be executed by a server provided in an embodiment of the present application. The server can be implemented in software and / or hardware. In this embodiment, the execution subject of the method is a baseboard management controller (BMC) as an example. The baseboard management controller is used to monitor and manage the operating status of the motherboard. The trust measurement method for motherboard firmware provided in this embodiment includes the following steps. Step S101: When it is detected that the mainboard is in an unsafe operating state, a reset signal of the mainboard is detected.

[0030] Specifically, when the mainboard is running, the BMC in the embodiment of the present application will monitor and manage the operation status of the mainboard. When the mainboard is detected to be in an unsafe operation state, including when the mainboard is detected to be in a power-on startup state, an active reset state, or a passive reset state, the mainboard reset signal PERST will be detected through the complex programmable logic device (CPLD) of the BMC. The reset signal PERST is a global reset signal provided by the mainboard, and this signal is usually provided by a dedicated pin. When the PERST signal is activated, it triggers the reset process of all devices connected to the signal.

[0031] In an embodiment of the present application, before detecting the reset signal of the mainboard, it is also necessary to detect the power-on completion signal of the mainboard to confirm that the mainboard has completed powering on; obtain the current state of the reset control signal to confirm that the reset control signal is in the initial state.

[0032] Step S102: When it is detected that the reset signal of the mainboard is in the reset completion state, a reset control signal of a first state is sent to the mainboard to control the mainboard to maintain in the reset completion state.

[0033] Specifically, in some embodiments of the present application, when the reset of the mainboard is completed, the reset completion state of the reset signal PERST is a low level state, that is, PERST=0; when the BMC determines that the reset of the mainboard is completed by detecting the state of the PERST signal, it will send a reset control signal of the first state to the mainboard, interrupting the operation process of the mainboard, preventing the mainboard from entering the startup process immediately after the reset is completed, and maintaining the mainboard in the reset completion state.

[0034] Normally, the active reset state of the motherboard includes a cold reset state and a hot reset state; wherein the cold reset state is a hardware reset, which controls the motherboard's hardware to reset by changing the state of the motherboard's hardware reset pin; and the hot reset is a software reset, which does not trigger the change of the hardware pin. Therefore, when some servers are hot reset, the BMC cannot determine whether the motherboard has performed a reset operation by the state of the PERST signal. Therefore, in an embodiment of the present application, the BMC monitors the heartbeat signal of the motherboard through a USB interface or an IPMI protocol. The heartbeat signal of the motherboard is a periodically sent signal used to indicate that the system is in a normal operating state. When an abnormality is detected in the heartbeat signal of the motherboard, it indicates that the motherboard is in an abnormal operating state. At this time, the BMC will confirm that the motherboard has entered a hot reset state, and send a reset control signal of the first state to the motherboard, notifying the motherboard to perform a reset operation and maintain it in a reset completion state. When the motherboard receives the reset control signal of the first state, it will perform a reset operation according to the reset timing, and after the reset operation is completed, it will maintain the reset completion state and wait for the BMC to perform a trust measurement.

[0035] In some embodiments of the present application, the passive reset state includes a process in which the mainboard is remotely reset by the baseboard management controller; when the baseboard management controller is triggered to remotely reset the mainboard, a reset control signal of the third state is sent to the mainboard to control the mainboard to perform a reset operation. Specifically, during the operation of the mainboard, when the CPLD of the mainboard detects the reset control signal of the third state sent by the BMC, the mainboard is triggered to perform a reset operation according to the reset timing, and after the reset operation is completed, the mainboard will set the state of the reset signal to the reset completion state, that is, PERST=0.

[0036] Step S103: Perform a credibility measurement on the BIOS firmware of the mainboard.

[0037] Specifically, when the BIOS firmware of the mainboard is trusted by the BMC, the access right of the BIOS firmware of the mainboard is first switched to the BMC master control. In the embodiment of the present application, the access right of the BIOS firmware is switched to the BMC master control by modifying the value of the SPI switching signal CPU_SPI_SELECT of the mainboard.

[0038] In an embodiment of the present application, when the BMC performs a trust measurement on the BIOS firmware, a copy of the contents in the BIOS will be stored in advance in the BMC's memory. After the BMC completes the self-check and the access permission of the mainboard's BIOS firmware is switched to the BMC master control, the BMC obtains the current contents of the BIOS firmware through the SPI (serial peripheral interface) and matches them with the initial contents stored in the BMC. If the contents are the same, the verification passes, confirming that the BIOS firmware is trustworthy. If they are different, a verification failure will be prompted, preventing the mainboard from entering the boot process.

[0039] Step S104: If the measurement result shows that the BIOS firmware is credible, a reset control signal of the second state is sent to the mainboard to control the mainboard to release the reset state and allow the mainboard to enter the startup process.

[0040] Specifically, when the measurement result shows that the BIOS firmware is credible and a reset control signal of the second state is sent to the mainboard, the access right of the mainboard's BIOS firmware needs to be switched to the mainboard master control so that the mainboard can continue to access the content in the BIOS firmware and enter the startup process normally.

[0041] In one embodiment of the present application, the initial state of the reset control signal is a first level signal, the first state of the reset control signal is a second level signal, the second state of the reset control signal is a first level pulse signal, and the third state of the reset control signal is a second level pulse signal. Exemplarily, when the reset control signal in the initial state is designed to be a high level signal, the reset control signal in the first state may be a low level signal, the reset control signal in the second state may be composed of four consecutive high level pulse signals, and the reset control signal in the third state may be composed of eight consecutive low level pulse signals.

[0042] In summary, the trust measurement method of the motherboard firmware provided in the above embodiment detects the reset signal of the motherboard when the BMC detects that the motherboard is in an unsafe operating state; when it is detected that the reset signal of the motherboard is in a reset completion state, a reset control signal of the first state is sent to the motherboard to control the motherboard to maintain in the reset completion state; and the trust measurement of the BIOS firmware of the motherboard is performed; if the measurement result shows that the BIOS firmware is trustworthy, a reset control signal of the second state is sent to the motherboard to control the motherboard to release the reset state, so that the motherboard enters the startup process. In this way, under the condition that the hardware circuit of the motherboard is not modified, only by modifying the interaction logic between the BMC and the motherboard, the trust measurement of the unsafe state during the operation of the motherboard can be realized based on the BMC, which not only does not require the addition of an additional measurement module, but also increases flexibility and ease of operation, reduces hardware costs, and improves the security of the operation of the entire computing system.

[0043] See also Figure 2 , which is a trust measurement method for mainboard firmware provided in an embodiment of the present application. The method can be executed by the server provided in an embodiment of the present application. The server can be implemented in software and / or hardware. In this embodiment, the execution subject of the method is the mainboard of the server as an example. The trust measurement method for mainboard firmware provided in this embodiment includes the following steps.

[0044] Step S201: In response to the received reset command, a reset operation is performed according to a reset sequence.

[0045] Specifically, in an embodiment of the present application, when the mainboard receives a reset command, the CPLD of the mainboard will pull the reset pin of the integrated circuit (IC) from a high level to a low level in sequence according to the reset timing, triggering the reset process of the IC, returning the IC to an initial state, and clearing the internal counters, registers, and state machines of the chip; pull the reset pin of the PCIE peripheral from a high level to a low level, so that the PCIE device performs a state reset, including link training and initialization processes; pull the reset pin of the CPU to a low level state, so that the CPU performs initialization.

[0046] Step S202: When the reset operation is completed, the reset signal is set to a reset completion state.

[0047] Specifically, when the above reset operation is completed, the reset signal PERST is set to a reset completion state, that is, PERST=0.

[0048] Step S203: In response to the reset control signal in the first state, maintaining the reset completion state, and waiting for the baseboard management controller to perform a trust measurement on the BIOS firmware of the mainboard.

[0049] Step S204: in response to the reset control signal of the second state, releasing the reset state and entering the startup process.

[0050] Specifically, when the BMC detects the reset signal PERST=0, it determines that the motherboard reset is complete and sends a reset control signal of the first state to the motherboard. After receiving the reset control signal of the first state, the motherboard maintains the reset completion state and waits for the BMC to measure the trustworthiness of the motherboard's BIOS firmware. At this time, it will not continue to enter the boot process. Only when the BIOS firmware is confirmed to be trustworthy after measurement, and after receiving the reset control signal of the second state sent by the BMC, the motherboard will release the reset state, load the BIOS program, and enter the boot process.

[0051] In this embodiment, the reset control signal of the first state sent by the BMC is used to reset the mainboard. The mainboard will enter the boot process only after it passes the trust measurement by the BMC. This can prevent the mainboard processor from running untrusted BIOS programs, build a safer computing environment for users, and reduce the risk of computing resources being maliciously tampered with or stolen.

[0052] See also Figure 3 , is a schematic diagram of the trust measurement process during power-on startup provided by an embodiment of the present application. Figure 3 The trust measurement process at power-on startup is introduced in detail.

[0053] When the server device is in standby (STBY) mode, the mainboard has received power supply, but has not been fully started, and is waiting for an external power button or BMC remote command to fully start. If the user presses the physical power button on the chassis, or outputs a remote power command through the BMC, the power-on / off signal BMC_PWRBTN_N output by the BMC to the mainboard is pulled high to control the system to start remotely. In response to the remote power-on command sent by the BMC, the mainboard starts to power on according to the timing requirements, and after the power-on is completed, it outputs a power-on completion signal to notify the BMC, that is, the power-on completion signal PWRGD is set to 1.

[0054] After the system's STBY power supply is normal, the BMC will perform a power-on self-test to ensure that the BMC is credible. After completing the power-on self-test, the BMC will detect the power-on completion signal PWRGD of the motherboard through the BMC's CPLD, and confirm the current state of the reset control signal BMC_RESET_N. If the BMC detects that the power-on completion signal PWRGD output by the motherboard is valid, and the reset control signal BMC_RESET_N is in the initial state, that is, PWRGD=1&BMC_RESET_N=1, the reset signal PERST output by the motherboard is detected. If the reset signal PERST of the motherboard is in the reset completion state, that is, PERST=0, it is determined that the motherboard has performed a reset operation.

[0055] At this time, the BMC will send a reset control signal of the first state to the motherboard, that is, control the reset control signal to be in a low level state (BMC_RESET_N=0), and set the SPI switching signal CPU_SPI_SELECT of the motherboard CPU to 1, and control the access right of the BIOS firmware to switch to the BMC master control; the motherboard is maintained in the reset completion state through the low-level reset control signal BMC_RESET_N, preventing the motherboard from entering the startup process after the reset is completed, and waiting for the completion of the trusted measurement process.

[0056] To prevent the motherboard from accidentally starting up during the trusted measurement process, the BMC will continue to pull down the reset control signal BMC_RESET_N during the measurement process. At the same time, the BMC CPLD notifies the processor through the GPIO (general input / output) interrupt and starts to perform trusted measurement on the BIOS content through the SPI interface. After the trusted measurement is completed, the microprocessor on the BMC card needs to modify the pin state of the CPLD through the I2C bus to control the BMC to send the second state reset control signal to the motherboard, that is, to control the reset control signal BMC_RESET_N to output 4 high-level pulse signals to notify the motherboard that the trusted measurement is completed and can be started. The width of a single pulse can be set to 500µs. At the same time, the SPI switching signal CPU_SPI_SELECT of the motherboard CPU is set to 0, and the access rights of the motherboard BIOS firmware are controlled to be switched to access by the motherboard CPU. After detecting the 4 high-level pulse signals output by BMC_RESET_N, the motherboard releases the reset state according to the reset timing and starts to load the BIOS firmware program to enter the startup process.

[0057] During the power-on process, the reset control signal of the first state sent by the BMC pulls the reset of the motherboard, and the BIOS on the motherboard is accessed by the BMC during the initial power-on process. Even if the motherboard is powered on, the BIOS program cannot be entered. It is necessary to wait for the BMC to measure the motherboard. Only after the measurement is completed will the reset be released to allow the motherboard to start, preventing the motherboard processor from running untrusted BIOS programs.

[0058] See also Figure 4 , is a schematic diagram of the trust measurement process during active reset provided by the embodiment of the present application. Figure 4 The trust measurement process during active reset is introduced in detail. In this embodiment, the mainboard active reset process includes a cold reset process and a hot reset process.

[0059] During the operation of the motherboard, if the user triggers the reboot command by clicking the reset button on the display interface or through software operation, so that the motherboard actively performs the cold reset process, when the BMC detects that the power-on completion signal PWRGD output by the motherboard is valid, and the reset control signal BMC_RESET_N is in the initial state, that is, PWRGD=1&BMC_RESET_N=1, if the BMC detects that the reset signal output by the motherboard is in the reset completion state, that is, PERST=0, it is determined that the motherboard has performed the reset operation.

[0060] At this time, the BMC sends a reset control signal of the first state to the motherboard, that is, BMC_RESET_N=0, so that the motherboard is maintained in the reset completion state, and the SPI switching signal CPU_SPI_SELECT of the motherboard CPU is set to 1, and the access right of the BIOS firmware is switched to the BMC master control; the BMC performs a trust measurement on the current content of the BIOS firmware. After the trust measurement is completed, the BMC sends a reset control signal of the second state to the motherboard, that is, controls the reset control signal BMC_RESET_N to output 4 high-level pulse signals to notify the motherboard that the trust measurement is completed and can be started, and at the same time, sets the SPI switching signal CPU_SPI_SELECT of the motherboard CPU to 0, controls the access right of the motherboard BIOS firmware to be switched to be accessed by the motherboard CPU, and the motherboard releases the reset state according to the reset timing, and starts to load the BIOS firmware program to enter the startup process.

[0061] When the server needs to be quickly reset, and the system needs to perform a hot reset, since the hot reset of some servers will not trigger the change of the hardware pins, the BMC cannot judge the reset state of the mainboard through the state of the PERST signal. Therefore, in this embodiment, the heartbeat signal output by the mainboard is judged through the USB interface or the IPMI protocol. If the BMC detects through IPMI that the system does not send a heartbeat signal, or detects other fault conditions, the BMC will send a reset control signal of the first state to the mainboard, that is, pull down the reset control signal BMC_RESET_N, notify the mainboard to perform the reset operation and maintain it in the reset completion state, and set the SPI switching signal CPU_SPI_SELECT of the mainboard CPU to 1, and control the access rights of the BIOS firmware to switch to the BMC master control. When the mainboard receives the reset control signal of the first state, it will perform the reset operation according to the reset timing, and after the reset operation is completed, maintain the reset completion state, and wait for the BMC to perform a trust measurement. The subsequent process of performing a trust measurement on the BIOS firmware and the operation flow after the BMC measurement are completed are the same as the above-mentioned cold reset process, and will not be repeated here.

[0062] During the active reset process of the above-mentioned motherboard, the BMC will always monitor the operating status of the motherboard. Once it monitors that the reset-related flags fed back by the motherboard are valid, it will determine that the motherboard is reset and trigger the relevant operations of BIOS re-measurement to avoid situations that may threaten the security of the motherboard itself during operation, thereby improving the security of the entire system operation.

[0063] See also Figure 5 , is a schematic diagram of the trust measurement process when remotely resetting the motherboard provided in the embodiment of the present application. Figure 5 The trust measurement process when resetting the mainboard remotely is introduced in detail. During operation of the mainboard, when the mainboard receives the reset control signal in the third state, that is, after the mainboard CPLD detects eight low-level pulse signals continuously sent by the reset control signal bit BMC_RESET_N, it determines that a BMC remote reset command is received.

[0064] When the motherboard receives the reset command, the CPLD of the motherboard will pull the reset pin of the IC from high level to low level in sequence according to the reset timing, triggering the reset process of the IC, returning the IC to the initial state, clearing the internal counters, registers and state machines of the chip; pulling the reset pin of the PCIE peripheral from high level to low level to reset the PCIE device, including link training and initialization process; pulling the reset pin of the CPU to a low level state to enable the CPU to perform initialization.

[0065] It should be noted that the mainboard will not lose power during the reset process, that is, the power-on completion signal PWRGD output by the mainboard remains in a high level state; after the BMC sends a reset control signal in the third state, that is, a remote reset command, it starts to detect whether the reset control signal BMC_RESET_N and the power-on completion signal PWRGD are both 1 after a preset delay. When PWRGD=1&BMC_RESET_N=1, it detects whether the reset signal PERST output by the mainboard is at a low level. If PERST=0, it is determined that the mainboard has performed a reset operation.

[0066] At this time, the BMC sends a reset control signal of the first state to the motherboard, that is, BMC_RESET_N=0, so that the motherboard is maintained in the reset completion state, and the CPU's SPI switching signal CPU_SPI_SELECT is set to 1, and the BIOS firmware is controlled to be accessed by the BMC. The BMC CPLD notifies the processor through the GPIO interrupt to start verifying the BIOS firmware, that is, to perform a trust measurement on the BIOS. During the trust measurement process, the BMC reset control signal BMC_RESET_N remains in a low level state to prevent the motherboard from accidentally starting.

[0067] After the trust measurement is completed, the microprocessor on the BMC card needs to modify the pin status of the CPLD through the I2C bus, and control the BMC to send the reset control signal of the second state to the mainboard, that is, control the reset control signal BMC_RESET_N to output 4 high-level pulse signals to notify the mainboard that the trust measurement is completed and can be started. At the same time, the CPU's SPI switching signal CPU_SPI_SELECT is set to 0, and the access right of the mainboard BIOS is controlled to be switched to access by the mainboard CPU. After detecting the 4 high-level pulse signals output by BMC_RESET_N, the mainboard releases the reset according to the reset timing and starts to enter the startup process.

[0068] In the above-mentioned process of remotely resetting the motherboard, the BMC resets the motherboard through the reset control signal of the interactive interface, and determines the reset state of the motherboard at this time through the reset state signal fed back by the motherboard. In the process of measuring the BIOS firmware, the BMC always controls the motherboard to be in a reset completed state, and only releases the reset to enter the startup program after the measurement is completed, thereby avoiding the motherboard running an untrusted BIOS program during remote reset, which causes the leakage of computing resources.

[0069] In summary, the trusted measurement method of the mainboard firmware provided in the embodiment of the present application maintains the original structure and design of the mainboard, and can realize the trusted measurement of the unsafe state during the operation of the mainboard only by modifying the signal interaction logic of the interactive interface between the BMC and the mainboard. It has strong feasibility and low modification cost, and can cover the mainboard power-on, active reset, passive reset and other operating states that are relatively vulnerable to attack, thereby meeting the requirements for trusted operation of the computing system and ensuring the security of the system operation. In addition, since the BMC card is portable, the trusted measurement process is integrated on the BMC card to achieve the purpose of remote trusted measurement of the mainboard on the basis of ensuring that the original remote monitoring and management functions remain unchanged, thereby enhancing flexibility and portability.

[0070] Based on the same inventive concept as the above-mentioned embodiment, an embodiment of the present invention provides a server, which includes a baseboard management controller and a mainboard. Wherein, the baseboard management controller and the mainboard may each include at least one memory for storing a computer program and at least one processor for executing the computer program stored in the memory. When the computer program stored in the memory is executed, the processor is used to execute the trust measurement method of the mainboard firmware described in the above-mentioned embodiment.

[0071] It should be noted that the detailed functional implementation of each of the above-mentioned units can be referred to the introduction in the aforementioned method embodiment, and will not be repeated here.

[0072] Based on the same inventive concept as the above-mentioned embodiment, this embodiment further provides a computer-readable storage medium, in which a computer program is stored. The computer-readable storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (FlashMemory), a magnetic surface memory, an optical disc, or a read-only optical disc (CD-ROM) or other memory; it may also be various devices including one or any combination of the above-mentioned memories, such as a mobile phone, a computer, a tablet device, a personal digital assistant, etc. When the computer program stored in the computer-readable storage medium is executed by the processor, the trust measurement method of the above-mentioned motherboard firmware is implemented. For the specific steps and processes implemented when the computer program is executed by the processor, please refer to the description of the above-mentioned embodiment, which will not be repeated here.

[0073] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] In this document, the terms "comprises," "comprising," or any other variations thereof, are intended to cover a non-exclusive inclusion of elements other than those listed and may also include additional elements not expressly listed.

[0075] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A trust measurement method for motherboard firmware, characterized in that: Applied to a baseboard management controller, the baseboard management controller is used to monitor and manage the operating status of a mainboard, the method comprising: When it is detected that the mainboard is in an unsafe operating state, detecting a reset signal of the mainboard; When detecting that the reset signal of the mainboard is in the reset completion state, sending a reset control signal of a first state to the mainboard to control the mainboard to maintain in the reset completion state; Performing a trust measurement on the BIOS firmware of the mainboard; If the measurement result shows that the BIOS firmware is credible, a reset control signal in the second state is sent to the mainboard to control the mainboard to release the reset state and allow the mainboard to enter a startup process.

2. The trust measurement method of mainboard firmware according to claim 1, characterized in that: After the step of sending a reset control signal of the first state to the mainboard, the method further includes: switching the access rights of the BIOS firmware of the mainboard to the main control of the baseboard management controller; After the step of sending the reset control signal of the second state to the mainboard, the method further includes: switching the access permission of the BIOS firmware of the mainboard to the mainboard master control.

3. The trust measurement method of mainboard firmware according to claim 1, characterized in that: The mainboard being in an unsafe operation state includes: the mainboard being in a power-on startup state, an active reset state, or a passive reset state.

4. The trust measurement method of mainboard firmware according to claim 3, characterized in that: The active reset state includes a hot reset state; Monitor the heartbeat signal of the mainboard via a USB interface or IPMI protocol; When it is detected that the heartbeat signal of the mainboard is abnormal, it is confirmed that the mainboard enters the hot reset state, and a reset control signal of the first state is sent to the mainboard to notify the mainboard to perform a reset operation and maintain the reset completion state.

5. The trust measurement method of mainboard firmware according to claim 3, characterized in that: The passive reset state includes a process in which the mainboard is remotely reset by the baseboard management controller; Before detecting the reset signal of the mainboard, the method further includes: When the baseboard management controller is triggered to remotely reset the mainboard, a reset control signal in a third state is sent to the mainboard to control the mainboard to perform a reset operation.

6. The trust measurement method of mainboard firmware according to claim 5, characterized in that: Before detecting the reset signal of the mainboard, the method further includes: Detecting a power-on completion signal of the mainboard to confirm that the mainboard has completed powering on; The current state of the reset control signal is obtained to confirm that the reset control signal is in an initial state.

7. The trust measurement method of mainboard firmware according to claim 6, characterized in that: The initial state of the reset control signal is a first level signal; The first state of the reset control signal is a second level signal; The second state of the reset control signal is a first level pulse signal; The third state of the reset control signal is a second level pulse signal.

8. A trust measurement method for motherboard firmware, characterized in that: Applied to a mainboard, the method comprises: In response to the received reset command, performing a reset operation according to a reset timing; When the reset operation is completed, the reset signal is set to a reset completion state; In response to the reset control signal of the first state, maintaining the reset completion state, and waiting for the baseboard management controller to perform a trust measurement on the BIOS firmware of the mainboard; In response to the reset control signal in the second state, the reset state is released and the startup process is entered.

9. A server, characterized in that: include: Baseboard management controller and motherboard; Wherein, the baseboard management controller is used to execute the trust measurement method of the mainboard firmware according to any one of claims 1 to 7; The mainboard is used to execute the trust measurement method of mainboard firmware as claimed in claim 8.

10. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed by a processor, the trust measurement method for mainboard firmware according to any one of claims 1 to 8 is implemented.

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