Gate drive circuit

Abstract

The invention discloses a gate drive circuit. The gate drive circuit comprises an input circuit, a first voltage stabilizing circuit, a first output circuit, a second voltage stabilizing circuit, a second output circuit, a first pull-down circuit and a second pull-down circuit. The input circuit provides a control signal. The first voltage stabilizing circuit receives an external control signal and is coupled to the control signal. The first output circuit provides a timing drive signal and an isolation control signal based on the control signal. The second voltage stabilizing circuit receives an external control signal and is coupled with the time sequence driving signal. The second output circuit provides a gate drive signal based on the isolation control signal. The first pull-down circuit is coupled among the control signal, the timing drive signal and the gradient gate low voltage. The second pull-down circuit is coupled between the gate driving signal and the gate low voltage.

Description

Technical Field

[0001] The invention relates to a driving circuit, and in particular to a gate driving circuit. Background Art

[0002] In current display technology, the gate drive circuit is formed on a glass substrate and is used to provide a gate drive signal to turn on the pixel circuit in the display panel. Since the wire electrodes in the gate drive circuit are adjacent, the charges of the circuits may penetrate through coupling, so the gate drive signal may be affected by the voltage fluctuations of other circuits. Therefore, in order for the pixel circuit in the display panel to operate normally, the gate drive signal needs to stabilize the voltage level to avoid excessive fluctuations. Summary of the invention

[0003] The invention provides a gate driving circuit which can avoid excessive voltage level fluctuation on the gate driving signal.

[0004] The gate drive circuit of the present invention includes an input circuit, a first voltage stabilizing circuit, a first output circuit, a second voltage stabilizing circuit, a second output circuit, a first pull-down circuit and a second pull-down circuit. The input circuit receives a first direction scanning signal, a second direction scanning signal, a first timing drive signal, and a second timing drive signal to provide a first control signal. The first voltage stabilizing circuit receives an external control signal and is coupled between a gate low voltage and the first control signal. The first output circuit receives a first control signal and a first clock signal to provide a third timing drive signal and an isolation control signal. The second voltage stabilizing circuit receives an external control signal and is coupled between a gate low voltage and the third clock drive signal. The second output circuit receives an isolation control signal and a first clock signal to provide a gate drive signal. The first pull-down circuit is coupled between the first control signal, the third timing drive signal and a gradual gate low voltage. The second pull-down circuit is coupled between the gate drive signal and the gate low voltage.

[0005] Based on the above, the gate driving circuit of the embodiment of the present invention, through the first voltage stabilizing circuit, the second voltage stabilizing circuit, the first pull-down circuit and the second pull-down circuit, during the time / period when the gate driving circuit is not started, the control signal, the timing driving signal, and the gate driving signal are stabilized at a lower voltage level (i.e., a non-enabling level) to reduce interference with the pixel voltage.

[0006] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 4 is a system diagram of a gate driving circuit according to an embodiment of the present invention.

[0008] Figure 2 FIG. 4 is a schematic diagram of driving waveforms of a gate driving circuit according to an embodiment of the present invention.

[0009] Wherein, the reference numerals are:

[0010] 100: Gate drive circuit

[0011] 110: Input circuit

[0012] 120: First voltage stabilizing circuit

[0013] 130: First output circuit

[0014] 140: Second voltage stabilizing circuit

[0015] 150: Second output circuit

[0016] 160: First pull-down circuit

[0017] 170: Second pull-down circuit

[0018] C1, C2: capacitors

[0019] CK(n), XCK(n): clock signal

[0020] D2U: Second direction scanning signal

[0021] G(n): Gate drive signal

[0022] M1~M15: Transistor

[0023] Q(n), Q1(n): control signal

[0024] Q'(n): isolated control signal

[0025] S(n-1), S(n), S(n+1): timing drive signal

[0026] U2D: first direction scanning signal

[0027] VEX: External control signal

[0028] VGL: Gate Low Voltage

[0029] VGL1: Gradient gate low voltage DETAILED DESCRIPTION

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present invention, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0031] It should be understood that although the terms "first", "second", "third", etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the "first element", "component", "region", "layer" or "part" discussed below can be referred to as a second element, component, region, layer or part without departing from the teachings of this article.

[0032] The terms used herein are only for the purpose of describing specific embodiments and are not restrictive. As used herein, unless the content clearly indicates, the singular forms "one", "an" and "the" are intended to include plural forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that when used in this specification, the terms "include" and / or "include" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or their combinations.

[0033] Figure 1 is a system diagram of a gate driving circuit according to an embodiment of the present invention. Figure 1 In this embodiment, the gate driving circuit 100 includes an input circuit 110, a first voltage stabilizing circuit 120, a first output circuit 130, a second voltage stabilizing circuit 140, a second output circuit 150, a first pull-down circuit 160 and a second pull-down circuit 170.

[0034] The input circuit 110 receives the first direction scanning signal U2D, the second direction scanning signal D2U, the timing driving signal S(n-1) (corresponding to the first timing driving signal), and the timing driving signal S(n+1) (corresponding to the second timing driving signal) to provide the control signal Q(n) (corresponding to the first control signal), wherein n is an index number. The first voltage regulating circuit 120 receives the external control signal VEX and is coupled between the gate low voltage VGL and the control signal Q(n) so that the control signal Q(n) is stabilized at a disable level (such as the gate low voltage VGL) during the time / period when the gate driving circuit 100 is not activated.

[0035] The first output circuit 130 receives the control signal Q(n) and the clock signal CK(n) (corresponding to the first clock signal) to provide a timing drive signal S(n) (corresponding to the third timing drive signal) and an isolation control signal Q'(n). The second voltage regulator circuit 140 receives an external control signal VEX and is coupled between the gate low voltage VGL and the timing drive signal S(n) so that the timing drive signal S(n) is stabilized at a disable level (such as the gate low voltage VGL) during the time / cycle when the gate drive circuit 100 is not activated.

[0036] The second output circuit 150 receives the isolation control signal Q'(n) and the clock signal CK(n) to provide a gate drive signal G(n), wherein the gate drive signal G(n) is provided to a display panel (not shown) to drive a corresponding pixel circuit (not shown). The first pull-down circuit 160 is coupled between the control signal Q(n), the timing drive signal S(n) and the gradual gate low voltage VGL1, so that the control signal Q(n) and the timing drive signal S(n) are stabilized at the gradual gate low voltage VGL1 during the time / period when the gate drive circuit 100 is not activated, wherein the gradual gate low voltage VGL1 is, for example, independent of the gate low voltage VGL. The second pull-down circuit 170 is coupled between the gate drive signal G(n) and the gate low voltage VGL, so that the gate drive signal G(n) is stabilized at the gate low voltage VGL during the time / period when the gate drive circuit 100 is not activated.

[0037] According to the above, via the first voltage stabilizing circuit 120, the second voltage stabilizing circuit 140, the first pull-down circuit 160 and the second pull-down circuit 170, during the time / period when the gate driving circuit 100 is not activated, the control signal Q(n), the timing driving signal S(n), and the gate driving signal G(n) are stabilized at a lower voltage level (i.e., a non-enabling level) to reduce interference with the pixel voltage.

[0038] In the embodiment of the present invention, the gradual gate low voltage VGL1 may decrease over time to reflect the stress generated by the transistors in the first pull-down circuit 160 being continuously applied with voltage.

[0039] In the present embodiment, the input circuit 110 includes transistors M1 and M2 (corresponding to the first transistor and the second transistor), the first voltage stabilizing circuit 120 includes a transistor M6 (corresponding to the sixth transistor), the first output circuit 130 includes transistors M3 and M4 (corresponding to the third transistor and the fourth transistor), the second voltage stabilizing circuit 140 includes a transistor M7 (corresponding to the seventh transistor), the second output circuit 150 includes a transistor M5 and a capacitor C1 (corresponding to the fifth transistor and the first capacitor), the first pull-down circuit 160 includes transistors M8 to M12 and a capacitor C2 (corresponding to the eighth transistor to the twelfth transistor, and the second capacitor), and the second pull-down circuit 170 includes transistors M13 to M15 (corresponding to the thirteenth transistor to the fifteenth transistor. The transistors M1 to M15 are N-type transistors as an example, and the transistors M1 to M15 may be oxide thin-film transistors (oxide TFTs), but the embodiment of the present invention is not limited thereto.

[0040] In the present embodiment, the transistor M1 has a first end (e.g., one of the source or the drain) for receiving the first direction scan signal U2D, a control end (e.g., a gate) for receiving the timing drive signal S(n-1), and a second end (e.g., the other of the source or the drain) for providing the control signal Q(n). The transistor M2 has a first end coupled to the second end of the transistor M1, a control end for receiving the timing drive signal S(n+1), and a second end for receiving the second direction scan signal D2U. Furthermore, the rear control end (e.g., the bottom gate) of the transistor M1 is coupled to the control end of the transistor M1, and the rear control end of the transistor M2 is coupled to the control end of the transistor M2.

[0041] In the present embodiment, the transistor M3 has a first terminal receiving the control signal Q(n), a control terminal receiving the gate high voltage VGH, and a second terminal providing the isolation control signal Q'(n). The transistor M4 has a first terminal receiving the clock signal CK(n), a control terminal receiving the isolation control signal Q'(n), and a second terminal providing the timing drive signal S(n). Furthermore, the rear control terminal of the transistor M3 receives the gate low voltage VGL, and the rear control terminal of the transistor M4 is coupled to the control terminal of the transistor M4.

[0042] In this embodiment, the transistor M5 has a first terminal for receiving the clock signal CK(n), a control terminal for receiving the isolation control signal Q'(n), and a second terminal for providing the gate drive signal G(n). The capacitor C1 is coupled between the control terminal of the transistor M5 and the second terminal of the transistor M5. In addition, the rear control terminal of the transistor M5 is coupled to the control terminal of the transistor M5.

[0043] In this embodiment, the transistor M6 has a first terminal receiving a gate low voltage VGL, a control terminal receiving an external control signal VEX, and a second terminal coupled to the control signal Q(n). In addition, a rear control terminal of the sixth transistor M6 receives the gate low voltage VGL.

[0044] In this embodiment, the transistor M7 has a first terminal receiving a gate low voltage VGL, a control terminal receiving an external control signal VEX, and a second terminal coupled to the timing driving signal S(n). In addition, the rear control terminal of the seventh transistor M7 receives the gate low voltage VGL.

[0045] In the present embodiment, transistor M8 has a first end for providing control signal Q1(n), a control end for receiving control signal Q(n), and a second end for receiving gradual gate low voltage VGL1. Capacitor C2 is coupled to clock signal CK(n) and the first end of transistor M8. Transistor M9 has a first end for coupling control signal Q(n), a control end for receiving control signal Q1(n), and a second end for receiving gradual gate low voltage VGL1. Transistor M10 has a first end for receiving control signal Q1(n), a control end for receiving external control signal VEX, and a second end for receiving gradual gate low voltage VGL1. Transistor M11 has a first end for coupling timing drive signal S(n), a control end for receiving control signal Q1(n), and a second end for receiving gradual gate low voltage VGL1. Transistor M12 has a first end for coupling timing drive signal S(n), a control end for receiving clock signal XCK(n), and a second end for receiving gradual gate low voltage VGL1. Furthermore, the rear control terminal of the transistor M8 is coupled to the control terminal of the transistor M8 , and a plurality of rear control terminals of the transistors M9 ˜ M12 receive the gradual gate low voltage VGL1 .

[0046] In the present embodiment, the transistor M13 has a first end coupled to the gate drive signal G(n), a control end receiving the control signal Q1(n), and a second end receiving the gate low voltage VGL. The transistor M14 has a first end coupled to the gate drive signal G(n), a control end receiving the clock signal XCK(n), and a second end receiving the gate low voltage VGL. The transistor M15 has a first end coupled to the gate drive signal G(n), a control end receiving the external control signal VEX, and a second end receiving the gate low voltage VGL. In addition, the multiple rear control ends of the transistors M13 to M15 receive the gate low voltage VGL.

[0047] Figure 2 FIG. 1 is a schematic diagram of a driving waveform of a gate driving circuit according to an embodiment of the present invention. Figure 1 and 2In this embodiment, the clock signals CK(n) and XCK(n) are enabled alternately in sequence, so the first pull-down circuit 160 and the second pull-down circuit 170 periodically pull down the timing drive signal S(n) and the gate drive signal G(n) during the time / period when the gate drive circuit 100 is not enabled. In addition, during one frame period, the external control signal VEX can be enabled at least once (e.g., a high voltage level) during the time / period other than when the gate drive circuit 100 is enabled, so as to pull down the control signal Q(n), the control signal Q1(n), the timing drive signal S(n), and the gate drive signal G(n) through the first voltage regulator circuit 120, the second voltage regulator circuit 140, the first pull-down circuit 160, and the second pull-down circuit 170.

[0048] In an embodiment of the present invention, the gate driving circuit 100 may be one of multiple stages of a gate driver (not shown) on a display panel (not shown), that is, the gate driving circuit 100 may be connected in series to form a gate driver (not shown), wherein the gate driver (not shown) may be implemented as a gate on array (GOA), but the embodiment of the present invention is not limited thereto.

[0049] In summary, the gate driving circuit of the embodiment of the present invention, through the first voltage stabilizing circuit, the second voltage stabilizing circuit, the first pull-down circuit and the second pull-down circuit, during the time / period when the gate driving circuit is not started, the control signal, the timing driving signal, and the gate driving signal are stabilized at a lower voltage level (i.e., a non-enabling level) to reduce the interference to the pixel voltage.

[0050] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person having ordinary knowledge in the technical field may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A gate drive circuit, characterized in that: include: An input circuit receives a first direction scanning signal, a second direction scanning signal, a first timing driving signal, and a second timing driving signal to provide a first control signal; A first voltage stabilizing circuit receives an external control signal and is coupled between a gate low voltage and the first control signal; A first output circuit receives the first control signal and a first clock signal to provide a third timing driving signal and an isolation control signal; a second voltage stabilizing circuit, receiving the external control signal and coupled between the gate low voltage and the third timing driving signal; a second output circuit, receiving the isolation control signal and the first clock signal to provide a gate driving signal; a first pull-down circuit coupled between the first control signal, the third timing driving signal and a gradual gate low voltage; and A second pull-down circuit is coupled between the gate driving signal and the gate low voltage.

2. The gate driving circuit according to claim 1, wherein: The input circuit includes: a first transistor having a first terminal for receiving the first direction scanning signal, a control terminal for receiving the first timing driving signal, and a second terminal for providing the first control signal; and A second transistor has a first end coupled to the second end of the first transistor, a control end receiving the second timing driving signal, and a second end receiving the second direction scanning signal.

3. The gate driving circuit according to claim 2, characterized in that: A rear control terminal of the first transistor is coupled to the control terminal of the first transistor, and a rear control terminal of the second transistor is coupled to the control terminal of the second transistor.

4. The gate driving circuit according to claim 1, wherein: The first output circuit comprises: a third transistor having a first terminal receiving the first control signal, a control terminal receiving a gate high voltage, and a second terminal providing the isolation control signal; and A fourth transistor has a first terminal receiving the first clock signal, a control terminal receiving the isolation control signal, and a second terminal providing the third timing driving signal.

5. The gate driving circuit according to claim 4, characterized in that: A rear control terminal of the third transistor receives the gate low voltage, and a rear control terminal of the fourth transistor is coupled to the control terminal of the fourth transistor.

6. The gate driving circuit according to claim 1, wherein: The second output circuit comprises: a fifth transistor having a first terminal for receiving the first clock signal, a control terminal for receiving the isolation control signal, and a second terminal for providing the gate driving signal; and A first capacitor is coupled between the control terminal of the fifth transistor and the second terminal of the fifth transistor.

7. The gate driving circuit according to claim 6, characterized in that: A rear control terminal of the fifth transistor is coupled to the control terminal of the fifth transistor.

8. The gate driving circuit according to claim 1, wherein: The first voltage stabilizing circuit comprises: A sixth transistor has a first terminal receiving the gate low voltage, a control terminal receiving the external control signal, and a second terminal coupled to the first control signal.

9. The gate driving circuit according to claim 8, characterized in that: A rear control terminal of the sixth transistor receives the gate low voltage.

10. The gate driving circuit according to claim 1, wherein: The second voltage stabilizing circuit comprises: A seventh transistor has a first terminal receiving the gate low voltage, a control terminal receiving the external control signal, and a second terminal coupled to the third timing driving signal.

11. The gate driving circuit according to claim 8, characterized in that: A rear control terminal of the seventh transistor receives the gate low voltage.

12. The gate driving circuit according to claim 1, wherein: The first pull-down circuit comprises: an eighth transistor having a first terminal providing a second control signal, a control terminal receiving the first control signal, and a second terminal receiving the gradual gate low voltage; a second capacitor coupled to the first clock signal and the first end of the eighth transistor; a ninth transistor having a first terminal coupled to the first control signal, a control terminal receiving the second control signal, and a second terminal receiving the gradual gate low voltage; a tenth transistor having a first terminal receiving the second control signal, a control terminal receiving the external control signal, and a second terminal receiving the gradual gate low voltage; an eleventh transistor having a first terminal coupled to the third timing driving signal, a control terminal receiving the second control signal, and a second terminal receiving the gradual gate low voltage; and A twelfth transistor has a first end coupled to the third timing driving signal, a control end receiving a second clock signal, and a second end receiving the gradual gate low voltage.

13. The gate driving circuit according to claim 12, wherein: A rear control terminal of the eighth transistor is coupled to the control terminal of the eighth transistor, and a plurality of rear control terminals of the ninth transistor to the twelfth transistor receive the gradual gate low voltage.

14. The gate driving circuit according to claim 12, wherein: The second pull-down circuit comprises: a thirteenth transistor having a first terminal coupled to the gate driving signal, a control terminal receiving the second control signal, and a second terminal receiving the gate low voltage; a fourteenth transistor having a first terminal coupled to the gate driving signal, a control terminal receiving the second clock signal, and a second terminal receiving the gate low voltage; and A fifteenth transistor has a first terminal coupled to the gate driving signal, a control terminal receiving the external control signal, and a second terminal receiving the gate low voltage.

15. The gate driving circuit according to claim 14, characterized in that: A plurality of rear control terminals of the thirteenth transistor to the fifteenth transistor receive the gate low voltage.

16. The gate driving circuit according to claim 1, wherein: The gradual gate low voltage decreases over time.

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