Silicon wafer surface high sheet resistance diffusion method, high sheet resistance TOPCON battery and preparation method

Abstract

The invention provides a silicon wafer surface high sheet resistance diffusion method, a TOPCON cell and a preparation method thereof, and belongs to the technical field of solar cell manufacturing, and the method comprises the steps: placing a silicon wafer needing B diffusion into a closed furnace tube, and heating to a preset reaction temperature; oxygen and BCl3 are introduced into the furnace tube, and B is gradually diffused into the silicon wafer according to the gradient distribution concentration; purging reaction gas and raising the temperature, and preparing subsequent oxidation at a constant temperature; in the oxidation stage, oxygen is introduced into the furnace tube and reacts with the surface of the silicon wafer to generate silicon oxide, so that rich B atoms on the surface of the silicon wafer are sucked out, and the silicon wafer with the high sheet resistance value is obtained; and the pressure in the furnace tube is recovered to normal pressure, cooling is performed, and the high-square-resistance silicon wafer is taken out from the furnace tube. According to the diffusion method provided by the invention, the high sheet resistance of more than 300 ohms of the silicon wafer can be achieved, the contact effect of the battery is not influenced by the subsequent cooperation with the LECO technology, the passivation effect of low surface concentration caused by the high sheet resistance is improved, and the investment of diffusion SE equipment can be saved, so that the cost is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cell manufacturing, and specifically relates to a silicon wafer surface high-square-resistance diffusion method, a high-square-resistance TOPCON cell and a preparation method thereof. Background Art

[0002] TOPCON cell, full name Tunnel Oxide Passivated Contact cell, is a more advanced N-type silicon cell technology. TOPCON is a tunnel oxide passivated contact solar cell technology based on the principle of selective carriers. Its cell structure is an N-type silicon substrate cell. An ultra-thin layer of silicon oxide is prepared on the back of the cell, and then a thin layer of doped silicon is deposited. The two together form a passivated contact structure, which effectively reduces surface recombination and metal contact recombination.

[0003] In order to ensure good electrode contact performance between the screen-printed front metal gate electrode and the emitter, the emitter requires a higher surface doping concentration. The block resistance after diffusion is generally controlled at 60-80Ω / sq (in ohms per square). However, a diffusion layer with a higher doping concentration will cause blue light absorption loss and surface recombination loss of photogenerated carriers, which is not conducive to achieving improved conversion efficiency.

[0004] The Selective Emitter (SE) structure is an effective technology to overcome the above difficulties. The basic structure of a selective emitter solar cell is similar to that of a conventional solar cell, but it is necessary to form a highly doped deep diffusion region at the contact point between the front metal gate electrode and the silicon wafer, and to form a low-doped shallow diffusion region in other areas between the metal gate electrodes. The sheet resistance of the low-doped shallow diffusion region is generally controlled at 90 to 120 Ω / sq. Such a structure can reduce the recombination of the diffusion layer in the area between the front metal gate electrodes, improve the short-wave response of the solar cell, and reduce the contact resistance between the front metal gate electrode and the silicon surface emitter in the diffusion layer, so that the short-circuit current, open-circuit voltage, and fill factor are all improved, thereby improving the conversion efficiency. The currently used SE solution, that is, the selective emitter forms a highly doped deep diffusion region at the contact point between the front metal gate electrode and the silicon wafer, and forms a low-doped shallow diffusion region in other areas between the metal gate electrodes to achieve a better contact effect, and it is necessary to make different sheet resistances for the gate line contact position and the non-contact position.

[0005] Currently, cells made using selective emitter technology have two disadvantages:

[0006] (1) The use of selective emitter technology still cannot take into account both contact and passivation effects.

[0007] (2) Because different regions need to be doped, there are more process steps and higher costs. Summary of the invention

[0008] The embodiment of the present invention provides a high-square-resistance diffusion method on a silicon wafer surface, aiming to solve the problem that low-square-resistance batteries are not conducive to achieving battery efficiency conversion.

[0009] In the first aspect, in order to achieve the above-mentioned purpose, the technical solution adopted by the present invention is: to provide a high-square-resistance diffusion method on a silicon wafer surface, the method comprising:

[0010] Place the silicon wafer that needs B diffusion into a closed furnace tube and heat it to the preset reaction temperature;

[0011] Oxygen and BCl3 are introduced into the furnace tube, and B is gradually diffused into the silicon wafer in a gradient distribution concentration;

[0012] Purge the reaction gas and raise the temperature, and keep the temperature constant to prepare for subsequent oxidation;

[0013] In the oxidation stage, oxygen is introduced into the furnace tube to react with the surface of the silicon wafer to form silicon oxide, so as to absorb the abundant B atoms on the surface of the silicon wafer to obtain a high-resistance silicon wafer;

[0014] The pressure in the furnace tube returns to normal pressure, the temperature drops, and the high-resistance silicon wafer is taken out of the furnace tube.

[0015] In a first aspect, in an achievable manner, the step of placing a silicon wafer that needs B diffusion into a closed furnace tube and heating the tube to a preset reaction temperature includes:

[0016] After evacuation, the ambient temperature in the furnace tube is raised in stages. The first heating duration is 360±10s, and the temperature is raised to 820±5℃.

[0017] The second heating duration is 600±10s, and the temperature is raised to 825±5℃;

[0018] After the leak is found, the third heating period lasts for 300±10s, and the temperature is raised to 825±5℃;

[0019] The constant temperature lasts for 240±10s, and oxygen is introduced;

[0020] The fourth heating duration is 180±10s, and the temperature is raised to 840±5°C, reaching the preset reaction temperature.

[0021] In a first aspect, in an achievable manner, the vacuuming duration is 60±10 s, and the vacuum is evacuated to 0.1 standard atmospheric pressure.

[0022] In a first aspect, in a feasible manner, the flow rate of oxygen gas introduced at a constant temperature is 1500±10 sccm.

[0023] In a first aspect, in an achievable manner, the step of introducing oxygen and BCl3 into the furnace tube and gradually diffusing B into the silicon wafer at a gradient concentration includes:

[0024] The first gradient deposition diffusion, the oxygen flow rate is 400±10sccm, the BCl3 flow rate is 120±10sccm, and the first diffusion duration is 120±10s;

[0025] The fifth heating lasts for 180±10s and the temperature rises to 845±5℃;

[0026] The second gradient deposition diffusion, the oxygen flow rate is 400±10sccm, the BCl3 flow rate is 120±10sccm, and the second diffusion duration is 210±10s;

[0027] The sixth heating lasts for 180±10s and the temperature rises to 855±5℃;

[0028] For the third gradient deposition diffusion, the oxygen flow rate was 400±10sccm, the BCl3 flow rate was 120±10sccm, and the duration of the third diffusion was 210±10s.

[0029] In a first aspect, in an achievable manner, the purging of the reaction gas and the heating to prepare for subsequent oxidation at a constant temperature include:

[0030] The purge duration is 180±10s; the temperature is maintained at 870±5℃;

[0031] The seventh heating lasts for 330±10s and the temperature rises to 895±5℃.

[0032] In a first aspect, in a feasible manner, after the seventh temperature increase, the constant temperature duration is 270±10s, and the temperature is maintained at 895±5°C.

[0033] In a first aspect, in an achievable manner, during the oxidation stage, oxygen is introduced into the furnace tube to react with the surface of the silicon wafer to generate silicon oxide, so as to absorb the abundant B atoms on the surface of the silicon wafer to obtain a high square resistance silicon wafer, comprising:

[0034] In the first oxidation stage, the oxygen flow rate is 18000±10sccm, the duration is 1200±10s, and the temperature is 1010±5℃;

[0035] In the second oxidation stage, the oxygen flow rate is 18000±10sccm, the duration is 2400±10s, and the temperature is 1020±5℃;

[0036] In the third oxidation stage, the oxygen flow rate is 18000±10sccm, the duration is 1800±10s, and the temperature is 1030±5℃;

[0037] Then in the cooling stage, the oxygen flow rate is 18000±10sccm, and the duration is 1500±10s; the temperature drops to 820±5°C.

[0038] In a second aspect, the present invention provides a method for preparing a TOPCON battery based on LECO technology, the method comprising:

[0039] A high-square-resistance silicon wafer is obtained by utilizing the high-square-resistance diffusion method on the surface of a silicon wafer;

[0040] Polysilicon deposition is performed on the front side of the high-resistance silicon wafer;

[0041] Remove BSG and alkali polish;

[0042] Aluminum oxide deposition on the front and back of high-resistance silicon wafers;

[0043] Silicon nitride deposition on the front and back sides of high-resistance silicon wafers;

[0044] Screen printing;

[0045] After heat treatment, LECO treatment is used to obtain a high-resistance TOPCON battery.

[0046] In a third aspect, the present invention provides a high square resistance TOPCON battery, which is prepared by the TOPCON battery preparation method based on LECO technology.

[0047] Compared with the prior art, the high-square-resistance diffusion method on the silicon wafer surface, the preparation method of the TOPCON battery and the high-square-resistance TOPCON battery provided by the present invention have the following beneficial effects: a boron diffusion process with three gradient deposition diffusions is carried out by advancing the step-by-step deposition of source-heating-source-heating-source, so that the deposited B can be deposited uniformly in steps, while ensuring that the square resistance reaches the target value, while maintaining the uniformity of the square resistance, thereby improving the uniformity deterioration caused by the increase of the square resistance, improving the high boron diffusion square resistance, and obtaining a high-square-resistance silicon wafer, and combining with the LECO technology, it is possible to reduce the recombination of photogenerated carriers at the emitter, thereby improving the battery conversion efficiency. DETAILED DESCRIPTION

[0048] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0049] The high-square-resistance diffusion method on the surface of a silicon wafer provided by the present invention is now described. The high-square-resistance diffusion method on the surface of a silicon wafer comprises:

[0050] Place the silicon wafer that needs B diffusion into a closed furnace tube and heat it to the preset reaction temperature;

[0051] Oxygen and BCl3 are introduced into the furnace tube, and B is gradually diffused into the silicon wafer in a gradient distribution concentration;

[0052] Purge the reaction gas and raise the temperature, and keep the temperature constant to prepare for subsequent oxidation;

[0053] In the oxidation stage, oxygen is introduced into the furnace tube to react with the surface of the silicon wafer to form silicon oxide, so as to absorb the abundant B atoms on the surface of the silicon wafer to obtain a high-resistance silicon wafer;

[0054] The pressure in the furnace tube returns to normal pressure, the temperature drops, and the high-resistance silicon wafer is taken out of the furnace tube.

[0055] Compared with the prior art, the high-square-resistance diffusion method on the silicon wafer surface, the preparation method of the TOPCON battery and the high-square-resistance TOPCON battery provided by the present invention have the following beneficial effects: a boron diffusion process with three gradient deposition diffusions is carried out by advancing the step-by-step deposition of source-heating-source-heating-source, so that the deposited B can be deposited uniformly in steps, while ensuring that the square resistance reaches the target value, while maintaining the uniformity of the square resistance, thereby improving the uniformity deterioration caused by the increase of the square resistance, improving the high boron diffusion square resistance, and obtaining a high-square-resistance silicon wafer, and combining with the LECO technology, it is possible to reduce the recombination of photogenerated carriers at the emitter, thereby improving the battery conversion efficiency.

[0056] Through the diffusion method of the present invention, the silicon wafer can achieve a high square resistance of more than 300Ω. The subsequent use of LECO technology will not affect the contact effect of the battery. It can not only improve the passivation effect of the low surface concentration brought by the high square resistance, but also save the investment in diffusion SE equipment and thus reduce costs.

[0057] Since the boron diffusion method of the present invention has many steps and involves many parameters, for the sake of clarity, the process steps of the diffusion method are shown in a table below. The embodiment is as follows:

[0058]

[0059]

[0060] Through the steps and process parameter adjustments provided in the above table, the surface square resistance of the silicon wafer can be greatly increased from the original 95Ω to 370Ω through step-by-step deposition of boron diffusion, thus realizing the preparation of high-square-resistance silicon wafers. The subsequent combination with LECO technology can reduce the recombination of photogenerated carriers at the emitter and improve the battery conversion efficiency.

[0061] The steps in the above table can be divided into the following stages:

[0062] Phase 1: Steps 1 to 9 are the preparation of reaction conditions. The silicon wafer to be diffused is placed in the closed furnace tube where the reaction takes place. Then the sealing of the furnace tube is checked and the temperature is raised to the temperature required for the reaction. Ensure that the temperature of each area of ​​the furnace tube is stable. The time refers to the duration of each step.

[0063] Phase 2: Steps 10 to 14 are deposition diffusion steps for reactions. During this process, oxygen with a flow rate of 400 sccm and BCL3 with a flow rate of 120 sccm are introduced respectively, and B is gradually diffused into the silicon wafer with a gradient concentration. During this process, the amount of source introduced is greatly reduced compared to the normal concentration to reduce the doping concentration.

[0064] Stage 3: Steps 15 to 17 are the process of purging the reaction gas and raising the temperature to prepare for the subsequent oxidation step.

[0065] Stage 4: Steps 18 to 21 are oxidation steps. At this time, oxygen with a flow rate of 18,000 sccm is introduced into the furnace tube to react with the surface of the silicon wafer to form silicon oxide. The solid solubility of B in silicon oxide is greater than that in silicon, so the abundant B atoms on the surface of the silicon wafer are absorbed, and the surface square resistance is controlled to 370Ω while adjusting the uniformity of the surface square resistance to ensure that the metal and the semiconductor can achieve good contact after LECO.

[0066] Stage 5: Step 22 to Step 26, the reaction is completed, the pressure in the furnace tube returns to normal pressure, the temperature drops, and the silicon wafer that has completed diffusion is withdrawn from the furnace tube and prepared to enter the next process.

[0067] During the entire reaction process, the second and fourth stages are most closely related to the introduction of LECO. The second stage significantly reduces the B content diffused to the surface of the silicon wafer; the fourth stage controls the sheet resistance to the required value while adjusting the uniformity. Only after the introduction of LECO can the silicon wafer with a sheet resistance of 370Ω made by the process parameters in the table be used to prepare the battery, so that when in contact with the semiconductor, it can achieve good contact effect and maintain passivation performance, thereby greatly improving the battery conversion efficiency.

[0068] The specific chemical reaction process is:

[0069] 4BCl3+3O2→2B2O3+6Cl2, 2B2O3+3Si→3SiO2+4B

[0070] Steps 10-14 are the deposition diffusion process. By controlling the gradient temperature and time, the B generated by the reaction is deposited in the silicon substrate at different depths with different concentrations. Steps 18-21 are the oxidation process, which also plays the role of gettingtering. Due to the difference in solid solubility, the oxide generated by the reaction of a large flow of oxygen with the silicon substrate absorbs the excess B in the silicon substrate, and the square resistance value is controlled to reach the required 370Ω.

[0071] The battery parameters made by using the 370Ω high square resistance process are significantly improved compared with the conventional SE selective emitter process. The test data are as follows:

[0072] Example 1

[0073] The square resistance test values ​​of silicon wafers obtained by the diffusion method provided by the present invention are shown in Table 1 below:

[0074] Table 1

[0075] Sheet 1 Sheet 2 Slice 3 Slice 4 Slice 5 1 point 386 362 362 383 348 2 o'clock 373 375 375 378 364 3 o'clock 377 372 379 372 371 4 o'clock 378 373 381 380 363 5 o'clock 378 372 383 371 374 6 o'clock 373 368 371 357 353 7 o'clock 364 368 365 352 347 8 o'clock 379 362 383 395 358 9 o'clock 361 383 387 359 391

[0076] Table 1 above is based on normal process monitoring, with 5 high square resistance silicon wafers, each tested at 9 points, and the average square resistance is 371. As a comparison group, the square resistance of conventional SE is 93Ω in the gate line area and 135Ω in the non-gate line contact area. The comparison of battery parameters is shown in Table 2:

[0077] Table 2

[0078] Uoc Isc FF Rs RSH Eff quantity This program 0.7365 14.035 85.59 0.0010 1131 26.48％ 30834 Comparison group 0.7319 13.967 85.64 0.0011 1905 26.285 23519

[0079] From the comparison data of the batteries, we can see that after the square resistance is improved, the voltage and current values ​​of the battery made with high square resistance silicon wafers are significantly improved, and the series resistance Rs reflecting the contact situation has not increased significantly, indicating that the contact effect between the metal and the silicon wafer is good, and the battery efficiency is improved by 0.2%.

[0080] Example 2

[0081] The square resistance test values ​​of the high square resistance silicon wafer prepared by the present invention are as follows in Table 3:

[0082] Table 3

[0083]

[0084]

[0085] The average square resistance monitoring value in the above table is 377. The square resistance value of the conventional SE in the comparison group is 97Ω in the gate line area and 132Ω in the non-gate line contact area. The comparison of battery parameters is shown in Table 4:

[0086] Table 4

[0087] Uoc Isc FF Rs R Eff quantity Comparison group 0.7263 13.914 85.27 0.00122 2006 26.10％ 45544 This program 0.7348 13.95 85.46 0.00123 2025 26.35％ 38574

[0088] Through two large-scale data comparisons, it can be clearly found that the high square resistance process of this solution can significantly improve the battery efficiency, and the effect is obvious. Therefore, the high square resistance silicon wafer with a square resistance of more than 300Ω prepared by the diffusion method provided by the present invention, combined with the LECO technology, can achieve the contact effect of the battery without affecting the low surface concentration passivation effect brought by the high square resistance, and can also save the investment in diffusion SE equipment and reduce costs.

[0089] The principle of high square resistance silicon wafer combined with LECO technology to improve battery conversion efficiency is as follows:

[0090] Before the introduction of LECO technology, to form an ohmic contact between a semiconductor (silicon substrate) and a metal (silver paste), two conditions must be met at the same time: one is a suitable sintering temperature to make the series resistance between the metal and the semiconductor low enough; the other is a sufficient doping concentration.

[0091] There is a potential barrier when metal and semiconductor are in contact. To form current conduction, the potential barrier must be crossed. There are three modes of electron crossing the potential barrier: thermal electron emission, field emission and field thermal electron emission. Under normal circumstances, the field thermal electron emission mode can be satisfied when the doped B concentration is greater than 1E17. As the B doping concentration increases, it gradually transforms to the field emission mode, that is, the field effect is enhanced. However, the increase in the introduction of doped B impurities will lead to an increase in recombination (therefore, the highest square resistance is only 95 ohms in the metal and semiconductor contact area in SE mode), thereby reducing the open circuit voltage of the battery. The purpose of the present invention is to pursue good contact effects at low doping concentrations, which can not only ensure contact but also improve passivation effects, thereby achieving higher battery conversion efficiency.

[0092] With the introduction of LECO technology, laser enhanced sintering forms a mutual dissolution of metal and semiconductor, which can directly conduct the contact. Because the change in contact mode no longer requires the pursuit of a higher B doping concentration, the square resistance can be higher, so that a higher emitter passivation effect can be achieved while ensuring the contact effect, thereby improving the battery efficiency. Through repeated verification, the square resistance can now be achieved to 370Ω or even higher, and the cost of SE and post-annealing processes can also be reduced.

[0093] The relevant terms are explained as follows:

[0094] Boron diffusion: Boron trichloride is introduced and reacts with oxygen under high temperature and low pressure to generate boron atoms that deposit a P-type layer on the surface of the silicon wafer, forming a PN junction.

[0095] LECO: Laser Enhanced Contact Optimization, laser enhanced contact technology, applies bias to the cell and uses the laser-induced local charge flow effect to induce thermal migration of the electrode material to the semiconductor material interface, producing micro-nano-level interlaced fusion between the electrode material / passivation layer / semiconductor to reduce the contact resistance between the metal and the semiconductor. This technology can reduce the material's requirements for sintering temperature and surface doping concentration, while forming better metal-semiconductor contact.

[0096] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0097] Based on the same inventive concept, the present application embodiment also provides a method for preparing a TOPCON battery based on LECO technology, the method comprising:

[0098] A high-square-resistance silicon wafer is obtained by utilizing the high-square-resistance diffusion method on the surface of a silicon wafer;

[0099] Polysilicon deposition is performed on the front side of the high-resistance silicon wafer;

[0100] Remove BSG and alkali polish;

[0101] Aluminum oxide deposition on the front and back of high-resistance silicon wafers;

[0102] Silicon nitride deposition on the front and back sides of high square resistivity silicon wafers;

[0103] Screen printing;

[0104] After heat treatment, LECO treatment is used to obtain a high-resistance TOPCON battery.

[0105] The diffused high square resistance silicon wafer of the present invention can achieve a high square resistance of more than 300Ω. The subsequent use of LECO technology will not affect the contact effect of the battery. It can not only improve the passivation effect of the low surface concentration brought by the high square resistance, but also save the investment in diffused SE equipment and reduce costs.

[0106] The production process of the TOPCON battery preparation method based on LECO technology is as follows: texturing - boron diffusion - oxidation + wet method + alkaline polishing - annealing - alumina + back SiNx - front SiNx - printing - heat treatment - LECO - testing and sorting.

[0107] The present invention provides a high square resistance TOPCON battery, which is prepared by adopting the TOPCON battery preparation method based on LECO technology.

[0108] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for high square resistance diffusion on a silicon wafer surface, characterized in that: The method comprises: Place the silicon wafer that needs B diffusion into a closed furnace tube and heat it to the preset reaction temperature; Oxygen and BCl3 are introduced into the furnace tube, and B is gradually diffused into the silicon wafer at a gradient concentration; Purge the reaction gas and raise the temperature, and keep the temperature constant to prepare for subsequent oxidation; In the oxidation stage, oxygen is introduced into the furnace tube to react with the surface of the silicon wafer to form silicon oxide, which absorbs the abundant B atoms on the surface of the silicon wafer to obtain a high-resistance silicon wafer; The pressure in the furnace tube returns to normal pressure, the temperature drops, and the high-resistance silicon wafer is taken out of the furnace tube.

2. The high square resistance diffusion method on silicon wafer surface as claimed in claim 1, characterized in that: The step of placing the silicon wafer to be diffused by B into a closed furnace tube and heating it to a preset reaction temperature comprises: After evacuation, the ambient temperature in the furnace tube is raised in stages. The first heating duration is 360±10s, and the temperature is raised to 820±5℃. The second heating duration is 600±10s, and the temperature is raised to 825±5℃; After the leak is found, the third heating period lasts for 300±10s, and the temperature is raised to 825±5℃; The constant temperature lasts for 240±10s, and oxygen is introduced; The fourth heating duration is 180±10s, and the temperature is raised to 840±5°C, reaching the preset reaction temperature.

3. The high square resistance diffusion method on silicon wafer surface as claimed in claim 2, characterized in that: The vacuuming duration is 60±10s, and the vacuum is evacuated to 0.1 standard atmospheric pressure.

4. The high square resistance diffusion method on silicon wafer surface as claimed in claim 2, characterized in that: The oxygen flow rate is 1500±10sccm when the temperature is constant.

5. The high square resistance diffusion method on silicon wafer surface as claimed in claim 1, characterized in that: The method of introducing oxygen and BCl3 into the furnace tube and gradually diffusing B into the silicon wafer at a gradient concentration includes: The first gradient deposition diffusion, the oxygen flow rate is 400±10sccm, the BCl3 flow rate is 120±10sccm, and the first diffusion duration is 120±10s; The fifth heating lasts for 180±10s and the temperature rises to 845±5℃; The second gradient deposition diffusion, the oxygen flow rate is 400±10sccm, the BCl3 flow rate is 120±10sccm, and the second diffusion duration is 210±10s; The sixth heating lasts for 180±10s and the temperature rises to 855±5℃; For the third gradient deposition diffusion, the oxygen flow rate was 400±10sccm, the BCl3 flow rate was 120±10sccm, and the duration of the third diffusion was 210±10s.

6. The high square resistance diffusion method on silicon wafer surface as claimed in claim 1, characterized in that: The purging of the reaction gas and heating, and constant temperature preparation for subsequent oxidation, include: The purge duration is 180±10s; the temperature is maintained at 870±5℃; The seventh heating lasts for 330±10s and the temperature rises to 895±5℃.

7. The high square resistance diffusion method on silicon wafer surface as claimed in claim 6, characterized in that: After the seventh heating, the constant temperature lasted for 270±10s and the temperature was maintained at 895±5℃.

8. The high square resistance diffusion method on silicon wafer surface as claimed in claim 1, characterized in that: In the oxidation stage, oxygen is introduced into the furnace tube to react with the surface of the silicon wafer to generate silicon oxide, so as to absorb the abundant B atoms on the surface of the silicon wafer to obtain a high square resistance silicon wafer, including: In the first oxidation stage, the oxygen flow rate is 18000±10sccm, the duration is 1200±10s, and the temperature is 1010±5℃; In the second oxidation stage, the oxygen flow rate is 18000±10sccm, the duration is 2400±10s, and the temperature is 1020±5℃; In the third oxidation stage, the oxygen flow rate is 18000±10sccm, the duration is 1800±10s, and the temperature is 1030±5℃; Then in the cooling stage, the oxygen flow rate is 18000±10sccm, and the duration is 1500±10s; the temperature drops to 820±5°C.

9. A method for preparing a TOPCON battery based on LECO technology, characterized in that: The method comprises: A high-square-resistance silicon wafer is obtained by using the high-square-resistance diffusion method on the silicon wafer surface as described in any one of claims 1 to 8; Polysilicon deposition is performed on the front side of the high-resistance silicon wafer; Remove BSG and alkali polish; Aluminum oxide deposition on the front and back of high-resistance silicon wafers; Silicon nitride deposition on the front and back sides of high square resistivity silicon wafers; Screen printing; After heat treatment, LECO treatment is used to obtain a high-resistance TOPCON battery;.

10. A high square resistance TOPCON battery, characterized in that: The battery is prepared by the TOPCON battery preparation method based on LECO technology as described in claim 9.

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