Junction field effect transistor compatible with BCD platform and preparation method thereof

Abstract

The invention provides a junction field effect transistor compatible with a BCD platform and a preparation method thereof, and the preparation method comprises the steps: etching a second grid electrode of an LDMOS device region to open a part of the surface of a second drift region, etching a middle region of a first grid electrode of a JFET device region to form a first opening, opening a part of the surface of a first drift region, and forming a second opening; a first body region is then formed in the first drift region at the bottom of the first opening of the JFET device region through an ion implantation process. According to the invention, a new photomask does not need to be additionally added in the process of forming the first body region, and the middle region of the first gate, which is subsequently injected into the first body region, of the JFET device region is synchronously opened in the process of etching the second gate of the LDMOS device region and opening part of the surface of the second drift region, so that the photomask for independently opening the middle region of the first gate is saved; the preparation process is simplified, and the cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a junction field effect transistor compatible with a BCD platform and a preparation method thereof. Background Art

[0002] At present, in the process of preparing Junction Field-Effect Transistor (JEFT) based on BCD (Bipolar-CMOS-DMOS) platform, it is conventionally necessary to add a mask to perform channel injection of JFET transistor separately, but this increases the wafer flow, resulting in a more complicated preparation process and also increases the production cost.

[0003] In addition, in the current process of preparing junction field effect transistors based on the BCD platform, taking N-JFET as an example, compared with the ion implantation area obtained by the conventional JFET channel implantation with a mask added separately, the N-type drift region of the junction field effect transistor is still relatively concentrated, and it is difficult to turn off by source / drain (S / D) ion implantation (P-plus / P+ / heavily doped region), and the channel turn-off voltage Vt of the N-JFET may be greater than 10V. Summary of the invention

[0004] The present application provides a junction field effect transistor compatible with a BCD platform and a preparation method thereof, which can solve the problem that a traditional preparation method of a junction field effect transistor compatible with a BCD platform requires an additional photomask, resulting in increased costs.

[0005] On the one hand, an embodiment of the present application provides a method for preparing a junction field effect transistor compatible with a BCD platform, comprising:

[0006] Providing a substrate, wherein the substrate at least comprises a JFET device region and an LDMOS device region;

[0007] Performing multiple ion implantation processes on the substrate to form a first buried layer on the substrate surface of the JFET device region, and forming a second buried layer and a ring-shaped buried layer surrounding the second buried layer on the substrate surface of the LDMOS device region;

[0008] forming an epitaxial layer, wherein the epitaxial layer covers the first buried layer of the JFET device region and the second buried layer and the annular buried layer of the LDMOS device region;

[0009] forming a plurality of shallow trench isolation structures spaced apart from each other in the epitaxial layers of the JFET device region and the LDMOS device region;

[0010] By multiple ion implantation processes, a first drift region and a first bottom implantation region are formed in the epitaxial layer of the JFET device region, and a second drift region and a second bottom implantation region are formed in the epitaxial layer of the LDMOS device region;

[0011] Through multiple ion implantation processes, a well region 1 of the first conductivity type is formed in the first drift region of the JFET device region, and a well region 2 of the second conductivity type is formed in the epitaxial layer outside the first drift region, and a well region 3 of the second conductivity type, a well region 4 of the first conductivity type, and a well region 5 of the second conductivity type are sequentially formed from inside to outside in the epitaxial layer outside the second drift region of the LDMOS device region;

[0012] Forming a polysilicon material layer, wherein the polysilicon material layer covers the epitaxial layer of the JFET device region and the epitaxial layer of the LDMOS device region;

[0013] Etching the polysilicon material layer to obtain a first gate of the JFET device region and a second gate of the LDMOS device region;

[0014] Etching a middle region of the first gate of the JFET device region to form a first opening, opening a portion of the surface of the first drift region, and etching a middle region of the second gate of the LDMOS device region to form a second opening, opening a portion of the surface of the second drift region;

[0015] Through multiple ion implantation processes, a first body region is formed in a first drift region at a first opening bottom of the JFET device region, and a second body region is formed in a second drift region at a second opening bottom of the LDMOS device region.

[0016] Optionally, in the method for preparing a junction field effect transistor compatible with the BCD platform, after forming the first body region and the second body region, the method for preparing a junction field effect transistor compatible with the BCD platform further includes:

[0017] Through multiple ion implantation processes, a first heavily doped region is formed in the first body region of the JFET device region, a second heavily doped region is formed in the well region one of the first conductivity type, a third heavily doped region is formed in the well region two of the second conductivity type, and a fourth heavily doped region is formed in the second body region of the LDMOS device region, a fifth heavily doped region is formed in the second drift region, a sixth heavily doped region is formed in the well region four of the first conductivity type, and a seventh heavily doped region is formed in the well region five of the second conductivity type.

[0018] Optionally, in the method for preparing a junction field effect transistor compatible with the BCD platform, after forming a well region 1 of the first conductivity type, a well region 2 of the second conductivity type, a well region 3 of the second conductivity type, a well region 4 of the first conductivity type, and a well region 5 of the second conductivity type, and before forming a polysilicon material layer, the method for preparing a junction field effect transistor compatible with the BCD platform further includes:

[0019] A gate oxide layer is formed, wherein the gate oxide layer covers a portion of the surface of the second drift region of the LDMOS device region.

[0020] Optionally, in the method for preparing a junction field effect transistor compatible with the BCD platform, the well region one of the first conductivity type, the well region two of the second conductivity type, the well region three of the second conductivity type, the well region four of the first conductivity type and the well region five of the second conductivity type are all ring-shaped.

[0021] Optionally, in the method for preparing a junction field effect transistor compatible with the BCD platform, the first conductivity type is N-type; and the second conductivity type is P-type.

[0022] Optionally, in the method for preparing a junction field effect transistor compatible with the BCD platform, the conductivity type of the doped ions in the first buried layer is P type; the conductivity type of the doped ions in the second buried layer is N type; the conductivity type of the doped ions in the annular buried layer is P type; the conductivity type of the doped ions in the first drift region is N type; the conductivity type of the doped ions in the first bottom injection region is P type; the conductivity type of the doped ions in the second drift region is N type; the conductivity type of the doped ions in the second bottom injection region is P type; the conductivity type of the doped ions in the first body region is P type; and the conductivity type of the doped ions in the second body region is P type.

[0023] Optionally, in the method for preparing a junction field effect transistor compatible with the BCD platform, the conductivity type of the doped ions in the first heavily doped region is P type; the conductivity type of the doped ions in the second heavily doped region is N type; the conductivity type of the doped ions in the third heavily doped region is P type; the conductivity type of the doped ions in the fourth heavily doped region is P&N type; the conductivity type of the doped ions in the fifth heavily doped region is N type; the conductivity type of the doped ions in the sixth heavily doped region is N type; and the conductivity type of the doped ions in the seventh heavily doped region is P type.

[0024] On the other hand, the embodiment of the present application further provides a junction field effect transistor compatible with the BCD platform, including:

[0025] A substrate, wherein the substrate at least comprises a JFET device region and an LDMOS device region;

[0026] a first buried layer, wherein the first buried layer is located on a surface of the substrate of the JFET device region;

[0027] a second buried layer and an annular buried layer, wherein the second buried layer is located on the surface of the substrate in the LDMOS device region to form a second buried layer, and the annular buried layer is arranged around the second buried layer;

[0028] An epitaxial layer, wherein the epitaxial layer covers the first buried layer of the JFET device region and the second buried layer and the annular buried layer of the LDMOS device region;

[0029] A plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located in the epitaxial layers of the JFET device region and the LDMOS device region and are spaced apart from each other;

[0030] A first drift region and a first bottom injection region, wherein the first drift region and the first bottom injection region are both located in the epitaxial layer of the JFET device region, and the first bottom injection region is located at the bottom of the first drift region;

[0031] A second drift region and a second bottom injection region, wherein the second drift region and the second bottom injection region are both located in the epitaxial layer of the LDMOS device region, and the second bottom injection region is located at the bottom of the second drift region;

[0032] A well region 1 of a first conductivity type and a well region 2 of a second conductivity type, wherein the well region 1 of the first conductivity type is located in a first drift region of the JFET device region, and the well region 2 of the second conductivity type is located in an epitaxial layer outside the first drift region;

[0033] A well region three of the second conductivity type, a well region four of the first conductivity type, and a well region five of the second conductivity type, wherein the well region three of the second conductivity type, the well region four of the first conductivity type, and the well region five of the second conductivity type are all located in the epitaxial layer of the periphery of the second drift region of the LDMOS device region and are arranged sequentially from the inside to the outside;

[0034] A first gate, wherein the first gate is located on a first drift region of the JFET device region, wherein a first opening is formed in the middle of the first gate;

[0035] A second gate, the second gate is located on the second drift region of the LDMOS device region, wherein a second opening is formed in the middle of the second gate;

[0036] A first body region, the first body region is located in a first drift region at a bottom of a first opening of the JFET device region;

[0037] A second body region is located in a second drift region at a bottom of a second opening of the LDMOS device region.

[0038] The technical solution of this application has at least the following advantages:

[0039] The present application provides a junction field effect transistor compatible with a BCD platform and a preparation method thereof, wherein the preparation method is compatible with a 90nm BCD G3 platform, and while etching the second gate of the LDMOS device region to open a portion of the surface of the second drift region, etching the middle region of the first gate of the JFET device region to form a first opening, opening a portion of the surface of the first drift region, and then forming a first body region in the first drift region at the bottom of the first opening of the JFET device region through an ion implantation process. The present application does not require an additional new mask in the process of forming the first body region, and while etching the second gate of the LDMOS device region to open a portion of the surface of the second drift region, the middle region of the first gate of the JFET device region for subsequent first body region implantation is simultaneously opened, thereby saving the mask for opening the middle region of the first gate separately, simplifying the preparation process, and reducing costs.

[0040] In addition, the present application does not require an additional mask to form the first body region in the JFET device area. Compared with the traditional JFET preparation method based on the BCD platform, the preparation method of the present application can appropriately adjust the ion implantation dose of the doped ions in the first drift region of the JFET device area and the ion implantation dose of the first body region, making it relatively easier to shut down by the source / drain end, thereby appropriately reducing the channel turn-off voltage Vt of the JFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1-Figure 6 It is a schematic diagram of a semiconductor structure in each process step of preparing a junction field effect transistor compatible with a BCD platform according to an embodiment of the present invention;

[0043] The reference numerals are described as follows:

[0044] 10-substrate, 11-first buried layer, 12-second buried layer, 13-annular buried layer, 20-epitaxial layer, 21-shallow trench isolation structure one, 22-shallow trench isolation structure two, 23-first drift region, 24-first bottom injection region, 25-second drift region, 26-second bottom injection region, 31-well region two of the second conductivity type, 32-well region one of the first conductivity type, 33-well region three of the second conductivity type, 34-well region four of the first conductivity type, 35-well region five of the second conductivity type, 40-gate oxide layer, 50-polysilicon material layer, 51-first gate, 52-second gate, 61-first opening, 62-second opening, 71-first body region, 72-second body region, 81-first heavily doped region, 82-second heavily doped region, 83-third heavily doped region, 84-fourth heavily doped region, 85-fifth heavily doped region, 86-sixth heavily doped region, 87-seventh heavily doped region. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0046] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0047] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0048] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0049] The present application provides a method for preparing a junction field effect transistor compatible with a BCD platform, comprising:

[0050] First, refer to Figure 1 , Figure 1 It is a schematic diagram of a semiconductor structure after a shallow trench isolation structure is formed according to an embodiment of the present application. A substrate 10 is provided. The substrate 10 at least includes a JFET device region and an LDMOS device region.

[0051] Then, continue to refer to Figure 1 The substrate 10 is subjected to multiple ion implantation processes to form a first buried layer 11 on the surface of the substrate in the JFET device region, and a second buried layer 12 and a ring-shaped buried layer 13 surrounding the second buried layer 12 are formed on the surface of the substrate 10 in the LDMOS device region.

[0052] In this embodiment, the conductivity type of the doped ions in the first buried layer 11 is P type; the conductivity type of the doped ions in the second buried layer 12 is N type; and the conductivity type of the doped ions in the annular buried layer 13 is P type.

[0053] Next, continue to refer to Figure 1 , forming an epitaxial layer 20, wherein the epitaxial layer 20 covers the first buried layer 11 of the JFET device region and the second buried layer 12 and the annular buried layer 13 of the LDMOS device region.

[0054] For further information, please refer to Figure 1 A plurality of shallow trench isolation structures 1 21 spaced apart from each other are formed in the epitaxial layer 20 of the JFET device region, and a plurality of shallow trench isolation structures 2 22 spaced apart from each other are formed in the epitaxial layer 20 of the LDMOS device region. Specifically, all the shallow trench isolation structures 1 21 and all the shallow trench isolation structures 2 22 are ring-shaped.

[0055] Next, refer to Figure 2 , Figure 2 It is a schematic diagram of the semiconductor structure after the first drift region and the first bottom injection region and the second drift region and the second bottom injection region are formed in an embodiment of the present application. Through multiple ion implantation processes, a first drift region 23 and a first bottom injection region 24 located at the bottom of the first drift region 23 are formed in the epitaxial layer 20 of the JFET device region, and a second drift region 25 and a second bottom injection region 26 located at the bottom of the second drift region 25 are formed in the epitaxial layer 20 of the LDMOS device region.

[0056] In this embodiment, the conductivity type of the doped ions in the first drift region 23 is N-type; the conductivity type of the doped ions in the first bottom injection region 24 is P-type; the conductivity type of the doped ions in the second drift region 25 is N-type; and the conductivity type of the doped ions in the second bottom injection region 26 is P-type.

[0057] For further reference, Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after forming a well region one of the first conductivity type, a well region two of the second conductivity type, a well region three of the second conductivity type, a well region four of the first conductivity type and a well region five of the second conductivity type in an embodiment of the present application. Through multiple ion implantation processes, a well region one 32 of the first conductivity type is formed in the first drift region 23 of the JFET device region, and a well region two 31 of the second conductivity type is formed in the epitaxial layer 20 outside the first drift region 23. In addition, a well region three 33 of the second conductivity type, a well region four 34 of the first conductivity type and a well region five 35 of the second conductivity type are sequentially formed from the inside to the outside in the epitaxial layer 20 outside the second drift region 25 of the LDMOS device region.

[0058] In this embodiment, the first conductivity type is N type; and the second conductivity type is P type.

[0059] Preferably, the well region one 32 of the first conductivity type, the well region two 31 of the second conductivity type, the well region three 33 of the second conductivity type, the well region four 34 of the first conductivity type and the well region five 35 of the second conductivity type are all ring-shaped.

[0060] For further reference, Figure 4 , Figure 4 1 is a schematic diagram of a semiconductor structure after forming a first gate and a second gate in an embodiment of the present application, wherein a gate oxide layer 40 is formed, and the gate oxide layer 40 covers a portion of the surface of the second drift region 25 of the LDMOS device region.

[0061] In this embodiment, a whole gate oxide layer can be first deposited on the surface of the epitaxial layer of the LDMOS device region by a CVD process, and then the outer gate oxide layer 40 is etched away by a photolithography process, an etching process, etc., leaving the gate oxide layer 40 on a partial surface (middle area) of the second drift region 25 of the LDMOS device region.

[0062] Next, continue to refer to Figure 4 , forming a polysilicon material layer 50, wherein the polysilicon material layer 50 covers the epitaxial layer 20 of the JFET device region and the gate oxide layer 40 of the LDMOS device region.

[0063] In this embodiment, a whole layer of polysilicon material layer 50 may be deposited on the surface of the epitaxial layer in the JFET device region and the LDMOS device region by using a CVD process.

[0064] For further information, please refer to Figure 4 , etching the polysilicon material layer 50 to obtain a first gate 51 of the JFET device region and a second gate 52 of the LDMOS device region.

[0065] In this embodiment, the polysilicon material layer 50 may be etched by a dry etching process to obtain a first gate 51 of the JFET device region and a second gate 52 of the LDMOS device region.

[0066] Next, refer to Figure 5 , Figure 5 It is a schematic diagram of the semiconductor structure after the first body region and the second body region are formed in an embodiment of the present application, the middle area of ​​the first gate 51 of the JFET device area is etched to form a first opening 61, opening a portion of the surface of the first drift region 23, and the middle area of ​​the second gate 52 of the LDMOS device area is etched to form a second opening 62, opening a portion of the surface of the second drift region 25.

[0067] Finally, continue to refer to Figure 5 Through multiple ion implantation processes, a first body region 71 is formed in the first drift region 23 at the bottom of the first opening 61 of the JFET device region, and a second body region 72 is formed in the second drift region 25 at the bottom of the second opening 62 of the LDMOS device region.

[0068] In this embodiment, the conductivity type of the doped ions in the first body region 71 is P type; the conductivity type of the doped ions in the second body region 72 is P type.

[0069] In the present application, there is no need to add a new mask in the process of forming the first body region of the JFET device region. It is only necessary to simultaneously open the first gate middle region of the JFET device region for subsequent first body region injection during the process of etching the second gate of the LDMOS device region to open part of the surface of the second drift region. Subsequently, through the ion implantation process, the first body region is formed in the first drift region at the bottom of the first opening of the JFET device region, thereby saving the mask for separately opening the first gate middle region, that is, saving a mask for etching the polysilicon material layer above the first body region, simplifying the preparation process and reducing costs.

[0070] For further reference, Figure 6 , Figure 6It is a schematic diagram of the semiconductor structure after forming the first heavily doped region, the second heavily doped region, the third heavily doped region, the fourth heavily doped region, the fifth heavily doped region, the sixth heavily doped region and the seventh heavily doped region in an embodiment of the present application. After forming the first body region 71 and the second body region 72, the preparation method of the junction field effect transistor compatible with the BCD platform may also include: through multiple ion implantation processes, forming a first heavily doped region 81 in the first body region 71 of the JFET device region, forming a second heavily doped region 82 in the well region 1 32 of the first conductivity type, forming a third heavily doped region 83 in the well region 2 31 of the second conductivity type, and forming a fourth heavily doped region 84 in the second body region 72 of the LDMOS device region, forming a fifth heavily doped region 85 in the second drift region 25, forming a sixth heavily doped region 86 in the well region 4 34 of the first conductivity type, and forming a seventh heavily doped region 87 in the well region 5 35 of the second conductivity type.

[0071] In this embodiment, the conductivity type of the doped ions in the first heavily doped region 81 is P type; the conductivity type of the doped ions in the second heavily doped region 82 is N type; the conductivity type of the doped ions in the third heavily doped region 83 is P type; the conductivity type of the doped ions in the fourth heavily doped region 84 is P&N type; the conductivity type of the doped ions in the fifth heavily doped region 85 is N type; the conductivity type of the doped ions in the sixth heavily doped region 86 is N type; and the conductivity type of the doped ions in the seventh heavily doped region 87 is P type.

[0072] Based on the same inventive concept, the embodiment of the present application also provides a junction field effect transistor compatible with the BCD platform, referring to Figure 5 , the junction field effect transistor compatible with the BCD platform includes:

[0073] A substrate 10, wherein the substrate 10 at least includes a JFET device region and an LDMOS device region;

[0074] A first buried layer 11, wherein the first buried layer 11 is located on the surface of the substrate 10 in the JFET device region;

[0075] A second buried layer 12 and an annular buried layer 13, wherein the second buried layer 12 is located on the surface of the substrate 10 in the LDMOS device region to form the second buried layer 12, and the annular buried layer 13 is disposed around the second buried layer 12;

[0076] An epitaxial layer 20, wherein the epitaxial layer 20 covers the first buried layer 11 of the JFET device region and the second buried layer 12 and the ring buried layer 13 of the LDMOS device region;

[0077] A plurality of shallow trench isolation structures 1 21 and a plurality of shallow trench isolation structures 22, wherein the shallow trench isolation structures 1 21 are located in the epitaxial layer 20 of the JFET device region and are spaced apart from each other; and the shallow trench isolation structures 22 are located in the epitaxial layer of the LDMOS device region and are spaced apart from each other;

[0078] A first drift region 23 and a first bottom injection region 24, wherein the first drift region 23 and the first bottom injection region 24 are both located in the epitaxial layer 20 of the JFET device region, and the first bottom injection region 24 is located at the bottom of the first drift region 23;

[0079] A second drift region 25 and a second bottom injection region 26, wherein the second drift region 25 and the second bottom injection region 26 are both located in the epitaxial layer 20 of the LDMOS device region, and the second bottom injection region 26 is located at the bottom of the second drift region 25;

[0080] A well region 1 32 of a first conductivity type and a well region 2 31 of a second conductivity type, wherein the well region 1 32 of the first conductivity type is located in the first drift region 23 of the JFET device region, and the well region 2 31 of the second conductivity type is located in the epitaxial layer 20 outside the first drift region 23;

[0081] A well region 33 of the second conductivity type, a well region 4 of the first conductivity type, a well region 34 of the second conductivity type, and a well region 5 of the second conductivity type, wherein the well region 33 of the second conductivity type, the well region 4 of the first conductivity type, and the well region 5 of the second conductivity type are all located in the epitaxial layer 20 at the periphery of the second drift region 25 of the LDMOS device region and are arranged sequentially from the inside to the outside;

[0082] A first gate 51, wherein the first gate 51 is located on the first drift region 23 of the JFET device region, wherein a first opening 61 is formed in the middle of the first gate 51;

[0083] A second gate 52, wherein the second gate 52 is located on the second drift region 25 of the LDMOS device region, wherein a second opening 62 is formed in the middle of the second gate 52;

[0084] A first body region 71, wherein the first body region 71 is located in the first drift region 23 at the bottom of the first opening 61 of the JFET device region;

[0085] The second body region 72 is located in the second drift region 25 at the bottom of the second opening 62 of the LDMOS device region.

[0086] For further reference, Figure 6, the junction field effect transistor compatible with the BCD platform also includes: a first heavily doped region 81, a second heavily doped region 82, a third heavily doped region 83, a fourth heavily doped region 84, a fifth heavily doped region 85, a sixth heavily doped region 86 and a seventh heavily doped region 87, wherein the first heavily doped region 81 is located in the first body region 71 of the JFET device region, the second heavily doped region 82 is located in the well region one 32 of the first conductivity type, the third heavily doped region 83 is located in the well region two 31 of the second conductivity type, the fourth heavily doped region 84 is located in the second body region 72 of the LDMOS device region, the fifth heavily doped region 85 is located in the second drift region 25, the sixth heavily doped region 86 is located in the well region four 34 of the first conductivity type, and the seventh heavily doped region 87 is located in the well region five 35 of the second conductivity type.

[0087] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing a junction field effect transistor compatible with a BCD platform, characterized in that: include: Providing a substrate, wherein the substrate at least comprises a JFET device region and an LDMOS device region; Performing multiple ion implantation processes on the substrate to form a first buried layer on the substrate surface of the JFET device region, and forming a second buried layer and a ring-shaped buried layer surrounding the second buried layer on the substrate surface of the LDMOS device region; forming an epitaxial layer, wherein the epitaxial layer covers the first buried layer of the JFET device region and the second buried layer and the annular buried layer of the LDMOS device region; forming a plurality of shallow trench isolation structures spaced apart from each other in the epitaxial layers of the JFET device region and the LDMOS device region; By multiple ion implantation processes, a first drift region and a first bottom implantation region are formed in the epitaxial layer of the JFET device region, and a second drift region and a second bottom implantation region are formed in the epitaxial layer of the LDMOS device region; Through multiple ion implantation processes, a well region 1 of the first conductivity type is formed in the first drift region of the JFET device region, and a well region 2 of the second conductivity type is formed in the epitaxial layer outside the first drift region, and a well region 3 of the second conductivity type, a well region 4 of the first conductivity type, and a well region 5 of the second conductivity type are sequentially formed from inside to outside in the epitaxial layer outside the second drift region of the LDMOS device region; Forming a polysilicon material layer, wherein the polysilicon material layer covers the epitaxial layer of the JFET device region and the epitaxial layer of the LDMOS device region; Etching the polysilicon material layer to obtain a first gate of the JFET device region and a second gate of the LDMOS device region; Etching a middle region of the first gate of the JFET device region to form a first opening, opening a portion of the surface of the first drift region, and etching a middle region of the second gate of the LDMOS device region to form a second opening, opening a portion of the surface of the second drift region; Through multiple ion implantation processes, a first body region is formed in a first drift region at a first opening bottom of the JFET device region, and a second body region is formed in a second drift region at a second opening bottom of the LDMOS device region.

2. The method for preparing a junction field effect transistor compatible with the BCD platform according to claim 1, characterized in that: After forming the first body region and the second body region, the method for preparing the junction field effect transistor compatible with the BCD platform further includes: Through multiple ion implantation processes, a first heavily doped region is formed in the first body region of the JFET device region, a second heavily doped region is formed in the well region one of the first conductivity type, a third heavily doped region is formed in the well region two of the second conductivity type, and a fourth heavily doped region is formed in the second body region of the LDMOS device region, a fifth heavily doped region is formed in the second drift region, a sixth heavily doped region is formed in the well region four of the first conductivity type, and a seventh heavily doped region is formed in the well region five of the second conductivity type.

3. The method for preparing a junction field effect transistor compatible with the BCD platform according to claim 1, characterized in that: After forming a well region 1 of the first conductivity type, a well region 2 of the second conductivity type, a well region 3 of the second conductivity type, a well region 4 of the first conductivity type, and a well region 5 of the second conductivity type, and before forming a polysilicon material layer, the method for preparing a junction field effect transistor compatible with the BCD platform further includes: A gate oxide layer is formed, wherein the gate oxide layer covers a portion of the surface of the second drift region of the LDMOS device region.

4. The method for preparing a junction field effect transistor compatible with a BCD platform according to claim 1, characterized in that: The first conductive type well region 1, the second conductive type well region 2, the second conductive type well region 3, the first conductive type well region 4 and the second conductive type well region 5 are all ring-shaped.

5. The method for preparing a junction field effect transistor compatible with the BCD platform according to claim 1, characterized in that: The first conductivity type is N type; the second conductivity type is P type.

6. The method for preparing a junction field effect transistor compatible with a BCD platform according to claim 1, characterized in that: The conductivity type of the doped ions in the first buried layer is P type; the conductivity type of the doped ions in the second buried layer is N type; the conductivity type of the doped ions in the annular buried layer is P type; the conductivity type of the doped ions in the first drift region is N type; the conductivity type of the doped ions in the first bottom injection region is P type; the conductivity type of the doped ions in the second drift region is N type; the conductivity type of the doped ions in the second bottom injection region is P type; the conductivity type of the doped ions in the first body region is P type; the conductivity type of the doped ions in the second body region is P type.

7. The method for preparing a junction field effect transistor compatible with a BCD platform according to claim 2, characterized in that: The conductivity type of the doped ions in the first heavily doped region is P type; the conductivity type of the doped ions in the second heavily doped region is N type; the conductivity type of the doped ions in the third heavily doped region is P type; the conductivity type of the doped ions in the fourth heavily doped region is P&N type; the conductivity type of the doped ions in the fifth heavily doped region is N type; The conductivity type of the doped ions in the sixth heavily doped region is N-type; the conductivity type of the doped ions in the seventh heavily doped region is P-type.

8. A junction field effect transistor compatible with the BCD platform, characterized in that: include: A substrate, wherein the substrate at least comprises a JFET device region and an LDMOS device region; a first buried layer, wherein the first buried layer is located on a surface of the substrate of the JFET device region; a second buried layer and an annular buried layer, wherein the second buried layer is located on the surface of the substrate in the LDMOS device region to form a second buried layer, and the annular buried layer is arranged around the second buried layer; An epitaxial layer, wherein the epitaxial layer covers the first buried layer of the JFET device region and the second buried layer and the annular buried layer of the LDMOS device region; A plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located in the epitaxial layers of the JFET device region and the LDMOS device region and are spaced apart from each other; A first drift region and a first bottom injection region, wherein the first drift region and the first bottom injection region are both located in the epitaxial layer of the JFET device region, and the first bottom injection region is located at the bottom of the first drift region; A second drift region and a second bottom injection region, wherein the second drift region and the second bottom injection region are both located in the epitaxial layer of the LDMOS device region, and the second bottom injection region is located at the bottom of the second drift region; A well region 1 of a first conductivity type and a well region 2 of a second conductivity type, wherein the well region 1 of the first conductivity type is located in a first drift region of the JFET device region, and the well region 2 of the second conductivity type is located in an epitaxial layer outside the first drift region; A well region three of the second conductivity type, a well region four of the first conductivity type, and a well region five of the second conductivity type, wherein the well region three of the second conductivity type, the well region four of the first conductivity type, and the well region five of the second conductivity type are all located in the epitaxial layer of the periphery of the second drift region of the LDMOS device region and are arranged sequentially from the inside to the outside; A first gate, wherein the first gate is located on a first drift region of the JFET device region, wherein a first opening is formed in the middle of the first gate; a second gate, wherein the second gate is located on a second drift region of the LDMOS device region, wherein A second opening is formed in the middle of the second gate; A first body region, the first body region is located in a first drift region at a bottom of a first opening of the JFET device region; A second body region is located in a second drift region at a bottom of a second opening of the LDMOS device region.

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