Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a wafer; forming a dielectric layer above the wafer and forming a first groove in the dielectric layer, wherein the first groove exposes at least one part of the wafer; a first metal layer covering the inner wall of the first groove is formed on the whole surface above the dielectric layer, so that the filling environment of gate metal is effectively improved, and the contact coverage between the gate metal and a nearby area is good; forming first gate metal filled in the first groove above the first metal layer by adopting a stripping process; wet etching is carried out on the first metal layer to obtain second gate metal which is located below the first gate metal, the vertical projection of the second gate metal falls into the vertical projection range of the first gate metal, and gate metal is formed. On the other hand, the gate metal with the specific morphology is obtained based on the lateral corrosion effect of the gate metal, and the parasitic capacitance is further reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit devices and manufacturing, and relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] GaN HEMT (High Electron Mobility Transistor) is a semiconductor device made of wide bandgap semiconductor material gallium nitride (GaN). It is widely used in high-frequency amplifiers, oscillators and fully controlled power electronic devices due to its excellent electron mobility. In its structure, the structure of the gate is crucial to the performance of the device. The gate not only controls the conductive state of the device, but also affects the threshold voltage, gate swing and long-term stability of the device.

[0003] At present, gate metal is usually realized by using photolithography technology and development process in the gate groove. However, during the photolithography process, photoresist will be filled into the gate groove, and when the photoresist is developed, the developer will also enter the gate groove. The chemical components in the developer may react with the inner wall of the gate groove to undergo oxidation and change the morphology of the inner wall of the gate groove. In addition, during the cleaning process after the photolithography process is completed, the cleaning cleanliness is affected due to the limitations of the internal area of ​​the gate groove. The photoresist residue and the developer residue adhere to the inside of the gate groove and cause pollution to the internal area of ​​the gate groove, which affects the subsequent filling environment of the gate metal, and ultimately affects the electrical characteristics of the gate metal, thereby degrading the performance of the device.

[0004] Therefore, how to provide a semiconductor device and a manufacturing method thereof to achieve good filling of gate metal in the gate groove and improve the working performance of the device has become an important technical problem that needs to be solved urgently by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem in the prior art that the contamination in the inner area of ​​the gate groove caused by the photolithography process affects the gate metal filling environment and deteriorates the device performance.

[0007] To achieve the above object and other related objects, the present invention provides a method for manufacturing a semiconductor device, comprising the following steps:

[0008] providing a wafer;

[0009] forming a dielectric layer above the wafer and forming a first groove in the dielectric layer, wherein the first groove exposes at least a portion of the wafer;

[0010] forming a first metal layer entirely above the dielectric layer, wherein the first metal layer also covers an inner wall of the first groove;

[0011] forming a first gate metal on the first metal layer by a lift-off process, wherein the first gate metal is also filled into the first groove;

[0012] The first metal layer is wet-etched and a portion of the first metal layer located below the first gate metal is retained as a second gate metal, a vertical projection of the second gate metal falls within a vertical projection range of the first gate metal, and the first gate metal and the second gate metal constitute a gate metal.

[0013] Optionally, forming a first gate metal on the first metal layer by a lift-off process comprises the following steps:

[0014] forming a photoresist layer above the first metal layer;

[0015] Patterning the photoresist layer to form a second groove, wherein the width of the second groove is greater than the width of the first groove and the second groove reveals the first groove covered with the first metal layer;

[0016] forming a second metal layer on the photoresist layer, wherein the second metal layer is also filled into the second groove and the first groove covered with the first metal layer;

[0017] The photoresist layer is stripped to remove the portion of the second metal layer located above the photoresist layer, and the remaining portion of the second metal layer is used as the first gate metal.

[0018] Optionally, the method for forming the first metal layer includes at least one of atomic layer deposition and magnetron sputtering, the material of the first metal layer includes at least one of Ni, Ti, TiN, Al and W, and the thickness range of the first metal layer is less than or equal to 10nm; the method for forming the second metal layer includes at least one of atomic layer deposition and magnetron sputtering, and the material of the second metal layer includes at least one of Pt, Au, Al, Ti and Ta.

[0019] Optionally, the wafer includes a substrate and an epitaxial layer located on the substrate, wherein the material of the substrate includes at least one of silicon, silicon carbide, sapphire and diamond, the epitaxial layer includes a transition layer, a channel layer and a barrier layer stacked in sequence from bottom to top, and the transition layer includes at least one of an AlN nucleation layer, a multi-quantum well buffer layer, an Al composition gradient buffer layer and a GaN buffer layer.

[0020] Optionally, the material of the dielectric layer includes at least one of SiN, SiO2, SiON, AlN and Al2O3, and the method for forming the dielectric layer includes at least one of plasma enhanced chemical vapor deposition, physical vapor deposition and atomic layer deposition.

[0021] Optionally, the manufacturing method further includes the step of forming a source metal and a drain metal above the wafer, wherein the source metal and the drain metal are embedded in the dielectric layer and arranged on both sides of the gate metal.

[0022] Optionally, forming a dielectric layer above the wafer comprises the following steps:

[0023] forming a first dielectric layer above the wafer;

[0024] forming a source contact hole and a drain contact hole in the first dielectric layer, wherein the source contact hole and the drain contact hole respectively expose a portion of the wafer;

[0025] forming a metal material layer above the first dielectric layer, wherein the metal material layer is also filled into the source contact hole and the drain contact hole;

[0026] Etching the metal material layer to obtain a source metal and a drain metal that are separately arranged, wherein the source metal is at least filled in the source contact hole, and the drain metal is at least filled in the drain contact hole;

[0027] A second dielectric layer is formed above the first dielectric layer, wherein the second dielectric layer covers the source metal and the drain metal to form a dielectric layer together with the first dielectric layer.

[0028] Optionally, the manufacturing method further includes the step of forming an interconnect metal layer above the wafer, wherein the interconnect metal layer is electrically connected to the source metal, the drain metal and the gate metal respectively.

[0029] The present invention also provides a semiconductor device, comprising:

[0030] Wafer;

[0031] a dielectric layer, located above the wafer, and having a first groove formed in the dielectric layer, wherein the first groove exposes at least a portion of the wafer;

[0032] A gate metal is located above the dielectric layer and filled into the first groove, the gate metal includes a second gate metal and a first gate metal located above the second gate metal, wherein the second gate metal covers the inner wall of the first groove, the first gate metal fills into the first groove, and the vertical projection of the second gate metal falls within the vertical projection range of the first gate metal.

[0033] Optionally, the formation method of the first metal layer includes at least one of atomic layer deposition and magnetron sputtering, the material of the first metal layer includes at least one of Ni, Ti, TiN, Al and W, and the thickness range of the first metal layer is less than or equal to 10nm.

[0034] As described above, in the manufacturing method of the semiconductor device of the present invention, in the manufacturing process of the gate metal, after forming the first groove for filling the gate metal, the method of depositing the first metal layer on the whole surface is adopted, so that the regional contact coverage between the gate metal and the epitaxial layer and the dielectric layer is good, which can avoid the problem that the photolithography process affects the gate metal filling environment in the traditional gate metal manufacturing process, and effectively improve the performance of the device, and then the first metal layer is etched by a wet etching process to obtain the second gate metal, which avoids the dry etching causing loss to the dielectric layer or the presence of metal debris residue near the second gate metal affecting the performance of the device, and improves the electrical performance and reliability of the device, and also based on the lateral corrosion effect of the wet etching, the vertical projection of the second gate metal falls within the vertical projection range of the first gate metal, further reducing the parasitic capacitance, and achieving a significant improvement in the performance of the device. In the semiconductor device of the present invention, in the gate metal structure, the vertical projection of the second gate metal falls within the vertical projection range of the first gate metal, effectively reducing the parasitic capacitance of the device, thereby improving the reliability and stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The flowchart is a step chart of a method for manufacturing a semiconductor device of the present invention.

[0036] Figure 2 It is a partial cross-sectional schematic diagram of a wafer in the method for manufacturing a semiconductor device of the present invention.

[0037] Figure 3 It is a partial cross-sectional schematic diagram of the structure obtained after forming the source contact hole and the drain contact hole in the method for manufacturing the semiconductor device of the present invention.

[0038] Figure 4 It is a partial cross-sectional schematic diagram of the structure obtained after forming the source metal and the drain metal in the method for manufacturing the semiconductor device of the present invention.

[0039] Figure 5It is a schematic partial cross-sectional view of a structure obtained after forming a second dielectric layer in the method for manufacturing a semiconductor device of the present invention.

[0040] Figure 6 It is a schematic partial cross-sectional view of a structure obtained after forming a first groove in the method for manufacturing a semiconductor device of the present invention.

[0041] Figure 7 It is a schematic partial cross-sectional view of a structure obtained after forming a first metal layer in the method for manufacturing a semiconductor device of the present invention.

[0042] Figure 8 It is a schematic partial cross-sectional view of a structure obtained after forming a second groove in the method for manufacturing a semiconductor device of the present invention.

[0043] Fig. 9 It is a schematic partial cross-sectional view of a structure obtained after forming a second metal layer in the method for manufacturing a semiconductor device of the present invention.

[0044] Fig.10 It is a schematic partial cross-sectional view of a structure obtained after forming a first gate metal in the method for manufacturing a semiconductor device of the present invention.

[0045] Fig.11 It is a schematic partial cross-sectional view of a structure obtained after forming a second gate metal in the method for manufacturing a semiconductor device of the present invention.

[0046] Fig.12 It is a schematic partial cross-sectional view of a structure obtained after forming an interconnect metal layer in the method for manufacturing a semiconductor device of the present invention.

[0047] Fig.13 The diagram shows a cross-sectional view of the region near the gate metal after dry etching the first metal layer.

[0048] Description of Reference Numerals

[0049] 10 Wafer

[0050] 11 Substrate

[0051] 12 Epitaxial layer

[0052] 121 Transition Layer

[0053] 122 channel layer

[0054] 123 Barrier layer

[0055] 20 Dielectric layer

[0056] 21 First dielectric layer

[0057] 211 Source contact hole

[0058] 212 Drain contact hole

[0059] 22 Second dielectric layer

[0060] 201 First Groove

[0061] 31 Source Metal

[0062] 32 Drain Metal

[0063] 40 First metal layer

[0064] 41 Second Gate Metal

[0065] 50 Photoresist layer

[0066] 501 Second Groove

[0067] 60 Second metal layer

[0068] 61 First Gate Metal

[0069] 70 Gate Metal

[0070] 80 Third dielectric layer

[0071] 90 Interconnect Metal Layer

[0072] Steps S1 to S5 DETAILED DESCRIPTION

[0073] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0074] See also Figures 1 to 13 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0075] Embodiment 1

[0076] This embodiment provides a method for manufacturing a semiconductor device. Figure 1 , which is a flowchart of the steps of the production method, comprising the following steps:

[0077] S1: providing a wafer;

[0078] S2: forming a dielectric layer above the wafer and forming a first groove in the dielectric layer, wherein the first groove exposes at least a portion of the wafer;

[0079] S3: forming a first metal layer on the entire surface of the dielectric layer, wherein the first metal layer also covers an inner wall of the first groove;

[0080] S4: forming a first gate metal on the first metal layer by a lift-off process, wherein the first gate metal is also filled into the first groove;

[0081] S5: wet-etching the first metal layer and retaining a portion of the first metal layer located below the first gate metal as a second gate metal, wherein a vertical projection of the second gate metal falls within a vertical projection range of the first gate metal, and the first gate metal and the second gate metal constitute a gate metal.

[0082] First, see Figure 2 , execute step S1 to provide a wafer 10.

[0083] As an example, the wafer 10 includes a substrate 11 and an epitaxial layer 12 located on the substrate 11, wherein the material of the substrate 11 includes at least one of silicon, silicon carbide, sapphire and diamond, and the epitaxial layer 12 includes a transition layer 121, a channel layer 122 and a barrier layer 123 stacked in sequence from bottom to top, and the transition layer 121 includes at least one of an AlN nucleation layer, a multi-quantum well buffer layer, an Al composition gradient buffer layer and a GaN buffer layer. This embodiment is introduced by taking the manufacture of a HEMT device as an example, and in other examples, it can also be used to manufacture other suitable semiconductor devices. At this time, the specific structure of the wafer 10 is adjusted based on actual conditions.

[0084] Then, see Figures 3 to 6 , executing step S2, forming a dielectric layer 20 above the wafer 10 and forming a first groove 201 in the dielectric layer 20, wherein the first groove 201 exposes at least a portion of the wafer 10 (such as Figure 6 shown).

[0085] As an example, the material of the dielectric layer 20 includes at least one of SiN, SiO2, SiON, AlN and Al2O3, and the formation method of the dielectric layer 20 includes at least one of plasma enhanced chemical vapor deposition, physical vapor deposition and atomic layer deposition.

[0086] As an example, Figures 3 to 5As shown, the manufacturing method also includes the step of forming a source metal 31 and a drain metal 32 on the wafer 10, wherein the source metal 31 and the drain metal 32 are embedded in the dielectric layer 20 and arranged on both sides of the gate metal 70 (please refer to Fig.11 ).

[0087] As an example, forming the dielectric layer 20 on the wafer 10 includes the following steps:

[0088] like Figure 3 As shown, a first dielectric layer 21 is formed above the wafer 10; a source contact hole 211 and a drain contact hole 212 are formed in the first dielectric layer 21, and the source contact hole 211 and the drain contact hole 212 respectively expose a portion of the wafer 10, and may only expose the upper surface of the wafer 10, or may extend into the upper surface layer of the wafer 10;

[0089] like Figure 4 As shown, a metal material layer (not shown) is formed above the first dielectric layer 21, and the metal material layer is also filled into the source contact hole 211 and the drain contact hole 212; the metal material layer is etched to obtain a source metal 31 and a drain metal 32 which are separately arranged, wherein the source metal 31 is at least filled into the source contact hole 211, and the drain metal 32 is at least filled into the drain contact hole 212. In this embodiment, the source metal 31 and the drain metal 32 both include a portion exposed above the first dielectric layer 21;

[0090] like Figure 5 As shown, a second dielectric layer 22 is formed on the first dielectric layer 21 , and the second dielectric layer 22 covers the source metal 31 and the drain metal 32 to form a dielectric layer 20 together with the first dielectric layer 21 .

[0091] As an example, after forming the source metal 31 and the drain metal 32, a high temperature diffusion annealing step is further included to form a good ohmic contact between the source metal 31 and the drain metal 32 and the wafer 10, and then, Figure 7 As shown, the first groove 201 is formed in the dielectric layer 20 to serve as a gate groove.

[0092] Then, see Figure 7 , executing step S3 , forming a first metal layer 40 on the entire surface of the dielectric layer 20 , wherein the first metal layer 40 also covers the inner wall of the first groove 201 .

[0093] As an example, the method for forming the first metal layer 40 includes at least one of atomic layer deposition and magnetron sputtering, the material of the first metal layer 40 includes at least one of Ni, Ti, TiN, Al and W, and the thickness range of the first metal layer 40 is less than or equal to 10nm, including but not limited to 4nm, 6nm and 8nm. In this embodiment, the atomic layer deposition (ALD) method is used to form a TiN layer as the first metal layer 40. Based on the relatively small thickness of the first metal layer 40, strict control is required to avoid adverse effects on device performance. The ALD method can accurately control the film thickness; at the same time, the first metal layer 40 needs to be filled in the first groove 201 and cover the inner wall (including the side wall and the bottom wall) of the first groove 201. Compared with other methods, the ALD method has better step coverage and is more suitable for forming the first metal layer 40.

[0094] Later, please refer to Figures 8 to 10 , executing step S4 , forming a first gate metal 61 on the first metal layer 40 by a lift-off process, and the first gate metal 61 is also filled into the first groove 201 .

[0095] As an example, forming the first gate metal 61 on the first metal layer 40 by using a lift-off process includes the following steps:

[0096] like Figure 8 As shown, a photoresist layer 50 is formed on the first metal layer 40, and the photoresist layer 50 is also filled into the first groove 201 covered with the first metal layer 40; the photoresist layer 50 is patterned to form a second groove 501, the width of the second groove 501 is greater than the width of the first groove 201, and the second groove 501 exposes the first groove 201 covered with the first metal layer 40;

[0097] like Fig. 9 As shown, a second metal layer 60 is formed on the photoresist layer 50, and the second metal layer 60 is also filled into the second groove 501 and the first groove 201 covered with the first metal layer 40;

[0098] like Fig.10 As shown, the photoresist layer 50 is stripped to remove the portion of the second metal layer 60 located above the photoresist layer 50, and the remaining portion of the second metal layer 60 is used as the first gate metal 61. It should be noted that the thickness of the photoresist layer 50 and the second metal layer 60 is set based on actual needs, and it is necessary to ensure that the second metal layer 60 completely fills the remaining space of the first groove 201 and also fills an appropriate amount of the bottom position of the second groove 501 so that the first gate metal 61 is in a "T" shape, thereby maintaining a small gate resistance.

[0099] As an example, a method of forming the second metal layer 60 includes at least one of an atomic layer deposition method and a magnetron sputtering method, and a material of the second metal layer 60 includes at least one of Pt, Au, Al, Ti, and Ta.

[0100] Next, see Fig.11 , execute step S5, wet-etch the first metal layer 40 and retain the portion of the first metal layer 40 located below the first gate metal 61 as the second gate metal 41, and the vertical projection of the second gate metal 41 falls within the vertical projection range of the first gate metal 61 (that is, there is a distance between the horizontally exposed end surface of the second gate metal 41 and the horizontally exposed end surface of the first gate metal 61, and the second gate metal 41 is retracted between the first gate metal 61 and the dielectric layer 20), and the first gate metal 61 and the second gate metal 41 constitute the gate metal 70.

[0101] Specifically, the manufacturing method of the present embodiment can achieve the following technical effects by first depositing the first metal layer 40 on the entire surface above the dielectric layer 20 during the process of manufacturing the gate metal 70, and then etching the first metal layer 40 by wet etching after forming the first gate metal 61 by a lift-off process to obtain the second gate metal 41 located below the first gate metal 61: when the gate metal 70 is manufactured in the gate groove by a conventional photolithography etching method, the photoresist and the developer will enter the gate groove (i.e., the first groove 201), causing pollution to the inner area of ​​the gate groove, and the cleaning cleanliness is limited due to the limitation of the inner area of ​​the gate groove, and the subsequent gate metal filling environment cannot be guaranteed, thereby affecting the performance of the device. However, by forming the first gate metal 61 after the first metal layer 40 is deposited on the entire surface of the present embodiment, the photolithography process pollution (including developer residues and photoresist residues, etc.) in the area where the gate metal 70 contacts the epitaxial layer 12 and the dielectric layer 20 can be avoided, thereby improving the adverse effects of the conventional method on the device performance. After forming the first gate metal 61, the first metal layer 40 is etched by wet etching to obtain the second gate metal 41. On the one hand, the dry etching process can avoid the loss of the dielectric layer 20 under the first metal layer 40 to ensure the electrical performance of the device. At the same time, please refer to Fig.13, which is a schematic diagram of the cross-sectional structure of the gate metal and the surrounding area after the first metal layer is dry-etched. If dry etching is used, metal debris will remain on the surface of the epitaxial layer near the gate metal 70 (that is, the etching is not thorough and some residues exist). The metal debris may be partially connected to the gate metal 70, resulting in a larger gate length of the device (corresponding to the gate size in the width direction described in this embodiment), thereby affecting the breakdown voltage of the device. At the same time, the parasitic capacitance is increased due to the reduced distance between the gate metal 70 and the source / drain metal, which affects the reliability of the device. In the second aspect, based on the first gate metal 61 being located on the first metal layer 40, On the one hand, this positional relationship enables the first gate metal 61 to shield the reserved part of the first metal layer 40, thereby saving a photolithography process; on the third hand, while removing a part of the first metal layer 40 by wet etching, the end face of the retained part of the first metal layer 40 (i.e., the second gate metal 41) in the horizontal direction is retracted under the first gate metal 61 (i.e., the vertical projection falls within the vertical projection range of the first gate metal 61) due to the lateral corrosion effect of the wet etching itself, which can further reduce the parasitic capacitance between the gate metal 70 and the source metal 31 (or the drain metal 32), thereby ensuring the response speed and working stability of the device.

[0102] As an example, see Fig.12 The manufacturing method further includes the step of forming an interconnect metal layer 90 above the wafer 10, wherein the interconnect metal layer is electrically connected to the source metal 31, the drain metal 32 and the gate metal 70 respectively.

[0103] As an example, forming the interconnect metal layer 90 on the wafer 10 includes the following steps:

[0104] like Fig.12 As shown, a third dielectric layer 80 is formed above the dielectric layer 20, and the third dielectric layer 80 also covers the gate metal 70; a plurality of conductive holes are formed in the third dielectric layer 80, and each conductive hole correspondingly exposes at least a portion of one of the source metal 31, the drain metal 32 and the gate metal 70; an interconnect metal material layer (not shown) is formed above the third dielectric layer 80 and the interconnect metal material layer is etched to obtain the interconnect metal layer 90.

[0105] In the manufacturing method of the semiconductor device of the present embodiment, during the manufacturing process of the gate metal, after forming the first groove for filling the gate metal, a method of depositing the first metal layer on the entire surface is used to ensure good contact coverage between the gate metal and the epitaxial layer and the dielectric layer, thereby avoiding the problem of the photolithography process affecting the gate metal filling environment during the traditional gate metal manufacturing process, and effectively improving the performance of the device; then, a wet etching process is used to etch the first metal layer to obtain the second gate metal, thereby avoiding the loss of the dielectric layer caused by dry etching or the presence of metal debris residue near the second gate metal that affects the performance of the device, thereby improving the electrical performance and reliability of the device, and based on the lateral corrosion effect of the wet etching, the vertical projection of the second gate metal falls within the vertical projection range of the first gate metal, thereby further reducing the parasitic capacitance and achieving a significant improvement in the device performance.

[0106] Embodiment 2

[0107] This embodiment provides a semiconductor device. The semiconductor device can be manufactured by using the method described in the first embodiment or other suitable methods. Fig.12 The semiconductor device includes a wafer 10 , a dielectric layer 20 and a gate metal 70 .

[0108] Specifically, the dielectric layer 20 is located above the wafer 10, and a first groove 201 is formed in the dielectric layer 20, and the first groove 201 exposes at least a portion of the wafer 10; the gate metal 70 is located above the dielectric layer 20 and filled into the first groove 201, and the gate metal 70 includes a second gate metal 41 and a first gate metal 61 located above the second gate metal 41, wherein the second gate metal 41 covers the inner wall of the first groove 201, the first gate metal 61 is filled into the first groove 201, and the vertical projection of the second gate metal 41 falls within the vertical projection range of the first gate metal 61.

[0109] As an example, the formation method of the first metal layer 40 includes at least one of atomic layer deposition and magnetron sputtering, the material of the first metal layer 40 includes at least one of Ni, Ti, TiN, Al and W, and the thickness range of the first metal layer 40 is less than or equal to 10nm; the formation method of the second metal layer 60 includes at least one of atomic layer deposition and magnetron sputtering, and the material of the second metal layer 60 includes at least one of Pt, Au, Al, Ti and Ta.

[0110] As an example, the semiconductor device further includes a source metal 31 and a drain metal 32 . The source metal 31 and the drain metal 32 are embedded in the dielectric layer 20 and are arranged on both sides of the gate metal 70 .

[0111] In the semiconductor device of this embodiment, in the gate metal structure, the vertical projection of the second gate metal falls within the vertical projection range of the first gate metal, which effectively reduces the parasitic capacitance of the device, thereby improving the reliability and stability of the device.

[0112] In summary, the method for manufacturing a semiconductor device of the present invention, in the process of manufacturing the gate metal, after forming the first groove for filling the gate metal, adopts the method of depositing the first metal layer on the entire surface, so that the regional contact coverage between the gate metal and the epitaxial layer and the dielectric layer is good, which can avoid the problem of the photolithography process affecting the gate metal filling environment in the traditional gate metal manufacturing process, effectively improve the performance of the device, and then adopt the wet etching process to etch the first metal layer to obtain the second gate metal, avoiding the dry etching to cause loss to the dielectric layer or the presence of metal debris residue near the second gate metal and affecting the performance of the device, improving the electrical performance and reliability of the device, and also based on the lateral corrosion effect of the wet etching, the vertical projection of the second gate metal falls within the vertical projection range of the first gate metal, further reducing the parasitic capacitance, and achieving a significant improvement in device performance. In the semiconductor device of the present invention, in the gate metal structure, the vertical projection of the second gate metal falls within the vertical projection range of the first gate metal, effectively reducing the parasitic capacitance of the device, thereby improving the reliability and stability of the device. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0113] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, It is characterized in that The following steps are involved: providing a wafer; forming a dielectric layer above the wafer and forming a first groove in the dielectric layer, wherein the first groove exposes at least a portion of the wafer; forming a first metal layer entirely above the dielectric layer, wherein the first metal layer also covers an inner wall of the first groove; forming a first gate metal on the first metal layer by a lift-off process, wherein the first gate metal is also filled into the first groove; The first metal layer is wet-etched and a portion of the first metal layer located below the first gate metal is retained as a second gate metal, a vertical projection of the second gate metal falls within a vertical projection range of the first gate metal, and the first gate metal and the second gate metal constitute a gate metal.

2. The method for manufacturing a semiconductor device according to claim 1, Features: Forming a first gate metal on the first metal layer by a lift-off process comprises the following steps: forming a photoresist layer above the first metal layer; Patterning the photoresist layer to form a second groove, wherein the width of the second groove is greater than the width of the first groove and the second groove reveals the first groove covered with the first metal layer; forming a second metal layer on the photoresist layer, wherein the second metal layer is also filled into the second groove and the first groove covered with the first metal layer; The photoresist layer is stripped to remove the portion of the second metal layer located above the photoresist layer, and the remaining portion of the second metal layer is used as the first gate metal.

3. The method for manufacturing a semiconductor device according to claim 2, Features: The method for forming the first metal layer includes at least one of atomic layer deposition and magnetron sputtering, the material of the first metal layer includes at least one of Ni, Ti, TiN, Al and W, and the thickness range of the first metal layer is less than or equal to 10nm; the method for forming the second metal layer includes at least one of atomic layer deposition and magnetron sputtering, the material of the second metal layer includes at least one of Pt, Au, Al, Ti and Ta.

4. The method for manufacturing a semiconductor device according to claim 1, Features: The wafer includes a substrate and an epitaxial layer located on the substrate, wherein the material of the substrate includes at least one of silicon, silicon carbide, sapphire and diamond, the epitaxial layer includes a transition layer, a channel layer and a barrier layer stacked in sequence from bottom to top, and the transition layer includes at least one of an AlN nucleation layer, a multi-quantum well buffer layer, an Al composition gradient buffer layer and a GaN buffer layer.

5. The method for manufacturing a semiconductor device according to claim 1, Features: The material of the dielectric layer includes SiN, SiO 2 , SiON, AlN and Al 2 O 3 At least one of the methods, wherein the dielectric layer is formed by a method comprising at least one of a plasma enhanced chemical vapor deposition method, a physical vapor deposition method and an atomic layer deposition method.

6. The method for manufacturing a semiconductor device according to claim 1, Features: The manufacturing method also includes the step of forming a source metal and a drain metal on the wafer. The source metal and the drain metal are embedded in the dielectric layer and arranged on both sides of the gate metal.

7. The method for manufacturing a semiconductor device according to claim 1, Features: Forming a dielectric layer above the wafer includes the following steps: forming a first dielectric layer above the wafer; forming a source contact hole and a drain contact hole in the first dielectric layer, wherein the source contact hole and the drain contact hole respectively expose a portion of the wafer; forming a metal material layer above the first dielectric layer, wherein the metal material layer is also filled into the source contact hole and the drain contact hole; Etching the metal material layer to obtain a source metal and a drain metal that are separately arranged, wherein the source metal is at least filled in the source contact hole, and the drain metal is at least filled in the drain contact hole; A second dielectric layer is formed above the first dielectric layer, wherein the second dielectric layer covers the source metal and the drain metal to form a dielectric layer together with the first dielectric layer.

8. The method for manufacturing a semiconductor device according to claim 1, Features: The manufacturing method further includes the step of forming an interconnect metal layer above the wafer, wherein the interconnect metal layer is electrically connected to the source metal, the drain metal and the gate metal respectively.

9. A semiconductor device, It is characterized in that include: Wafer; a dielectric layer, located above the wafer, and having a first groove formed in the dielectric layer, wherein the first groove exposes at least a portion of the wafer; A gate metal is located above the dielectric layer and filled into the first groove, the gate metal includes a second gate metal and a first gate metal located above the second gate metal, wherein the second gate metal covers the inner wall of the first groove, the first gate metal fills into the first groove, and the vertical projection of the second gate metal falls within the vertical projection range of the first gate metal.

10. The semiconductor device according to claim 9, Features: The formation method of the first metal layer includes at least one of atomic layer deposition and magnetron sputtering, the material of the first metal layer includes at least one of Ni, Ti, TiN, Al and W, and the thickness range of the first metal layer is less than or equal to 10nm.

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