Method for realizing gate self-alignment of ultra-short channel nano wall (NWaFET) device

Abstract

The invention discloses a gate self-alignment implementation method for an ultra-short channel nano wall (NWaFET) device, and relates to the field of microelectronic technologies and integrated circuits (IC). According to the gate self-alignment implementation method for the NWaFET device, MOS devices are stacked in the vertical direction, the structure can improve the IC integration level and save the chip area, the vertical structure simultaneously adopts a gate self-alignment mode, and therefore the gate self-alignment implementation method for the NWaFET device is achieved. The gate region of the structure only wraps the channel region or the channel region and the lightly doped drift region adjacent to the channel region, so that the stray capacitance between the gate and the heavily doped region can be greatly reduced, and the frequency characteristic of the device is improved. Silicon nitride and silicon oxide are used as masks, gate self-alignment is achieved, the number of times of photoetching and errors caused by multiple times of overlay are reduced, the integration degree of an integrated circuit is improved, and the difficulty and cost of the manufacturing process are reduced.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics and integrated circuits Background Art

[0002] In recent years, integrated circuit technology has developed rapidly, from Moore's Law [1] Since the invention of integrated circuits, the development of integrated circuits has always followed the principle of scaling down. [2] As device size continues to decrease, the principle of proportional reduction begins to face severe challenges. This is because when the device is extremely small, the thermal effect caused by the increased transistor leakage current greatly reduces the performance of the device, resulting in a significant decrease in the chip's gate control ability. Therefore, many researchers began to consider improving integrated circuits from other angles to continue Moore's Law.

[0003] FinFET, or fin field effect transistor, was first proposed by Professor Hu Zhengming of the University of California, Berkeley in a paper published in 2000. [3] . The main feature of FinFET is that the channel area is a fin-shaped semiconductor wrapped by the gate, and the length of the fin along the source and drain direction is the channel length. Compared with traditional planar CMOS, the semi-ring gate fin structure of FinFET increases the control area of ​​the gate over the channel, greatly enhancing the gate control capability, thereby effectively suppressing the short channel effect and reducing subthreshold leakage current. TSMC began to mass-produce chips with 7nm process nodes in 2018, and has developed 5nm and 3nm processes in recent years.

[0004] Although FinFET has many advantages in CMOS process, it will face a series of challenges after 5nm node: for example, the gate pitch and metal intercept will be further reduced, the subthreshold slope will increase, which means the subthreshold swing will increase and the gate leakage current will be large, and the increase in fin height will lead to an increase in parasitic capacitance. For this reason, many companies have proposed a gate-all-around transistor structure. [4] The gate and source and drain no longer maintain the fin shape, but the column structure passes through the gate vertically, so the gate can wrap the channel from all sides, continuing the idea of ​​the three-dimensional structure of FinFET, so as to maximize the control of the gate over the channel area, better control the short channel and drain induced barrier lowering (DIBL) effects, and achieve greater power consumption and area advantages. According to the data provided by the IEEE International Roadmap for Devices and Systems (IRDS), the gate length of the 5nm FINFET is actually 18nm, and the channel length Lch is also difficult to increase at subsequent process nodes.

[0005] Scaling down will reduce Lch to 9.6nm by 2028, after which Lch will no longer be able to be scaled down.

[0006] Novel nanowall NWaFET structure prior to this invention [5-7] , adopting a vertical design scheme, greatly improving the integration of the device, and suppressing the DIBL effect through a combined structure of heavily doped channel region and lightly doped drift region. The NWaFET structure achieves a further reduction in Lch by adopting a heavily doped channel. It has a shorter channel length Lch than existing FINFET, GAA, and VGAA, and has a higher integration.

[0007] This paper proposes a method for realizing gate self-alignment of an extremely short channel nanowall (NWaFET) device. This method stacks MOS devices in a vertical direction. This structure can improve IC integration and save chip area. In addition, a gate self-alignment method is adopted. The gate area of ​​this structure only wraps the channel area or the channel area and the lightly doped drift area adjacent to it, which can greatly reduce the parasitic capacitance between the gate and the heavily doped source and drain area, thereby improving the device frequency characteristics.

[0008] References

[0009] [1].Moore, Gordon E. "Cramming more components onto integrated

[0010] circuits".Electronics.Retrieved 2016-07-01.Instructions 1 / 7 pages 6CN 116705796A6

[0011] [2]. Thompson S, Packan P, Bohr M. MOS scaling: transistor challenges for the 21st century. Intel Technology Journal, 1998; pp 1-18.

[0012] [3].Chenming Hu,Lee WC,Kedzierski J,et al.FinFET-a self-aligneddouble-gate MOSFET scalable to 20nm[J].IEEE Transactions on Electron Devices,2000,47(12):2320-2325.

[0013] [4].JPColinge,MHGao,A.Romano,H.Maes,C.Claeys.Silicon-on-insulator "gate-all-around"MOSdevice[C].1990IEEESOS / SOITechnologyConference.Proceedings.Key West,FL,USA:IEEE,1990:137-138..

[0014] [5]. Liao Yongbo, Li Ping, Tang Ruifeng, et al. Structure of a new digital gate integrated circuit [P]. China, invention patent, application number: CN111048579.1.2020.

[0015] [6]. Li Ping, Tang Ruifeng, Liao Yongbo, et al. A new DRAM structure and implementation method [P]. China, invention patent, application number: CN202110252584.1.2021.

[0016] [7]. Liao Yongbo, Liu Jinming, Li Ping et al. A high-integration nano-wall integrated circuit structure [P]. China, invention patent, application number: CN202210413345.4.2022. Summary of the invention

[0017] The technical problem to be solved by the present invention is to provide a method for realizing gate self-alignment of an extremely short channel nanowall FET (NWaFET) device, which is manufactured by a special gate self-alignment process to achieve the improvement of the frequency characteristics of the vertical channel MOS basic unit structure and the significant improvement of the clock integration of large-scale integrated circuit applications.

[0018] Technical solution 1 of the present invention is a method for realizing gate self-alignment of an ultra-short channel nanowall (NWaFET) device, such as Figure 1As shown, at the bottom of the structure is a P-well silicon single crystal semiconductor region 101, and a silicon single crystal N+ drain region 102 of an NMOS device is formed on the upper part of the p-well silicon single crystal semiconductor region 101; above the N+ drain region 102 is an N-silicon single crystal drain region 103; above the N-drain region 103 is a P-type channel semiconductor region 104; above the p-type channel semiconductor region 104 is an N+ silicon single crystal semiconductor source region 105; the N+ drain region 102 includes an upper portion and a lower portion, the lower portion is wider than the lower portion, and the lower surface and side surfaces of the lower portion are surrounded by the P-well region 101 is surrounded, and a groove is arranged on the side of the N-drain region 103, the P-type channel semiconductor region 104, and the N+ source region 105 of the above-mentioned NMOS, and the lower surface of the groove is lower than or flush with the interface between the N+ region 102 and the N-region drain region 103 of the NMOS; the groove is filled with a gate electrode 108 and an insulating dielectric 110; the lower surface of the gate electrode 108 is lower than or flush with the interface between the P-channel region 104 and the N-drain region 103 of the NMOS, and the upper surface of the gate electrode 108 is higher than or flush with the interface between the P-channel region 104 and the N+ source region 105 of the NMOS. The gate electrode 108 is composed of heavily doped polycrystalline. The insulating gate dielectric 110 is used to isolate the gate electrode 108 from other semiconductor regions. The NMOS drain electrode 109 is arranged on the side of the N-drain region 103, the P-type channel region 104, and the N+ source region 105 of the NMOS. The NMOS metal gate electrode 107 is disposed above the polycrystalline gate region 108 of the NMOS and on the sides of the P channel region 104 and the N+ source region 105. The insulating material 106 isolates the NMOS drain electrode 109 from the N-drain region 103, the P channel semiconductor region 104 and the N+ source region 105 of the NMOS.

[0019] Technical solution 2 of the present invention is a method for realizing gate self-alignment of an extremely short channel nanowall FET (NWaFET) device, such as Figure 2As shown, at the bottom of the structure is an N-well silicon single crystal semiconductor region 111, and a silicon single crystal N+ drain region 112 of a PMOS device is formed on the upper part of the N-well silicon single crystal semiconductor region 111; above the P+ drain region 112 is a P-silicon single crystal drain region 113; above the P-drain region 113 is an N-type channel semiconductor region 114; above the N-type channel semiconductor region 114 is a P+ silicon single crystal semiconductor source region 115; the P+ drain region 112 includes an upper portion and a lower portion, the lower portion is wider than the lower portion, and the lower surface and side surfaces of the lower portion are surrounded by the N-well region 111 surrounds, and grooves are arranged on the sides of the PMOS P-drain region 113, the N-type channel semiconductor region 114, and the N+ source region 115, and the lower surface of the groove is lower than or flush with the interface between the PMOS P+ region 112 and the P-region drain region 113; the groove is filled with a gate electrode 118 and an insulating dielectric 120; the lower surface of the gate electrode 118 is lower than or flush with the interface between the PMOS N-channel region 114 and the P-drain region 113, and the upper surface of the gate electrode 118 is higher than or flush with the interface between the PMOS N-channel region 114 and the P+ source region 115. The gate electrode 118 is composed of heavily doped polycrystalline. The insulating gate dielectric 120 is used to isolate the gate electrode 118 from other semiconductor regions. The PMOS metal gate electrode 117 is arranged above the polycrystalline gate region 118 of the PMOS, and on the sides of the N-channel region 114 and the P+ source region 115. The PMOS drain electrode 119 is disposed on the side of the PMOS P-drain region 113, the N-channel region 114, and the P+source region 115. The insulating material 116 isolates the PMOS drain electrode 119 from the PMOS P-drain region 113, the N-channel semiconductor region 114, and the N+source region 115.

[0020] Furthermore, the thickness of the P-type channel (104) is less than 10 nm.

[0021] Furthermore, the doping concentration of the P-type channel semiconductor region (104) is more than two orders of magnitude higher than that of the N-drain region (103).

[0022] Furthermore, the thickness of the N-type channel (114) is less than 10 nm.

[0023] Furthermore, the doping concentration of the N-type channel semiconductor region (114) is more than two orders of magnitude higher than that of the P-drain region (113).

[0024] Furthermore, all layer thicknesses range from 1nm to 100nm, and doping concentrations range from 1e14cm -3 -1e20 cm -3 .

[0025] The present invention proposes a method for realizing gate self-alignment of an extremely short channel nanowall (NWaFET) device, which adopts a gate self-alignment method so that the gate region of a vertical MOS structure device only wraps the channel region or the channel region and the lightly doped drift region adjacent thereto, which can greatly reduce the parasitic capacitance between the gate and the heavily doped source and drain region, thereby improving the device frequency characteristics. Silicon nitride and silicon oxide are used as masks to realize gate self-alignment, which reduces the number of photolithography times and the errors caused by multiple overlays, improves the integration of integrated circuits, and reduces the difficulty and cost of the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The oblique cross-sectional view of an NMOS structure unit (source region, channel region, lightly doped drain region, drain region from top to bottom) using a method for realizing gate self-alignment of an extremely short channel nanowall (NWaFET) device according to the present invention.

[0027] Figure 2 The oblique cross-sectional view of a PMOS structure (source region, channel region, lightly doped drain region, drain region from top to bottom) unit using a method for realizing gate self-alignment of an extremely short channel nanowall (NWaFET) device according to the present invention.

[0028] Figure 3 The present invention is a top view of an NMOS structural unit using a method for realizing gate self-alignment of an extremely short channel nanowall (NWaFET) device.

[0029] Figure 4 The present invention is a top view of a PMOS structural unit using a method for realizing gate self-alignment of an extremely short channel nanowall FET (NWaFET) device.

[0030] Figure 5 , Figure 6 The present invention discloses a process flow of a method for realizing gate self-alignment of an extremely short channel nanowall FET (NWaFET) device, realizing the structures described in Technical Solutions 1 and 2. DETAILED DESCRIPTION

[0031] Example 1: In order to clearly understand the method for implementing gate self-alignment of an ultra-short channel nanowall (NWaFET) device of the present invention, this example specifically introduces the process flow of implementing the structure described in Technical Solution 1.

[0032] The first step, such as Figure 5 (a) shows a P-type bottom;

[0033] The second step is, Figure 5 As shown in (b), a layer of silicon dioxide and a thin layer of silicon nitride are deposited on a P-type substrate;

[0034] The third step is Figure 5As shown in (c), silicon nitride and silicon dioxide are etched, and a layer of N+ type semiconductor region and a layer of N-type semiconductor region are epitaxially grown, and a planarization process is performed by chemical mechanical polishing (CMP) to make the upper surface of silicon nitride flush with the upper surface of the N-type semiconductor region;

[0035] The fourth step is Figure 5 As shown in (d), a layer of P-type semiconductor region is epitaxially grown, and no P-type semiconductor grows on the silicon nitride in the gate region, forming an extremely short channel P-type semiconductor region;

[0036] Step 5: Figure 5 (e) shows chemical etching of silicon nitride;

[0037] Step 6: Figure 5 As shown in (f), a thin layer of silicon oxide SiO is grown by low temperature thermal oxidation. 2 , forming a gate oxide layer;

[0038] Step 7: Figure 5 (g) shows that polysilicon is deposited until the upper surface of the polysilicon is higher than the upper surface of the silicon oxide above the P-type semiconductor region, and then a chemical mechanical polishing (CMP) is performed to planarize the polysilicon until the upper surface is flush with the upper surface of the silicon oxide above the P-type semiconductor region;

[0039] Step 8: Figure 5 As shown in (h), oxidation is performed again. Because of the blocking effect of silicon oxide, the growth rate of silicon oxide of polysilicon is greater than the growth rate of silicon oxide above the P-type semiconductor region, and the thickness of silicon oxide above the polysilicon is greater than the thickness of silicon oxide above the P-type semiconductor channel region.

[0040] Step 9: Figure 5 As shown in (i), SiO is etched by reactive ion etching. 2 At the same time, endpoint detection is performed. When the SiO 2 Stop reactive ion etching when the silicon oxide disappears and a certain thickness of silicon oxide still exists above the polysilicon;

[0041] Step 10: Figure 5 As shown in (j), a thin N+ type semiconductor region source region is epitaxially grown, and semiconductor silicon will not grow on top of the polysilicon;

[0042] Step 11: Figure 5 As shown in (k), silicon oxide is deposited and then planarized by chemical mechanical polishing (CMP);

[0043] Step 12: Figure 5 As shown in (l), grooves are cut, filled with insulating material, holes are opened in the insulating material, and metal lead electrodes are filled.

[0044] Example 2: In order to clearly understand the method for implementing gate self-alignment of an ultra-short channel nanowall (NWaFET) device of the present invention, this example specifically introduces the process flow of implementing the structure described in Technical Solution 2.

[0045] The first step, such as Figure 6 (a) shows an N-type sink;

[0046] The second step is, Figure 6 As shown in (b), a layer of silicon dioxide and a thin layer of silicon nitride are deposited on an N-type substrate;

[0047] The third step is Figure 6 As shown in (c), silicon nitride and silicon dioxide are etched, and a layer of P+ type semiconductor region and a layer of P-type semiconductor region are epitaxially grown, and a planarization process is performed by chemical mechanical polishing (CMP) to make the upper surface of silicon nitride flush with the upper surface of the P-type semiconductor region;

[0048] The fourth step is Figure 6 As shown in (d), a layer of N-type semiconductor region is epitaxially grown, and no N-type semiconductor is grown on the silicon nitride in the gate region;

[0049] Step 5: Figure 6 (e) shows chemical etching of silicon nitride;

[0050] Step 6: Figure 6 As shown in (f), a thin layer of silicon oxide SiO is grown by low temperature thermal oxidation. 2 ;

[0051] Step 7: Figure 6 (g) shows that polysilicon is deposited until the upper surface of the polysilicon is higher than the upper surface of the silicon oxide above the N-type semiconductor region, and then a chemical mechanical polishing (CMP) is performed to planarize the polysilicon until the upper surface is flush with the upper surface of the silicon oxide above the N-type semiconductor region;

[0052] Step 8: Figure 6 As shown in (h), oxidation is performed again. Because of the blocking effect of silicon oxide, the growth rate of silicon oxide above the polysilicon is greater than the growth rate of silicon oxide above the N-type semiconductor region. The thickness of silicon oxide above the polysilicon is greater than the thickness of silicon oxide above the N-type semiconductor channel region.

[0053] Step 9: Figure 6 As shown in (i), SiO is etched by reactive ion etching. 2 At the same time, endpoint detection is performed. When the SiO 2 Stop reactive ion etching when the silicon oxide disappears and a certain thickness of silicon oxide still exists above the polysilicon;

[0054] Step 10: Figure 6 As shown in (j), a layer of P+ semiconductor region is grown epitaxially, and no growth occurs on top of the polysilicon;

[0055] Step 11: Figure 6 As shown in (k), silicon oxide is deposited and then planarized by chemical mechanical polishing (CMP);

[0056] Step 12: Figure 6 As shown in (l), grooves are cut, filled with insulating material, holes are opened in the insulating material, and metal lead electrodes are filled.

Claims

1. A method for realizing gate self-alignment of an extremely short channel nanowall transistor (NWaFET) device, It is characterized in that At the bottom of the structure is a P-well silicon single crystal semiconductor region 101, on the top of the p-well silicon single crystal semiconductor region 101 is formed a silicon single crystal N+ drain region 102 of the NMOS device; above the N+ drain region 102 is an N-silicon single crystal drain region 103; above the N-drain region 103 is a P-type channel semiconductor region 104; above the p-type channel semiconductor region 104 is an N+ silicon single crystal semiconductor source region 105; the N+ drain region 102 includes an upper portion and a lower portion, the lower portion is wider than the lower portion, and the lower surface and side surfaces of the lower portion are surrounded by the P-well region 10 1 is surrounded, and grooves are arranged on the sides of the N-drain region 103, the P-type channel semiconductor region 104, and the N+ source region 105 of the NMOS. The lower surface of the groove is lower than or flush with the interface between the N+ region 102 and the N-drain region 103 of the NMOS; the groove is filled with a gate electrode 108 and an insulating dielectric 110; the lower surface of the gate electrode 108 is lower than or flush with the interface between the P-channel region 104 and the N-drain region 103 of the NMOS, and the upper surface of the gate electrode 108 is higher than or flush with the interface between the P-channel region 104 and the N+ source region 105 of the NMOS. The gate electrode 108 is composed of heavily doped polycrystalline. The insulating gate dielectric 110 is used to isolate the gate electrode 108 from other semiconductor regions. The NMOS drain electrode 109 is arranged on the sides of the N-drain region 103, the P-type channel region 104, and the N+ source region 105 of the NMOS. The NMOS metal gate electrode 107 is disposed above the polycrystalline gate region 108 of the NMOS and on the sides of the P channel region 104 and the N+ source region 105. The insulating material 106 isolates the NMOS drain electrode 109 from the N-drain region 103, the P channel semiconductor region 104 and the N+ source region 105 of the NMOS.

2. A method for realizing gate self-alignment of an extremely short channel nanowall transistor (NWaFET) device, It is characterized in that At the bottom of the structure is an N-well silicon single crystal semiconductor region 111, on the upper part of the N-well silicon single crystal semiconductor region 111 is formed a silicon single crystal P+ drain region 112 of a PMOS device; above the P+ drain region 112 is a P- silicon single crystal drain region 113; above the P- drain region 113 is an N-type channel semiconductor region 114; Above the N-type channel semiconductor region 114 is a P+ silicon single crystal semiconductor source region 115; the P+ drain region 112 includes an upper portion and a lower portion, the lower portion is wider than the lower portion, and the lower surface and side surface of the lower portion are surrounded by the N-well region 111. A groove is provided on the side surface of the PMOS P-drain region 113, the N-type channel semiconductor region 114, and the P+ source region 115, and the lower surface of the groove is lower than or flush with the interface between the PMOS P+ region 112 and the P-region drain region 113; the groove is filled with a gate electrode 118 and an insulating medium 120; the lower surface of the gate electrode 118 is lower than or flush with the interface between the PMOS N-channel region 114 and the P-drain region 113, and the upper surface of the gate electrode 118 is higher than or flush with the interface between the PMOS N-channel region 114 and the P+ source region 115. The gate electrode 118 is made of heavily doped polycrystalline. The insulating gate dielectric 120 is used to isolate the gate electrode 118 from other semiconductor regions. The PMOS metal gate electrode 117 is disposed above the polycrystalline gate region 118 of the PMOS and on the sides of the N-channel region 114 and the P+ source region 115. The PMOS drain electrode 119 is disposed on the sides of the P-drain region 113, the N-type channel region 114, and the P+ source region 115 of the PMOS. The insulating material 116 isolates the PMOS drain electrode 119 from the P-drain region 113, the N-type channel semiconductor region 114, and the N+ source region 115 of the PMOS.

3. A method for realizing gate self-alignment of a very short channel nanowall FET (NWaFET) device according to any one of claims 1 to 2, Features The thickness of the P-type channel semiconductor region 104 of the NMOS is less than 10 nm, and the thickness of the N-type channel semiconductor region 114 of the PMOS is less than 10 nm.

4. A method for realizing gate self-alignment of a very short channel nanowall FET (NWaFET) device according to any one of claims 1 to 2, It is characterized in that All layer thicknesses range from 1nm to 100nm, and doping concentrations range from 1e14cm-3 to 1e20 cm-3.

5. A method for realizing gate self-alignment of an ultra-short channel nanowall field-effect transistor (NWaFET) device as described in claims 1, 2, 3, and 4, wherein the gate (108, 118) is made of polysilicon.

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