Integrated semiconductor device and preparation method thereof

Abstract

The invention provides an integrated semiconductor device and a preparation method thereof, and in the preparation method of the integrated semiconductor device, DTI (a first deep trench isolation structure and a second deep trench isolation structure) and SOI (an underlying silicon substrate, an intermediate oxide layer and a top silicon substrate) are combined to form all-dielectric isolation. Therefore, a CMOS (complementary metal oxide semiconductor) device (taking an NMOS (N-channel metal oxide semiconductor) device as an example) and an LDMOS (laterally diffused metal oxide semiconductor) device on an SOI (silicon-on-insulator) are completely isolated, the overall EMI (electro-magnetic interference) resistance of a chip is improved, a parasitic bipolar effect is completely eradicated, the latch risk is eliminated, and the working reliability of a circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an integrated semiconductor device and a method for preparing the same. Background Art

[0002] With the growing demand for high digital integration and high processing power in analog applications, BCD-on-SOI technology came into being. BCD is the full name of Bipolar-CMOS-DMOS, which means making bipolar transistors, CMOS devices and DMOS devices on the same chip. SOI is translated into silicon on insulator. BCD-on-SOI process technology combines the attractive properties of SOI (Silicon-On-Insulator) and DTI (Deep trench isolation) to make the product highly stable. The chip operating temperature range is -40℃ to 175℃. Due to its full dielectric isolation characteristics, the product exhibits high anti-EMI (electromagnetic interference) capability. Since there is no parasitic bipolar effect, the risk of latch-up will be completely eliminated, and the reliability of circuit operation is guaranteed.

[0003] At present, the traditional Bulk BCD process has the disadvantages of low integration and inability to meet the next generation of vehicle applications with higher-level data processing capabilities. Furthermore, the current capability of current MOSFETT devices is relatively weak. Although the traditional Bulk BCD process can improve the current capability, it may cause a series of disadvantages such as parasitic bipolar turn-on. Summary of the invention

[0004] The present application provides an integrated semiconductor device and a method for preparing the same, which improves the integration of a single chip and can meet the needs of next-generation vehicle-mounted applications with higher-level data processing capabilities. Therefore, the present application uses BCD-on-SOI technology to prepare integrated semiconductor devices, which can provide an ideal solution for realizing industrial, medical and vehicle-mounted applications.

[0005] On the one hand, an embodiment of the present application provides a method for preparing an integrated semiconductor device, comprising:

[0006] Providing a bottom silicon substrate, the bottom silicon substrate comprising a CMOS device region and an LDMOS device region, and an intermediate oxide layer and a top silicon substrate are sequentially formed on the bottom silicon substrate;

[0007] Forming an epitaxial layer, wherein the epitaxial layer covers the top silicon substrate of the CMOS device area and the top silicon substrate of the LDMOS device area;

[0008] forming a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located in the epitaxial layers of the CMOS device region and the LDMOS device region and are spaced apart from each other;

[0009] Etching the shallow trench isolation structure, the epitaxial layer, the top silicon substrate, the middle oxide layer and the bottom silicon substrate of the CMOS device area to form a first annular deep trench, and etching the shallow trench isolation structure, the epitaxial layer, the top silicon substrate, the middle oxide layer and the bottom silicon substrate of the LDMOS device area to form a second annular deep trench;

[0010] forming an isolation layer, wherein the isolation layer covers the sidewalls and bottom wall of the first annular deep groove and the sidewalls and bottom wall of the second annular deep groove;

[0011] Filling the first annular deep trench with polysilicon material to obtain a first annular deep trench isolation structure, and filling the second annular deep trench with polysilicon material to obtain a second annular deep trench isolation structure;

[0012] A first well region and two buffer regions are formed in the epitaxial layer in the first annular deep trench isolation structure of the CMOS device region, and a body region, a drift region and a second well region are formed in the epitaxial layer in the second annular deep trench isolation structure of the LDMOS device region by an ion implantation process, wherein the buffer regions are all located in the first well region and are respectively located on the side of the shallow trench isolation structure, the body region and the drift region are arranged at intervals, and the second well region is located in the drift region;

[0013] Forming a first gate and a second gate, wherein the first gate is located on the epitaxial layer between two buffer regions of the CMOS device region, and the second gate is located on the epitaxial layer between the body region and the drift region of the LDMOS device region;

[0014] A first base region, a first source region and a first drain region are respectively formed in the CMOS device region, and a second base region, a second source region and a second drain region are respectively formed in the LDMOS device region by an ion implantation process, wherein part of the first source region is located in a buffer region, the remaining first source region is located in the first well region, the first base region is located in the middle of the first source region, and the first drain region is located in another buffer region; the second base region and the second source region are both located in the body region, the second base region is located in the middle of the second source region, and the second drain region is located in the second well region.

[0015] Optionally, in the method for preparing the integrated semiconductor device, a lateral dimension of the second annular deep trench is at least twice a lateral dimension of the first annular deep trench.

[0016] Optionally, in the method for preparing the integrated semiconductor device, the depth of the second annular deep trench is greater than the depth of the first annular deep trench.

[0017] Optionally, in the method for preparing the integrated semiconductor device, after forming the first base region, the first source region and the first drain region, and the second base region, the second source region and the second drain region, the method for preparing the integrated semiconductor device further comprises:

[0018] Forming an interlayer insulating dielectric layer, wherein the interlayer insulating dielectric layer covers the first gate, the shallow trench isolation structure, the first annular deep trench and the epitaxial layer of the CMOS device area, and the second gate, the shallow trench isolation structure, the second annular deep trench and the epitaxial layer of the LDMOS device area;

[0019] Etching the interlayer insulating dielectric layer to form a plurality of through holes;

[0020] Filling metal material in the through hole to obtain a plurality of conductive plugs, wherein at least one of the conductive plugs is connected to the polysilicon material in the first annular deep trench, at least one of the conductive plugs is connected to the first gate, at least one of the conductive plugs is connected to the second base region, at least one of the conductive plugs is connected to the second gate, and at least one of the conductive plugs is connected to the second drain region;

[0021] A patterned metal layer is formed, wherein the patterned metal layer at least covers the conductive plug and a portion of the interlayer insulating dielectric layer in the CMOS device area, and a portion of the interlayer insulating dielectric layer in the LDMOS device area, and each conductive plug in the LDMOS device area is respectively covered, wherein the patterned metal layer in the CMOS device area and the patterned metal layer in the LDMOS device area are not connected.

[0022] Optionally, in the method for preparing the integrated semiconductor device, the step of forming a plurality of shallow trench isolation structures includes:

[0023] Etching the epitaxial layers of the CMOS device region and the LDMOS device region to form a plurality of shallow trenches;

[0024] An isolation material is filled in the shallow trenches to obtain a plurality of shallow trench isolation structures.

[0025] Optionally, in the method for preparing the integrated semiconductor device, the shallow trench isolation structures penetrated by the first annular deep trench isolation structure and the second annular deep trench isolation structure are both annular; and the remaining shallow trench isolation structures located within the second annular deep trench isolation structure are all strip-shaped.

[0026] Optionally, in the method for preparing the integrated semiconductor device, the conductivity type of the doped ions on the surface of the top silicon substrate is N-type; the doped type of the epitaxial layer is N-type; the conductivity type of the doped ions in the first well region is P-type; the conductivity type of the doped ions in the buffer region is N-type; the conductivity type of the doped ions in the body region is P-type; the conductivity type of the doped ions in the drift region is N-type, and the conductivity type of the doped ions in the second well region is N-type; the conductivity type of the doped ions in the first base region is P-type; the conductivity type of the doped ions in the first source region is N-type; the conductivity type of the doped ions in the first drain region is N-type; the conductivity type of the doped ions in the second base region is P-type; the conductivity type of the doped ions in the second source region is N-type; and the conductivity type of the doped ions in the second drain region is N-type.

[0027] Optionally, in the method for preparing the integrated semiconductor device, the isolation layer is made of silicon dioxide.

[0028] Optionally, in the method for preparing the integrated semiconductor device, the thickness of the bottom silicon substrate is 750 μm to 800 μm; the thickness of the middle oxide layer is 0.4 μm to 0.8 μm; and the thickness of the top silicon substrate is 0.3 μm to 0.7 μm.

[0029] On the other hand, an embodiment of the present application further provides an integrated semiconductor device, including:

[0030] A bottom silicon substrate, wherein the bottom silicon substrate comprises a CMOS device region and an LDMOS device region, and an intermediate oxide layer and a top silicon substrate are sequentially formed on the bottom silicon substrate;

[0031] An epitaxial layer, wherein the epitaxial layer covers the top silicon substrate of the CMOS device region and the top silicon substrate of the LDMOS device region;

[0032] A plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located in the epitaxial layers of the CMOS device region and the LDMOS device region and are spaced apart from each other;

[0033] A first annular deep trench, the first annular deep trench being located in a shallow trench isolation structure, an epitaxial layer, a top silicon substrate, an intermediate oxide layer and a partial thickness of a bottom silicon substrate in the CMOS device region;

[0034] A second annular deep trench, wherein the second annular deep trench is located in the shallow trench isolation structure, the epitaxial layer, the top silicon substrate, the middle oxide layer and a partial thickness of the bottom silicon substrate of the LDMOS device region;

[0035] an isolation layer, the isolation layer covering the side walls and bottom wall of the first annular deep groove and the side walls and bottom wall of the second annular deep groove;

[0036] A polysilicon material, wherein the polysilicon material fills the first annular deep trench to obtain a first annular deep trench isolation structure, and fills the second annular deep trench to obtain a second annular deep trench isolation structure;

[0037] A first well region, two buffer regions, a body region, a drift region, and a second well region, wherein the first well region and the two buffer regions are located in an epitaxial layer within a first annular deep trench isolation structure of the CMOS device region, and the body region, the drift region, and the second well region are located in an epitaxial layer within a second annular deep trench isolation structure of the LDMOS device region, wherein the buffer regions are all located in the first well region and are respectively located on the side of the shallow trench isolation structure, the body region and the drift region are spaced apart, and the second well region is located in the drift region;

[0038] A first gate and a second gate, wherein the first gate is located on an epitaxial layer between two buffer regions of the CMOS device region, and the second gate is located on an epitaxial layer between a body region and a drift region of the LDMOS device region;

[0039] A first base region, a first source region, a first drain region, a second base region, a second source region, and a second drain region, wherein, in the CMOS device region, part of the first source region is located in a buffer region, the remaining first source region is located in the first well region, the first base region is located in the middle of the first source region, and the first drain region is located in another buffer region; in the LDMOS device region, the second base region and the second source region are both located in the body region and the second base region is located in the middle of the second source region, and the second drain region is located in the second well region.

[0040] The technical solution of this application has at least the following advantages:

[0041] The present application combines DTI (a first deep trench isolation structure and a second deep trench isolation structure) with SOI (a bottom silicon substrate, an intermediate oxide layer, and a top silicon substrate) to form full dielectric isolation, thereby completely isolating the CMOS devices (this embodiment takes NMOS devices as an example) and LDMOS devices on the SOI, improving the overall anti-EMI capability of the chip, completely eliminating parasitic bipolar effects, and eliminating the risk of latch-up, thereby improving the circuit operation reliability.

[0042] Furthermore, since SOI MOS devices have high saturation current characteristics, they provide device options for high-performance digital logic functions. The use of the SOI BCD technology of the present application to prepare CMOS devices and LDMOS device integrated devices can more easily integrate high-density digital logic and analog functions into a single chip, which can meet the next generation of vehicle-mounted applications with higher levels of data processing capabilities, and provide an ideal solution for realizing industrial, medical and vehicle-mounted applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 is a schematic diagram of a semiconductor structure after forming an epitaxial layer according to an embodiment of the present invention;

[0045] Figure 2 is a schematic diagram of a semiconductor structure after a shallow trench isolation structure is formed according to an embodiment of the present invention;

[0046] Figure 3 is a schematic diagram of a semiconductor structure after forming a first deep trench and a second deep trench according to an embodiment of the present invention;

[0047] Figure 4 is a schematic top view of a first deep trench and a second deep trench according to an embodiment of the present invention;

[0048] Figure 5 is a schematic diagram of a semiconductor structure after a first deep trench isolation structure and a second deep trench isolation structure are formed according to an embodiment of the present invention;

[0049] Figure 6 It is a schematic diagram of a semiconductor structure after forming a first well region, two buffer regions, a body region, a drift region, and a second well region according to an embodiment of the present invention;

[0050] Figure 7 is a schematic diagram of a semiconductor structure after forming a first gate and a second gate according to an embodiment of the present invention;

[0051] Figure 8 is a schematic diagram of a semiconductor structure after a patterned metal layer is formed according to an embodiment of the present invention;

[0052] The reference numerals are described as follows:

[0053] 11-bottom silicon substrate, 12-middle oxide layer, 13-top silicon substrate, 20-epitaxial layer, 21-shallow trench isolation structure, 22-first deep trench, 23-second deep trench, 24-isolation layer, 25-polysilicon material, 31-first well region, 32-two buffer regions, 41-body region, 42-drift region, 43-second well region, 61-first gate, 62-second gate, 71-first base region, 72-first source region, 73-first drain region, 81-second base region, 82-second source region, 83-second drain region, 91-interlayer insulating dielectric layer, 92-conductive plug, 93-patterned metal layer. DETAILED DESCRIPTION

[0054] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0055] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0056] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0057] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0058] The present application provides a method for preparing an integrated semiconductor device. Figure 1-Figure 8 , the method for preparing the integrated semiconductor device comprises:

[0059] First, refer to Figure 1 , Figure 1 It is a schematic diagram of a semiconductor structure after forming an epitaxial layer according to an embodiment of the present invention, providing a bottom silicon substrate 11, wherein the bottom silicon substrate 11 comprises a CMOS device region and an LDMOS device region, and an intermediate oxide layer 12 and a top silicon substrate 13 are sequentially formed on the bottom silicon substrate 11.

[0060] In this embodiment, the thickness of the bottom silicon substrate 11 is 750 μm to 800 μm; the thickness of the middle oxide layer 12 is 0.4 μm to 0.8 μm; and the thickness of the top silicon substrate 13 is 0.3 μm to 0.7 μm.

[0061] This embodiment takes the CMOS device region as an NMOS device as an example, and specifically introduces the integrated preparation method of the NMOS device and the LDMOS device.

[0062] In this embodiment, the conductivity type of the doped ions on the surface of the top silicon substrate 13 is N-type.

[0063] Then, continue to refer to Figure 1 , forming an epitaxial layer 20, wherein the epitaxial layer 20 covers the top silicon substrate 13 of the CMOS device area and the top silicon substrate 13 of the LDMOS device area.

[0064] In this embodiment, the doping type of the epitaxial layer 20 is N-type.

[0065] Preferably, the epitaxial layer 20 may be formed by an epitaxial doping growth process.

[0066] Next, refer to Figure 2 , Figure 2 It is a schematic diagram of a semiconductor structure after forming a shallow trench isolation structure according to an embodiment of the present invention, wherein a plurality of shallow trench isolation structures 21 are formed. The shallow trench isolation structures 21 are located in the epitaxial layer 20 of the CMOS device region and the LDMOS device region and are spaced apart from each other.

[0067] Specifically, the steps of forming multiple shallow trench isolation structures include: etching the epitaxial layer 20 of the CMOS device area and the LDMOS device area to form multiple shallow trenches; filling isolation materials (such as silicon dioxide) in the shallow trenches to obtain multiple shallow trench isolation structures 21.

[0068] For further reference, Figure 3 and Figure 4 , Figure 3 is a schematic diagram of a semiconductor structure after forming a first deep trench and a second deep trench according to an embodiment of the present invention, Figure 4It is a top view schematic diagram of the first deep trench and the second deep trench of an embodiment of the present invention, wherein the shallow trench isolation structure 21, the epitaxial layer 20, the top silicon substrate 13, the intermediate oxide layer 12 and the partial thickness of the bottom silicon substrate 11 of the CMOS device area are etched to form a first annular deep trench 22, and the shallow trench isolation structure 21, the epitaxial layer 20, the top silicon substrate 13, the intermediate oxide layer 12 and the partial thickness of the bottom silicon substrate 11 of the LDMOS device area are etched to form a second annular deep trench 23.

[0069] Preferably, the transverse dimension of the second annular deep groove 23 is at least twice the transverse dimension of the first annular deep groove 22 .

[0070] Preferably, the depth of the second annular deep groove 23 is greater than the depth of the first annular deep groove 22 .

[0071] Next, refer to Figure 5 , Figure 5 It is a schematic diagram of the semiconductor structure after forming the first deep trench isolation structure and the second deep trench isolation structure according to an embodiment of the present invention, forming an isolation layer 24, and the isolation layer 24 covers the side walls and bottom walls of the first annular deep trench 22 and the side walls and bottom walls of the second annular deep trench 23.

[0072] In this embodiment, the isolation layer 24 is made of silicon dioxide.

[0073] For further information, please refer to Figure 5 , the first annular deep trench 22 is filled with polysilicon material 25 to obtain a first annular deep trench isolation structure, and the second annular deep trench 23 is filled with polysilicon material 25 to obtain a second annular deep trench isolation structure.

[0074] It is worth noting that the shallow trench isolation structures 21 penetrated by the first annular deep trench isolation structure and the second annular deep trench isolation structure are both annular; and the remaining shallow trench isolation structures 23 located in the area surrounded by the second annular deep trench isolation structure are all strip-shaped.

[0075] Next, refer to Figure 6 , Figure 6It is a schematic diagram of the semiconductor structure after forming the first well region, two buffer regions, body region, drift region, and second well region of the embodiment of the present invention. The first well region 31 and two buffer regions 32 are formed in the epitaxial layer 20 in the first annular deep trench isolation structure of the CMOS device region through ion implantation process, and the body region 41, drift region 42, and second well region 43 are formed in the epitaxial layer 20 in the second annular deep trench isolation structure of the LDMOS device region, wherein the buffer regions 32 are all located in the first well region 31 and are respectively located on the side of the shallow trench isolation structure 21, that is, the buffer regions 32 are all located in the area surrounded by the first annular deep trench isolation structure. Further, the body region 41 and the drift region 42 are arranged at intervals, and the second well region 43 is located in the drift region 42. Among them, the implantation of the N-type buffer region in the CMOS device region can help the NMOS device form a longitudinal conductive channel and improve the saturation current capability of the MOS device. Among them, the N-type buffer region 32 can also be called N-type.

[0076] In this embodiment, the conductivity type of the doped ions in the first well region 31 is P type; the conductivity type of the doped ions in the buffer region 32 is N type; the conductivity type of the doped ions in the body region 41 is P type; the conductivity type of the doped ions in the drift region 42 is N type, and the conductivity type of the doped ions in the second well region 43 is N type.

[0077] For further reference, Figure 7 , Figure 7 1 is a schematic diagram of a semiconductor structure after forming a first gate and a second gate according to an embodiment of the present invention, wherein a first gate 61 and a second gate 62 are formed, wherein the first gate 61 is located on the epitaxial layer 20 between the two buffer regions 32 of the CMOS device region, and the second gate 61 is located on the epitaxial layer 20 between the body region 41 and the drift region 42 of the LDMOS device region.

[0078] Finally, reference Figure 8 , Figure 8 3 is a schematic diagram of a semiconductor structure after a patterned metal layer is formed in an embodiment of the present invention, wherein a first base region 71, a first source region 72 and a first drain region 73 are respectively formed in the CMOS device region, and a second base region 81, a second source region 82 and a second drain region 83 are formed in the LDMOS device region through an ion implantation process, wherein part of the first source region 72 is located in a buffer region 32, and the remaining first source region 72 is located in the first well region 31, the first base region 71 is located in the middle of the first source region 72, and the first drain region 73 is located in another buffer region 32; the second base region 81 and the second source region 82 are both located in the body region 41, and the second base region 81 is located in the middle of the second source region 82, and the second drain region 83 is located in the second well region 42.

[0079] In this embodiment, the conductivity type of the doped ions in the first base region 71 is P type; the conductivity type of the doped ions in the first source region 72 is N type; the conductivity type of the doped ions in the first drain region 73 is N type; the conductivity type of the doped ions in the second base region 81 is P type; the conductivity type of the doped ions in the second source region 82 is N type; and the conductivity type of the doped ions in the second drain region 83 is N type.

[0080] For further information, please refer to Figure 8 After forming the first base region 71, the first source region 72 and the first drain region 73, and the second base region 81, the second source region 82 and the second drain region 83, the method for preparing the integrated semiconductor device may further include:

[0081] Forming an interlayer insulating dielectric layer 91, wherein the interlayer insulating dielectric layer 91 covers the first gate 61, the shallow trench isolation structure 21, the first annular deep trench and the epitaxial layer 20 of the CMOS device area, and covers the second gate 62, the shallow trench isolation structure 21, the second annular deep trench and the epitaxial layer 20 of the LDMOS device area;

[0082] Etching the interlayer insulating dielectric layer 91 to form a plurality of through holes;

[0083] Filling the through hole with metal material to obtain a plurality of conductive plugs 92, wherein at least one of the conductive plugs 92 is connected to the polysilicon material 25 in the first annular deep trench 22, at least one of the conductive plugs 92 is connected to the first gate 61, at least one of the conductive plugs 92 is connected to the second base region 81, at least one of the conductive plugs 92 is connected to the second gate 62, and at least one of the conductive plugs 92 is connected to the second drain region 83;

[0084] A patterned metal layer 93 is formed, wherein the patterned metal layer 93 at least covers the conductive plug 92 and a portion of the interlayer insulating dielectric layer 91 in the CMOS device area, and a portion of the interlayer insulating dielectric layer 91 in the LDMOS device area, and covers each conductive plug 92 in the LDMOS device area, respectively, wherein the patterned metal layer 93 in the CMOS device area and the patterned metal layer 93 in the LDMOS device area are not connected.

[0085] The present application combines DTI (first deep trench isolation structure, second deep trench isolation structure) and SOI (bottom silicon substrate, middle oxide layer and top silicon substrate) to form full dielectric isolation, thereby completely isolating the CMOS device (this embodiment takes NMOS device as an example) and LDMOS device on SOI, improving the overall anti-EMI capability of the chip, and completely eliminating the parasitic bipolar effect, eliminating the risk of latch-up, thereby improving the circuit operation reliability. Furthermore, since SOI MOS devices have high saturation current characteristics, they provide device selection for high-performance digital logic functions. The use of the SOI BCD technology of the present application to prepare CMOS devices and LDMOS device integrated devices can make it easier to integrate high-density digital logic and analog functions into a single chip, which can meet the next generation of vehicle-mounted applications with higher-level data processing capabilities, and provide an ideal solution for realizing industrial, medical and vehicle-mounted applications.

[0086] Based on the same inventive concept, the present application embodiment also provides an integrated semiconductor device, referring to Figure 8 , the integrated semiconductor device comprises:

[0087] A bottom silicon substrate 11, wherein the bottom silicon substrate 11 comprises a CMOS device region and an LDMOS device region, and an intermediate oxide layer 12 and a top silicon substrate 13 are sequentially formed on the bottom silicon substrate 11;

[0088] An epitaxial layer 20, wherein the epitaxial layer 20 covers the top silicon substrate 11 of the CMOS device region and the top silicon substrate 13 of the LDMOS device region;

[0089] A plurality of shallow trench isolation structures 21, wherein the shallow trench isolation structures 21 are located in the epitaxial layer 20 of the CMOS device region and the LDMOS device region and are spaced apart from each other;

[0090] A first annular deep trench 22, wherein the first annular deep trench 22 is located in the shallow trench isolation structure 21, the epitaxial layer 20, the top silicon substrate 13, the middle oxide layer 12 and the bottom silicon substrate 11 of a partial thickness in the CMOS device region;

[0091] A second annular deep trench 23, wherein the second annular deep trench 23 is located in the shallow trench isolation structure 21, the epitaxial layer 20, the top silicon substrate 13, the middle oxide layer 12 and the bottom silicon substrate 11 of a partial thickness in the LDMOS device region;

[0092] an isolation layer 24, wherein the isolation layer 24 covers the side walls and the bottom wall of the first annular deep groove 22 and the side walls and the bottom wall of the second annular deep groove 23;

[0093] A polysilicon material 25, wherein the polysilicon material 25 fills the first annular deep trench 22 to obtain a first annular deep trench isolation structure, and fills the second annular deep trench 23 to obtain a second annular deep trench isolation structure;

[0094] A first well region 31, two buffer regions 32, a body region 41, a drift region 42 and a second well region 43, wherein the first well region 31 and the two buffer regions 32 are located in the epitaxial layer 20 in the first annular deep trench isolation structure of the CMOS device region, the body region 41, the drift region 42 and the second well region 43 are located in the epitaxial layer 20 in the second annular deep trench isolation structure of the LDMOS device region, wherein the buffer regions 32 are all located in the first well region 31 and are respectively located on the side of the shallow trench isolation structure 21, the body region 41 and the drift region 42 are arranged at intervals, and the second well region 43 is located in the drift region 42;

[0095] A first gate 61 and a second gate 62, wherein the first gate 61 is located on the epitaxial layer 20 between the two buffer regions 32 of the CMOS device region, and the second gate 62 is located on the epitaxial layer 20 between the body region 41 and the drift region 42 of the LDMOS device region;

[0096] A first base region 71, a first source region 72, a first drain region 73, a second base region 81, a second source region 82 and a second drain region 83, wherein, in the CMOS device region, part of the first source region 72 is located in a buffer region 32, the remaining first source region 72 is located in the first well region 31, the first base region 71 is located in the middle of the first source region 72, and the first drain region 73 is located in another buffer region 32; in the LDMOS device region, the second base region 81 and the second source region 82 are both located in the body region 41 and the second base region 81 is located in the middle of the second source region 72, and the second drain region 73 is located in the second well region 43.

[0097] In the present application, the first deep trench isolation structure and the second deep trench isolation structure are DTI (Deep trench isolation). The present application uses DTI as an additional gate to increase the current capability of the N-MOSFET device, and combines the advantages of the SOI process to achieve good isolation of various devices and avoid parasitic effects.

[0098] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing an integrated semiconductor device, It is characterized in that include: Providing a bottom silicon substrate, the bottom silicon substrate comprising a CMOS device region and an LDMOS device region, and an intermediate oxide layer and a top silicon substrate are sequentially formed on the bottom silicon substrate; Forming an epitaxial layer, wherein the epitaxial layer covers the top silicon substrate of the CMOS device area and the top silicon substrate of the LDMOS device area; forming a plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located in the epitaxial layers of the CMOS device region and the LDMOS device region and are spaced apart from each other; Etching the shallow trench isolation structure, the epitaxial layer, the top silicon substrate, the middle oxide layer and the bottom silicon substrate of the CMOS device area to form a first annular deep trench, and etching the shallow trench isolation structure, the epitaxial layer, the top silicon substrate, the middle oxide layer and the bottom silicon substrate of the LDMOS device area to form a second annular deep trench; forming an isolation layer, wherein the isolation layer covers the sidewalls and bottom wall of the first annular deep groove and the sidewalls and bottom wall of the second annular deep groove; Filling the first annular deep trench with polysilicon material to obtain a first annular deep trench isolation structure, and filling the second annular deep trench with polysilicon material to obtain a second annular deep trench isolation structure; A first well region and two buffer regions are formed in the epitaxial layer in the first annular deep trench isolation structure of the CMOS device region, and a body region, a drift region and a second well region are formed in the epitaxial layer in the second annular deep trench isolation structure of the LDMOS device region by an ion implantation process, wherein the buffer regions are all located in the first well region and are respectively located on the side of the shallow trench isolation structure, the body region and the drift region are arranged at intervals, and the second well region is located in the drift region; Forming a first gate and a second gate, wherein the first gate is located on the epitaxial layer between two buffer regions of the CMOS device region, and the second gate is located on the epitaxial layer between the body region and the drift region of the LDMOS device region; A first base region, a first source region and a first drain region are respectively formed in the CMOS device region, and a second base region, a second source region and a second drain region are respectively formed in the LDMOS device region by an ion implantation process, wherein part of the first source region is located in a buffer region, the remaining first source region is located in the first well region, the first base region is located in the middle of the first source region, and the first drain region is located in another buffer region; the second base region and the second source region are both located in the body region, the second base region is located in the middle of the second source region, and the second drain region is located in the second well region.

2. The method for preparing an integrated semiconductor device according to claim 1, It is characterized in that The lateral dimension of the second deep annular groove is at least twice the lateral dimension of the first deep annular groove.

3. The method for preparing an integrated semiconductor device according to claim 1, It is characterized in that The depth of the second annular deep groove is greater than the depth of the first annular deep groove.

4. The method for preparing an integrated semiconductor device according to claim 1, It is characterized in that After forming the first base region, the first source region and the first drain region, and the second base region, the second source region and the second drain region, the method for preparing the integrated semiconductor device further includes: Forming an interlayer insulating dielectric layer, wherein the interlayer insulating dielectric layer covers the first gate, the shallow trench isolation structure, the first annular deep trench and the epitaxial layer of the CMOS device area, and the second gate, the shallow trench isolation structure, the second annular deep trench and the epitaxial layer of the LDMOS device area; Etching the interlayer insulating dielectric layer to form a plurality of through holes; Filling metal material in the through hole to obtain a plurality of conductive plugs, wherein at least one of the conductive plugs is connected to the polysilicon material in the first annular deep trench, at least one of the conductive plugs is connected to the first gate, at least one of the conductive plugs is connected to the second base region, at least one of the conductive plugs is connected to the second gate, and at least one of the conductive plugs is connected to the second drain region; A patterned metal layer is formed, wherein the patterned metal layer at least covers the conductive plug and a portion of the interlayer insulating dielectric layer in the CMOS device area, and a portion of the interlayer insulating dielectric layer in the LDMOS device area, and each conductive plug in the LDMOS device area is respectively covered, wherein the patterned metal layer in the CMOS device area and the patterned metal layer in the LDMOS device area are not connected.

5. The method for preparing an integrated semiconductor device according to claim 1, It is characterized in that The steps of forming a plurality of shallow trench isolation structures include: Etching the epitaxial layers of the CMOS device region and the LDMOS device region to form a plurality of shallow trenches; An isolation material is filled in the shallow trenches to obtain a plurality of shallow trench isolation structures.

6. The method for preparing an integrated semiconductor device according to claim 1 or 5, It is characterized in that The shallow trench isolation structures penetrated by the first annular deep trench isolation structure and the second annular deep trench isolation structure are all annular; and the remaining shallow trench isolation structures located in the second annular deep trench isolation structure are all strip-shaped.

7. The method for preparing an integrated semiconductor device according to claim 1, It is characterized in that The conductivity type of the doped ions on the surface of the top silicon substrate is N type; the doped type of the epitaxial layer is N type; the conductivity type of the doped ions in the first well region is P type; the conductivity type of the doped ions in the buffer region is N type; the conductivity type of the doped ions in the body region is P type; the conductivity type of the doped ions in the drift region is N type, and the conductivity type of the doped ions in the second well region is N type; the conductivity type of the doped ions in the first base region is P type; the conductivity type of the doped ions in the first source region is N type; the conductivity type of the doped ions in the first drain region is N type; the conductivity type of the doped ions in the second base region is P type; the conductivity type of the doped ions in the second source region is N type; the conductivity type of the doped ions in the second drain region is N type.

8. The method for preparing an integrated semiconductor device according to claim 1, It is characterized in that The material of the isolation layer is silicon dioxide.

9. The method for preparing an integrated semiconductor device according to claim 1, It is characterized in that The thickness of the bottom silicon substrate is 750 μm to 800 μm; the thickness of the middle oxide layer is 0.4 μm to 0.8 μm; and the thickness of the top silicon substrate is 0.3 μm to 0.7 μm.

10. An integrated semiconductor device, It is characterized in that include: A bottom silicon substrate, wherein the bottom silicon substrate comprises a CMOS device region and an LDMOS device region, and an intermediate oxide layer and a top silicon substrate are sequentially formed on the bottom silicon substrate; An epitaxial layer, wherein the epitaxial layer covers the top silicon substrate of the CMOS device region and the top silicon substrate of the LDMOS device region; A plurality of shallow trench isolation structures, wherein the shallow trench isolation structures are located in the epitaxial layers of the CMOS device region and the LDMOS device region and are spaced apart from each other; A first annular deep trench, the first annular deep trench being located in a shallow trench isolation structure, an epitaxial layer, a top silicon substrate, an intermediate oxide layer and a partial thickness of a bottom silicon substrate in the CMOS device region; A second annular deep trench, wherein the second annular deep trench is located in the shallow trench isolation structure, the epitaxial layer, the top silicon substrate, the middle oxide layer and a partial thickness of the bottom silicon substrate of the LDMOS device region; an isolation layer, the isolation layer covering the side walls and bottom wall of the first annular deep groove and the side walls and bottom wall of the second annular deep groove; A polysilicon material, wherein the polysilicon material fills the first annular deep trench to obtain a first annular deep trench isolation structure, and fills the second annular deep trench to obtain a second annular deep trench isolation structure; A first well region, two buffer regions, a body region, a drift region, and a second well region, wherein the first well region and the two buffer regions are located in an epitaxial layer within a first annular deep trench isolation structure of the CMOS device region, and the body region, the drift region, and the second well region are located in an epitaxial layer within a second annular deep trench isolation structure of the LDMOS device region, wherein the buffer regions are all located in the first well region and are respectively located on the side of the shallow trench isolation structure, the body region and the drift region are spaced apart, and the second well region is located in the drift region; A first gate and a second gate, wherein the first gate is located on an epitaxial layer between two buffer regions of the CMOS device region, and the second gate is located on an epitaxial layer between a body region and a drift region of the LDMOS device region; A first base region, a first source region, a first drain region, a second base region, a second source region, and a second drain region, wherein, in the CMOS device region, part of the first source region is located in a buffer region, the remaining first source region is located in the first well region, the first base region is located in the middle of the first source region, and the first drain region is located in another buffer region; in the LDMOS device region, the second base region and the second source region are both located in the body region and the second base region is located in the middle of the second source region, and the second drain region is located in the second well region.

Images