Manufacturing method of SOI BCD process integrated SGT device

Abstract

The invention provides a manufacturing method of an SOI BCD process integrated SGT device, and the method comprises the steps: providing an SOI substrate of a first conduction type, the SOI substrate is composed of a substrate of the first conduction type, an oxide layer and a thin silicon layer which are sequentially stacked from bottom to top, and the substrate comprises a forming region of an MOS device of the first conduction type, a forming region of an LDMOS device and a forming region of an SGT device; removing the oxide layer and the thin silicon layer on the SGT device, and then forming an epitaxial layer of a first conductive type on the substrate; shallow trench isolation is formed on the epitaxial layer to define an active region, a first deep trench and a second deep trench are respectively formed on the epitaxial layer in the formation region of the MOS device of the first conductive type and the formation region of the LDMOS device, and the bottom ends of the first deep trench and the second deep trench extend to the substrate; and respectively forming a first deep trench isolation structure and a second deep trench isolation structure in the first deep trench and the second deep trench. According to the invention, the SGT device and the LDMOS device are integrated, a solution is provided for the manufacturing of the intelligent high-side switch chip, and the competitiveness is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a SOI BCD process integrated SGT device. Background Art

[0002] See also Figure 1 IPD is the abbreviation of Intelligent Power Device, which refers to a high-performance semiconductor power switch with a built-in protection circuit that can absorb energy from inductive loads, etc. It is also called a smart switch, high-side / low-side switch, etc. With the rise of software, autonomous driving, and functional safety, high-side switches are rapidly replacing fuses that have no software configuration function, low reliability, and no diagnostic function.

[0003] In order to solve the above problems, it is necessary to propose a novel method for manufacturing SGT devices integrated by SOI BCD process. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method for manufacturing an SGT device integrated with an SOI BCD process, so as to solve the problem that the high-side switch in the prior art is being rapidly replaced, has no software configuration function, and has low reliability.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing an SOI BCD process integrated SGT device, comprising:

[0006] Step 1, providing a first conductive type SOI substrate, which is composed of a first conductive type substrate, an oxide layer and a thin silicon layer stacked in sequence from bottom to top, the substrate including a formation region for a first conductive type MOS device, a formation region for an LDMOS device and a formation region for an SGT device, removing the oxide layer and the thin silicon layer on the SGT device, and then forming a first conductive type epitaxial layer on the substrate;

[0007] Step 2, forming shallow trench isolation on the epitaxial layer to define an active area, and forming first and second deep trenches on the epitaxial layer of the formation area of ​​the first conductive type MOS device and the formation area of ​​the LDMOS device, respectively, wherein the bottom ends of the first and second deep trenches extend to the substrate;

[0008] Step 3, forming a first deep trench isolation structure and a second deep trench isolation structure in the first deep trench and the second deep trench, respectively; the first deep trench isolation structure is used to isolate the MOS device of the first conductivity type from other devices, and the second deep trench isolation structure is used to isolate the LDMOS device from other devices;

[0009] Step 4: forming a partial structure of an SGT device on the epitaxial layer, which includes:

[0010] A first trench formed on the epitaxial layer and a second trench located at a side of the first trench;

[0011] forming a first dielectric layer and a first gate polysilicon layer in the first and second trenches, wherein the first dielectric layer and the first gate polysilicon layer are located at the lower end of the first trench and in the second trench;

[0012] an isolation dielectric layer formed on the first gate polysilicon layer in the first;

[0013] a second dielectric layer formed in the first trench and on the epitaxial layer;

[0014] a second gate polysilicon layer filling the remaining first trench;

[0015] forming a first well of a second conductivity type of the SGT device on the epitaxial layer by ion implantation;

[0016] Step 5: forming a body region, a drift region, and a third well of the first conductivity type formed on the drift region of the LDMOS device by ion implantation, wherein a lateral spacing exists between the body region and the drift region; and a second well of the second conductivity type and a lightly doped drain of the MOS device of the first conductivity type;

[0017] Step 6: forming a first gate structure of an LDMOS device and a second gate structure of a MOS device of the first conductivity type on the epitaxial layer, wherein one end of the first gate structure extends to the body region, and the other end thereof extends to the shallow trench isolation on the adjacent drift region; forming a heavily doped region on the first well of the second conductivity type, the third well of the first conductivity type, the body region, and the lightly doped drain; the heavily doped region on the third well of the first conductivity type serves as the drain of the LDMOS device, and the heavily doped region on the body region serves as the source of the LDMOS device; the heavily doped region on the first well of the second conductivity type serves as the source of the SGT device; the heavily doped region on the lightly doped drain serves as the source and drain of the MOS device of the first conductivity type, respectively, and the second gate structure is self-aligned with the source and drain of the MOS device of the first conductivity type;

[0018] Step 7: forming a metal interconnect structure for leading out the first conductivity type MOS device, LDMOS device and SGT device on the front side of the substrate; and forming a metal layer as a drain terminal of the SGT device on the back side of the substrate.

[0019] Preferably, in step 1, the oxide layer and the thin silicon layer on the SGT device are removed by photolithography and etching methods.

[0020] Preferably, in step 2, the opening size of the first deep trench is smaller than the opening size of the second deep trench.

[0021] Preferably, in step 2, the first and second deep trenches with different opening sizes are formed in the same photolithography and etching process.

[0022] Preferably, the opening size of the second deep groove in step 2 is twice the opening size of the first deep groove.

[0023] Preferably, the method for forming the first and second deep trench isolation structures in step three includes: forming a sidewall oxide layer located on the first and second deep trenches; and forming a polysilicon layer filling the remaining first and second deep trenches by deposition and grinding methods.

[0024] Preferably, the method of forming a partial structure of the SGT device on the epitaxial layer in step four includes: forming the first dielectric layer and the first gate polysilicon layer in the first and second trenches, wherein the first dielectric layer and the first gate polysilicon layer are located at the lower end of the first trench and in the second trench; forming the isolation dielectric layer filling the remaining first trench, grinding the isolation dielectric layer onto the epitaxial layer, etching the isolation dielectric layer in the first trench so that part of it remains on the first gate polysilicon layer therein; forming a second dielectric layer on the epitaxial layer and in the first trench, and then forming the second gate polysilicon layer filling the remaining first trench.

[0025] Preferably, the etching method in step 4 is dry etching.

[0026] Preferably, the first and second wells, the third well of the first conductivity type, the heavily doped region on the body region, and the lightly doped drain in step six are formed in the same ion implantation, and the doping type thereof is the first conductivity type.

[0027] Preferably, step six further comprises forming a substrate lead-out region on the body region and a second well of the second conductivity type.

[0028] Preferably, the polysilicon layer and the second gate structure in step seven are simultaneously led out to one end.

[0029] Preferably, step seven further includes thinning the back side of the substrate before forming the metal layer on the back side of the substrate.

[0030] Preferably, in step seven, the substrate is thinned by chemical mechanical planarization grinding.

[0031] Preferably, the first conductivity type is N type, and the second conductivity type is P type.

[0032] Preferably, the first conductivity type is P type, and the second conductivity type is N type.

[0033] As described above, the method for manufacturing an SOI BCD process integrated SGT device of the present invention has the following beneficial effects:

[0034] The present invention adopts a structure combining DTI (deep trench) and SOI to form full dielectric isolation, which can achieve higher anti-EMI (electromagnetic interference) capability, completely eliminate parasitic bipolar effect, eliminate the risk of latch-up and improve the circuit working reliability. Due to the extremely low RSP (parasitic resistance), high temperature reliability and saturation zone working reliability of SGT (shielded gate) devices, the higher demand of MOSFET for vehicle-mounted intelligent high-side switches can be met. The present invention integrates SGT devices with LDMOS devices to provide a solution for the manufacture of intelligent high-side switch chips and enhance competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Shown is a schematic diagram of a high-side switch of the prior art;

[0036] Figure 2 Shown is a schematic diagram of the process flow of the present invention;

[0037] Figure 3 Shown is a schematic diagram of the SOI substrate of the present invention;

[0038] Figure 4 Shown is a schematic diagram of etching an SOI substrate according to the present invention;

[0039] Figure 5 Shown is a schematic diagram of forming an epitaxial layer of the present invention;

[0040] Figure 6 It is a schematic diagram showing a deep trench isolation structure formed according to the present invention;

[0041] Figure 7 Shown is a schematic diagram of a polished isolation dielectric layer of the present invention;

[0042] Figure 8 It is a schematic diagram of etching the isolation dielectric layer of the present invention;

[0043] Fig. 9 Shown is a partial structural schematic diagram of a SGT device formed according to the present invention;

[0044] Fig.10It is a schematic diagram showing the body region, the drift region, the third well formed on the drift region, the second well and the lightly doped drain of the MOS device formed according to the present invention;

[0045] Fig.11 It is a schematic diagram of forming a heavily doped region and a gate structure according to the present invention. DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] See also Figure 2 The present invention provides a method for manufacturing an SGT device integrated by SOI BCD (a single chip integrated process technology, which can manufacture bipolar, CMOS and DMOS devices on the same chip) process, comprising:

[0048] Step 1: Provide a first conductive type SOI substrate, which is composed of a first conductive type substrate 101, an oxide layer 102 and a thin silicon layer stacked in sequence from bottom to top to form a Figure 3 The structure shown in FIG. 1 includes a formation region of a MOS device of the first conductivity type, a formation region of an LDMOS device, and a formation region of an SGT device on the substrate. The oxide layer 102 and the thin silicon layer on the SGT device are removed to form a substrate as shown in FIG. Figure 4 The structure shown in FIG. 1 is then formed on the substrate, and an epitaxial layer 104 of the first conductivity type is formed. Figure 5 The structure shown;

[0049] In some embodiments, in step 1, the oxide layer 102 and the thin silicon layer on the SGT device are removed by photolithography and etching, and the etching method is dry etching.

[0050] In some embodiments, the first conductivity type is N-type, and the second conductivity type is P-type.

[0051] In some embodiments, the first conductivity type is P type, and the second conductivity type is N type.

[0052] Step 2: forming a shallow trench isolation 125 on the epitaxial layer 104 to define an active region, and forming a first deep trench and a second deep trench on the epitaxial layer 104 in the formation region of the first conductivity type MOS device and the formation region of the LDMOS device, respectively, wherein the bottom ends of the first deep trench and the second deep trench extend to the substrate; the first deep trench and the second deep trench are formed by photolithography and etching;

[0053] In some embodiments, the opening size of the first deep trench in step 2 is smaller than the opening size of the second deep trench.

[0054] In some embodiments, in step 2, the first and second deep trenches with different opening sizes are formed by the same photolithography and etching.

[0055] In some embodiments, the opening size of the second deep trench in step 2 is twice the opening size of the first deep trench.

[0056] Step 3: forming the first and second deep trench isolation structures in the first and second deep trenches respectively, forming Figure 6 The structure shown; the first deep trench isolation structure is used to isolate the MOS device of the first conductivity type from other devices, and the second deep trench isolation structure is used to isolate the LDMOS device from other devices;

[0057] In some embodiments, the method for forming the first and second deep trench isolation structures in step three includes: forming a sidewall oxide layer 105 located on the first and second deep trenches; forming a polysilicon layer 106 filling the remaining first and second deep trenches by deposition and grinding methods, and the grinding method is usually chemical mechanical planarization grinding.

[0058] Step 4: forming a partial structure of the SGT device on the epitaxial layer 104, forming Fig. 9 The structure shown comprises:

[0059] A first trench formed on the epitaxial layer 104 and a second trench located at a side of the first trench;

[0060] Forming a first dielectric layer 107 and a first gate polysilicon layer 108 in the first and second trenches, wherein the first dielectric layer 107 and the first gate polysilicon layer 108 are located at the lower end of the first trench and in the second trench;

[0061] An isolation dielectric layer 109 formed on the first gate polysilicon layer 108;

[0062] a second dielectric layer 110 formed in the first trench and on the epitaxial layer 104;

[0063] A second gate polysilicon layer 111 filling the remaining first trench;

[0064] Forming a first well 112 of a second conductivity type of the SGT device on the epitaxial layer 104 by ion implantation;

[0065] In some embodiments, the method of forming a partial structure of the SGT device on the epitaxial layer 104 in step 4 includes: forming a first dielectric layer 107 and a first gate polysilicon layer 108 in the first and second trenches, wherein the first dielectric layer 107 and the first gate polysilicon layer 108 are located at the lower end of the first trench and in the second trench; forming an isolation dielectric layer 109 filling the remaining first trench, grinding the isolation dielectric layer 109 onto the epitaxial layer 104, and forming Figure 7 The structure shown in FIG. 1 is formed by etching the isolation dielectric layer 109 in the first trench so that a portion of the isolation dielectric layer 109 remains on the first gate polysilicon layer 108 therein. Figure 8 The structure shown; a second dielectric layer 110 is formed on the epitaxial layer 104 and in the first trench, and then a second gate polysilicon layer 111 is formed to fill the remaining first trench, forming a Fig. 9 In the structure shown, the second gate polysilicon layer 111 can be formed by deposition and grinding methods.

[0066] In some embodiments, the etching method in step 4 is dry etching.

[0067] Step 5: Form the body region 115, the drift region 113, and the third well 114 of the first conductivity type formed on the drift region 113 of the LDMOS device by ion implantation, wherein the body region 115 and the drift region 113 have a lateral spacing, the drift region 113 is of the first conductivity type, and the body region is of the second conductivity type; and the second well 116 of the second conductivity type and the lightly doped drain 117 of the first conductivity type MOS device, so as to form Fig.10 The structure shown;

[0068] Step 6: Form a first gate structure 124 of an LDMOS device and a second gate structure 123 of a MOS device of the first conductivity type on the epitaxial layer 104, wherein one end of the first gate structure 124 extends to the body region 115, and the other end thereof extends to the shallow trench isolation 125 on the adjacent drift region 113; form a heavily doped region located on the first well 112 of the second conductivity type, the third well 114 of the first conductivity type, the body region 115, and the lightly doped drain 117, wherein the heavily doped region is of the first conductivity type; the heavily doped region 122 on the third well 114 of the first conductivity type serves as the drain of the LDMOS device, and the heavily doped region 121 on the body region 115 serves as the source of the LDMOS device; the heavily doped region 126 on the first well 112 of the second conductivity type serves as the source of the SGT device; the heavily doped regions (127, 118) on the lightly doped drain 117 serve as the source and drain of the MOS device of the first conductivity type, respectively, and the second gate structure 123 is self-aligned with the source and drain of the MOS device of the first conductivity type, so as to form a structure as follows: Fig.11 The structure shown;

[0069] The first conductivity type of the MOS region can be implanted with the first conductivity type to help the first conductivity type of the MOS form a vertical conductive channel. Fig.11 The dotted line in FIG. 1 shows the current conduction path of the first conductive type MOS of the SOI, which improves the saturation current capability of the MOS device.

[0070] In some embodiments, the first and second wells, the third well 114 of the first conductivity type, the heavily doped region on the body region 115 , and the lightly doped drain 117 in step six are formed in the same ion implantation.

[0071] In some embodiments, step six further includes forming a substrate lead-out region (120, 119) on the body region 115 and the second well 116 of the second conductivity type, and the substrate lead-out region (120, 119) is of the second conductivity type.

[0072] Step 7: forming a metal interconnection structure for leading out the first conductivity type MOS device, LDMOS device and SGT device on the front side of the substrate; and forming a metal layer as a drain terminal of the SGT device on the back side of the substrate.

[0073] In some embodiments, the polysilicon layer 106 and the second gate structure 123 in step seven are simultaneously led out to one end.

[0074] In some embodiments, before forming the metal layer on the back side of the substrate in step seven, the back side of the substrate is also thinned.

[0075] In some embodiments, in step seven, the substrate is thinned by chemical mechanical planarization.

[0076] The interconnect structure includes various conductive components to connect various IC devices to the integrated circuit. The interconnect structure also includes an interlayer dielectric (ILD) layer to separate and isolate various conductive components. For example, the interconnect structure includes contacts; metal lines; and through holes. The metal lines are distributed in multiple metal layers. For example, the metal lines may include copper, aluminum-copper alloys, other suitable conductive materials, or combinations thereof. The through holes may include copper, aluminum-copper alloys, other suitable conductive materials, or combinations thereof. The contacts may include tungsten, silicide, nickel, cobalt, copper, other suitable conductive materials, or combinations thereof. In some instances, the various conductive components may further include barrier layers such as tantalum and tantalum nitride, titanium and titanium nitride.

[0077] The ILD layer includes one or more dielectric materials to provide isolation functions to various device components (such as gates) and various conductive components (such as metal lines, contacts and vias). The ILD layer includes dielectric materials such as silicon oxide, low-k dielectric materials, other suitable dielectric materials or combinations thereof. In some instances, low-k dielectric materials include fluorinated silicon glass (FSG), carbon-doped silicon oxide, xerogels, aerogels, amorphous fluorinated carbon, polyparaxylene, BCB (bisbenzocyclobutene), polyimide and / or other suitable dielectric materials having a dielectric constant substantially less than that of thermal silicon oxide. For example, the formation of the ILD layer includes deposition and CMP. Deposition may include spin coating, CVD, other suitable deposition techniques or combinations thereof. The ILD layer may include multiple layers and may be formed together with various conductive components with appropriate procedures (such as damascene processes).

[0078] In some embodiments, the interconnect structure or its part is formed by deposition and patterning. For example, a metal (or metal alloy) such as aluminum copper is deposited by physical vapor deposition (PVD), and then patterned by photolithography and etching. Then the ILD layer is set by deposition (and CMP). In some embodiments, the interconnect structure uses a damascene process to form a metal line. In the damascene process, the ILD layer is deposited, the ILD layer is further flattened by CMP, and then patterned by photolithography and etching to form a groove. One or more conductive materials are deposited to fill the groove, and another CMP process is applied to remove excess conductive materials and flatten the top surface, thereby forming a conductive component. The damascene process can be used to form a metal line, a through hole and a contact. A dual damascene process can be applied to form a layer of metal line and a through hole adjacent to the metal line. In this case, the ILD layer is deposited and patterned twice to form a groove and a through hole respectively. Then metal is deposited to fill both the groove and the through hole to form a metal line and a through hole.

[0079] The present invention adopts a structure combining DTI (deep trench) and SOI to form full dielectric isolation, which can achieve higher anti-EMI (electromagnetic interference) capability, completely eliminate parasitic bipolar effect, eliminate the risk of latch-up and improve the circuit working reliability. Due to the extremely low RSP (parasitic resistance), high temperature reliability and saturation zone working reliability of SGT (shielded gate) devices, the higher demand of MOSFET for vehicle-mounted intelligent high-side switches can be met. The present invention integrates SGT devices with LDMOS devices to provide a solution for the manufacture of intelligent high-side switch chips and enhance competitiveness.

[0080] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0081] In summary, the present invention adopts a structure combining DTI (deep trench) and SOI to form full dielectric isolation, which can achieve higher anti-EMI (electromagnetic interference) capability, completely eliminate parasitic bipolar effects, eliminate the risk of latch-up, and improve the circuit working reliability. Due to the extremely low RSP (parasitic resistance) of the SGT (shielded gate) device, high temperature reliability and saturation zone working reliability, it can meet the higher demand of the vehicle-mounted intelligent high-side switch for MOSFET. The present invention integrates the SGT device with the LDMOS device to provide a solution for the manufacture of intelligent high-side switch chips and enhance competitiveness. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a SGT device integrated by a SOIBCD process, characterized in that: At least: Step 1, providing a first conductive type SOI substrate, which is composed of a first conductive type substrate, an oxide layer and a thin silicon layer stacked in sequence from bottom to top, the substrate including a formation region for a first conductive type MOS device, a formation region for an LDMOS device and a formation region for an SGT device, removing the oxide layer and the thin silicon layer on the SGT device, and then forming a first conductive type epitaxial layer on the substrate; Step 2, forming shallow trench isolation on the epitaxial layer to define an active area, and forming first and second deep trenches on the epitaxial layer of the formation area of ​​the first conductive type MOS device and the formation area of ​​the LDMOS device, respectively, wherein the bottom ends of the first and second deep trenches extend to the substrate; Step 3, forming a first deep trench isolation structure and a second deep trench isolation structure in the first deep trench and the second deep trench, respectively; the first deep trench isolation structure is used to isolate the MOS device of the first conductivity type from other devices, and the second deep trench isolation structure is used to isolate the LDMOS device from other devices; Step 4: forming a partial structure of an SGT device on the epitaxial layer, which includes: A first trench formed on the epitaxial layer and a second trench located at a side of the first trench; forming a first dielectric layer and a first gate polysilicon layer in the first and second trenches, wherein the first dielectric layer and the first gate polysilicon layer are located at the lower end of the first trench and in the second trench; an isolation dielectric layer formed on the first gate polysilicon layer in the first; a second dielectric layer formed in the first trench and on the epitaxial layer; a second gate polysilicon layer filling the remaining first trench; forming a first well of a second conductivity type of the SGT device on the epitaxial layer by ion implantation; Step 5: forming a body region, a drift region, and a third well of the first conductivity type formed on the drift region of the LDMOS device by ion implantation, wherein a lateral spacing exists between the body region and the drift region; and a second well of the second conductivity type and a lightly doped drain of the MOS device of the first conductivity type; Step 6: forming a first gate structure of an LDMOS device and a second gate structure of a MOS device of the first conductivity type on the epitaxial layer, wherein one end of the first gate structure extends to the body region, and the other end thereof extends to the shallow trench isolation on the adjacent drift region; forming a heavily doped region on the first well of the second conductivity type, the third well of the first conductivity type, the body region, and the lightly doped drain; the heavily doped region on the third well of the first conductivity type serves as the drain of the LDMOS device, and the heavily doped region on the body region serves as the source of the LDMOS device; the heavily doped region on the first well of the second conductivity type serves as the source of the SGT device; the heavily doped region on the lightly doped drain serves as the source and drain of the MOS device of the first conductivity type, respectively, and the second gate structure is self-aligned with the source and drain of the MOS device of the first conductivity type; Step 7: forming a metal interconnect structure for leading out the first conductivity type MOS device, LDMOS device and SGT device on the front side of the substrate; and forming a metal layer as a drain terminal of the SGT device on the back side of the substrate.

2. The method for manufacturing a SOIBCD integrated SGT device according to claim 1, characterized in that: In step 1, the oxide layer and the thin silicon layer on the SGT device are removed by photolithography and etching.

3. The method for manufacturing a SOIBCD integrated SGT device according to claim 1, characterized in that: In step 2, the opening size of the first deep trench is smaller than the opening size of the second deep trench.

4. The method for manufacturing a SGT device integrated by SOIBCD process according to claim 3, characterized in that: In step 2, the first and second deep trenches with different opening sizes are formed by the same photolithography and etching.

5. The method for manufacturing a SOIBCD integrated SGT device according to claim 3, characterized in that: The opening size of the second deep trench in step 2 is twice the opening size of the first deep trench.

6. The method for manufacturing a SOIBCD integrated SGT device according to claim 1, characterized in that: The method for forming the first and second deep trench isolation structures in step three includes: forming a sidewall oxide layer located on the first and second deep trenches; and forming a polysilicon layer filling the remaining first and second deep trenches by deposition and grinding methods.

7. The method for manufacturing a SOIBCD integrated SGT device according to claim 1, characterized in that: The method of forming a partial structure of the SGT device on the epitaxial layer in step four includes: forming the first dielectric layer and the first gate polysilicon layer in the first and second trenches, wherein the first dielectric layer and the first gate polysilicon layer are located at the lower end of the first trench and in the second trench; forming the isolation dielectric layer filling the remaining first trench, grinding the isolation dielectric layer onto the epitaxial layer, etching the isolation dielectric layer in the first trench so that part of it remains on the first gate polysilicon layer therein; forming a second dielectric layer on the epitaxial layer and in the first trench, and then forming the second gate polysilicon layer filling the remaining first trench.

8. The method for manufacturing a SGT device integrated by SOIBCD process according to claim 7, characterized in that: The etching method in step 4 is dry etching.

9. The method for manufacturing a SOIBCD integrated SGT device according to claim 1, characterized in that: The first and second wells, the third well of the first conductivity type, the heavily doped region on the body region, and the lightly doped drain in step six are formed in the same ion implantation, and the doping type thereof is the first conductivity type.

10. The method for manufacturing a SOIBCD integrated SGT device according to claim 1, characterized in that: Step six also includes forming a substrate lead-out region on the body region and a second well of the second conductivity type.

11. The method for manufacturing a SOI BCD process integrated SGT device according to claim 6, characterized in that: The polysilicon layer and the second gate structure in step seven are simultaneously led out to one end.

12. The method for manufacturing a SOIBCD integrated SGT device according to claim 1, characterized in that: In step seven, before forming the metal layer on the back side of the substrate, the back side of the substrate is thinned.

13. The method for manufacturing a SOIBCD integrated SGT device according to claim 12, characterized in that: In step seven, the substrate is thinned by chemical mechanical planarization and polishing.

14. The method for manufacturing a SGT device integrated by a SOIBCD process according to any one of claims 1 to 13, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

15. The method for manufacturing a SGT device integrated by a SOIBCD process according to any one of claims 1 to 13, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.

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